Samuel Silverstein, Stockholm University

Phase-1 L1Calo and L1Topo overview

Overview PreProcessor upgrade JEM upgrade CMX L1Topo

2

Phase-1 planning overview

Central TriggerL1Topo CTP

CORE

CMX

nMCM

CMX

Calorimeter Trigger

Preprocessor

Electron/Tau

Jet/Energy

AnalogueSignals

Muon TriggerBarrel Sector Logic

Endcap Secto r Logic

MuCTPi

Prop osedNew Electronics

New SW

PhaseI LarFex25Jul11

NewDigitalTBB

DIgitalPreprocessor

FeatureExtractor

DAQ DAQ

EM calorimeterdigital readout

Muon detector

EM & hadroniccalorimeters

L1accept

Hadronic layerfrom JEMs

3

PreProcessor upgrade(s)

MCM replacement (nMCM) Drop-in replacement for existing

MCMs FPGA allows new functionality

Improved filtering, test pulses, etc.

Other upgrade possibilities LVDS driver card

Send 0.10.1 trigger towers to upgraded JEM, or...

Send hadronic layer information directly to FEX

AnIn board New version to receive

multiplexed analog signals from TileCal A-layer (less likely)

4

JEM hardware upgrades

Physics motivation: FEX(s) require digital EM and hadronic layer data, but

TileCal upgrade not expected until Phase 2. Upgraded JEM can extract hadronic layer from

L1Calo real time data path for Phase1 use in FEX Upgrade idea:

Replace input and Glink daughter cards with new modules containing fast, modern FPGAs

Speed up readout data path to send data from input links to Glink card in real-time

New optical connectors on G-link card send real-time data serially to FEX

Double link speed from PPM to JEM to send 0.10.1 tower data to JEP.

5

JEM Upgrade possibilities

Receive finergranularity data

from nMCM?

Increased bandwidthto new DAQ interface:send input tower sums

Send hadronic layerto FEX

More logic and LUTsin input FPGAs:

enhanced energysum algorithms?

6

CMX

Most well-defined upgrade project Successful review in June (Stockholm) Engineering studies underway (see Yuri's talk)

Multiple operational modes possible Drop-in CMM replacement ('CMM emulation') Data source for L1Topo (main functionality) Topological processing capabilities if L1Topo is

somehow delayed (subject to cost-benefit study) Hardware studies and firmware develop are

needed for all of these Some effort from other institutes

7

CMM and CMX

8

To DAQ +ROI RODs

TP readoutto RODs

Backplane(400b)

DECODE

CMMEmulation

400b

RTM cables(3 25b)

TTCdec L1A, BCrst,Des1,Des2,etc

SER960Mb/sReadout

(2 24b)

CTP

CTP output

TP formatbuilder

SER6.4 Gb/s To TP

CTP cables(2 33b)

DES6.4 Gb/s

SER960Mb/s

Topologicalprocessing

CLKExt PLL

Des1,Des2,Xtal, L1A, BCRes

XTAL

Readout(2 24b)

Des1,Des2,Xtal, L1A, BCRes

TPInputs

CPLDVME--

AxxD16

CMX firmware (example)

Grey boxes may be goodareas for other institutesto contribute. See laterfirmware talks....

9

New backplane formats

Data formats from JEM and CMM proposed months ago Contents fairly well agreed (?)

"Presence" bits Fine coordinates Threshold bits ET value (?)

Simulation studies assume realistic data availability

Should converge soon on "exact" formats Important to develop prototype firmware in

advance of CMX final design review....

10

L1 Topological Processor

Central to Phase 1 plans (and possibly longer term) But architecture still not well defined...

Few discussions within L1Calo community Would like to benefit from GOLD results (delayed) Prototype firmware needed to validate architectural

concepts But need to have some idea of architecture to write realistic

prototype firmware, leading to chicken/egg situation... Whiteboard discussion yesterday...

Helped pin down some design parameters Different architectural ideas floated Discussed balance between maximizing L1Topo input

bandwidth vs. bandwidth reduction at source

11

Design parameters Link speeds from CMX to L1Topo

Current CMX assumption is 6.4 Gbit/s, Virtex 6 HXT But HXT can also drive some 9.6 Gbit/s links, and soon

available Virtex-7 devices can drive all links at 9.6 Mainz has Avago TX/RX pairs that can run at 10 Gbit/s Are 9.6 Gbit/s links from CMX to L1Topo conceivable?

Link multiplicities To send uncompressed backplane data from CMX

12 fibers/CMX at 6.4 Gbit/s 8 fibers/CMX at 9.6 Gbit/s

From 12 CMX modules, output to L1Topo would be: 144 fibers at 6.4 Gbit/s 96 fibers at 9.6 Gbit/s But maximum single FPGA-input is around ~80 fibers!

These numbers don't include ROIs from muons or FEX

12

Design parameters (2) Conclusions

To receive all topology data in a single FPGA (desirable for lower latency), bandwidth reduction needed at the source

Alternative: two FPGAs receiving and sharing unreduced input data:

FPGA

FPGA

72-80

72-80

Parallel links

13

Alternative architectures

O/E conversion on RTM(similar to FEX concept)

Outputto CTPUp to 12

parallel O/Emodules onRTM

L1Topo FPGAs(processing in

parallel)

Electrical connectionsto the main module

Readout FPGA

O/E conversion on main module(concept tested in GOLD)

Output fibers/cablesto CTP

L1 Topo FPGAs(processing in

parallel)

Optical feed-thruof fiber links tothe main module

Readout FPGA

Whatever architecture chosen, would like it to be modular and scalable

14

L1Topo firmware concept

Algorithm 1

TM(, MET)

Algorithm 2

e + Jets,non-overlap

Algorithm 3

(e, e)

CTP output

Algorithms select and process data in parallel

Parallel output to CTP

Roi DeSer and extraction

RoIs Jet RoIs Cluster RoIsET, MET FEX RoIs

Architecture should allow different collaborators todevelop modular algorithm tools that work side-by-side

15

Upcoming talks

Digital calorimeter triggers and FEX Hardware and firmware work around

the institutes Firmware development Technology developments relevant to

L1Calo upgrade