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PGAxxxEVM-034 User’s Guide

User's GuideSLDU011A–May 2015–Revised June 2016

PGAxxxEVM-034 User’s Guide

The PGAxxxEVM-034 provides a platform to test the PGA900 and PGA300 in the QFN package. TheEVM comes shipped as either the PGA900EVM-034 or PGA300EVM-034, with the name indicating theassociated part included with the EVM. The PGAxxxEVM-034 can be used interchangeably for bothdevices.

Contents1 Introduction ................................................................................................................... 22 Default Configuration ........................................................................................................ 33 Inputs and Output Configurations ......................................................................................... 4

3.1 Pressure Input....................................................................................................... 43.2 Temperature Input .................................................................................................. 43.3 Output ................................................................................................................ 43.4 Voltage Mode........................................................................................................ 53.5 Current Mode........................................................................................................ 63.6 OWI and SPI/I2C/SWD in 4- to 20-mA Current Loop........................................................... 7

4 OWI .......................................................................................................................... 104.1 Activation Pulse.................................................................................................... 114.2 Data Sent Through OWI.......................................................................................... 12

5 XDS200 and USB2ANY Connectors .................................................................................... 136 Power Supplies in the PGAxxxEVM-034................................................................................ 167 Schematics.................................................................................................................. 17

List of Figures

1 PGAxxxEVM-034 ............................................................................................................ 22 Pressure Stimulus in the PGAxxxEVM-034 .............................................................................. 43 PGA900 in Voltage Mode Configuration.................................................................................. 54 PGAxxxEVM-034 in Current Mode ........................................................................................ 65 Additional Loop Current in 4- to 20-mA Mode When Using SPI/I2C/SWD as Digital Interface .................. 86 Additional Loop Current in 4- to 20-mA Mode When Using OWI as Digital Interface .............................. 97 OWI Block Diagram ........................................................................................................ 108 OWI Activation Pulse for the PGA900 Generated by the PGAxxxEVM-034 in Voltage Mode................... 119 OWI Data at 320 bps; Oscilloscope Probe is Connected at TP20 in the PGAxxxEVM-034 ..................... 1210 XDS200 Emulator Connection to the PGAxxxEVM-034 .............................................................. 1311 USB2ANY Connection to the PGAxxxEVM-034 ....................................................................... 1412 USB2ANY ................................................................................................................... 1413 USB2ANY Pinout........................................................................................................... 1514 Power Distribution in PGAxxxEVM-034 ................................................................................. 1615 PGAxxxEVM-034 Main Schematic....................................................................................... 1716 Input and Output Schematic .............................................................................................. 1817 USB2ANY Schematic...................................................................................................... 1918 OWI Activation Pulse and Data Schematic ............................................................................. 2019 OWI Power Amplifier Schematic ......................................................................................... 2120 Power Supplies Schematic................................................................................................ 22

XDS200

Output &

Communication

Mode

Resistive

Bridge

Interface

One-Wire

Interface

Power

USB2ANY

Typical

Application

Components

Resistive

Bridge

Emulator

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PGAxxxEVM-034 User’s Guide

1 IntroductionFigure 1 shows the PGAxxxEVM-034 and its main sections.

Figure 1. PGAxxxEVM-034

www.ti.com Default Configuration

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PGAxxxEVM-034 User’s Guide

The PGAxxxEVM-034 is divided into six sections:1. Interface boards and external power:

(a) USB2ANY connector(b) XDS200 connector (single wire debugger)(c) Banana connectors to power up EVM

2. Power:(a) 7.5-V, 5-V, and 3.3-V regulators

3. Mode selection:(a) 4- to 20-mA loop (current mode)(b) Voltage mode

4. OWI circuitry5. Resistive bridge6. Application components

The applications components section highlights the only required components needed in a real lifeapplication using the PGA900/PGA300. In this case, the application is configured for current mode.

NOTE: The PGA900 and PGA300 have different features and pin functions and some circuitry andcommunication features found on the PGAxxxEVM-034 are only applicable to the PGA900.Additionally, each device has its own unique Graphical User Interface (GUI) thatcommunicates with the included USB2ANY board.

2 Default ConfigurationThe EVM requires a 10- to 30-V input applied to J20 and J21. Clamp the power supply current to 100 mA.The EVM is shipped configured for voltage mode as shown in Table 1.

Table 1. Jumper Settings for PGAxxxEVM-034 in Voltage Mode

Jumper Setting FunctionJ12 Closed PGAxxx powered up from OWI circuitry (VDD = 5 V)J1, J2, J3 Closed Connect resistive bridge to PGA900J6, J7, J8 Closed Voltage mode with a 100-nF loadJ24, J25, J26, J27, J28, J30 Closed SPI/I2C/UART enabled (only applicable to PGA900)J16 Closed Connect ASIC_GND to IRETURNJ14 Pins 1-2 closed Connect VDD cap to ASIC_GNDJ19 Pins 2-3 closed Connect USBGND to IRETURN

4.7 kQ

4.99 kQ 4.99 kQ

4.99 kQ

VBRGP

VBRGN

J2

J3

RC filter

RC filter

PGA900

VINPP

VINPN

J1

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3 Inputs and Output Configurations

3.1 Pressure InputThe PGAxxxEVM-034 consists of a resistive bridge where one leg of the bridge can be changed using adigital potentiometer. The changing leg consists of two digital potentiometers connected in parallel inseries with a 4.7-kΩ resistor. J1 must be closed to connect the bridge voltage from the PGA900 to theresistive bridge. In addition, J2 and J3 must be closed to connect the bridge outputs to the PGAxxx. AnRC filter is in series with each of the input pins in the PGAxxx with a cutoff frequency of about 106 Hz.Figure 2 shows the pressure stimulus circuit in the PGAxxxEVM-034.

Figure 2. Pressure Stimulus in the PGAxxxEVM-034

3.2 Temperature InputThe PGAxxxEVM-034 does not have on-board stimulus for the temperature inputs of the PGAxxx.However, TP27 and TP29 on the far right side of the board can be used to apply external signals.

3.3 OutputThe PGAxxxEVM-034 can be configured for voltage or current mode (4- to 20-mA loop). Each moderequires different jumper settings as described in the following sections.

110 Q

560 pF

VOUT

COMP

FBN

100 nF

PGA900

FBP

AVSS

DVSS

GND

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3.4 Voltage ModeThe PGAxxxEVM-034 is by default configured in voltage mode with a 100-nF load. A compensationcapacitor and an isolation resistor are needed for stability. Figure 3 shows the PGAxxx schematic forvoltage mode and Table 1 shows all the jumpers needed to configure the board in this mode. If thecapacitive load is different from 100 nF, then the isolation resistor and compensation capacitor valuesneed to be changed. Refer to application note PGA900 as a Capacitive Load Driver (SLDA020) for moreinformation.

Figure 3. PGA900 in Voltage Mode Configuration

NOTE: If the designer needs VDD to be more than 5 V in voltage mode, open J12 and close J13.VDD will be equal to the power applied to the PGAxxxEVM-034.

VOUT

COMP

FBN

PGA900

FBP

AVSS

DVSS

GND

150 Q

VDD

10 Q

OWI

J20

J21

PGA900EVMJ12

J13

USB2ANY

J16

PC

ASICGND IRETURN

J19

ASICGND IRETURN

USBGND

J16: Open for current mode

J16: Closed for

x Voltage mode

x SPI/I2C/SWD communication

J19: USBGND to IRETURN for OWI in current mode

J19: USBGND to ASICGND for SPI/I2C/SWD in current mode

PWR

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3.5 Current ModeWhen in current mode, the PGAxxxEVM-034 needs to be properly configured to separate the differentnegative references for all the voltage levels present in the board. Figure 4 shows the main connectionsfor current mode. The two different scenarios when in current mode are:• Current mode using OWI• Current mode using SPI/I2C/SWD (only applicable to the PGA900)

Figure 4. PGAxxxEVM-034 in Current Mode

NOTE: When in current mode, the input voltage to the EVM (J20 and J21) should be at least 20 V.

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PGAxxxEVM-034 User’s Guide

3.6 OWI and SPI/I2C/SWD in 4- to 20-mA Current LoopAs mentioned previously, when in current mode, there are two different scenarios depending on whetherOWI or SPI/I2C/SWD will be used as the type of communication for the PGA900. The PGA300 only allowscommunication through OWI, so always follow the settings found on Table 3 when using the PGA300 incurrent mode.Table 2 shows the jumper settings needed for each of these scenarios. Refer to Figure 4 forthe locations of the jumpers.

Table 2. Jumper Settings for PGA900EVM-034 in Current Mode using SPI/I2C/SWD

Jumper Setting FunctionJ16 Open Disconnect ASIC_GND from IRETURNJ19 Pins 1-2 closed Connect USBGND to ASICGNDJ13 Closed Connect PGA900 VDD pin to EVM input voltageJ6 Open Disconnect 180 pF between COMP and VOUTJ9 Closed Connect COMP to ASIC_GNDJ4 Closed Short out resistor at VOUTJ8 Open Disconnect FBN from VOUTJ5 Closed Connect VOUT to BJTJ7 Open Lift 100nF Voltage-mode load Capacitor at base of BJTJ10 Closed Connect FBP to IRETURN through 10-Ω resistorJ14 Pins 1-2 closed 100-nF capacitor from VDD to FBP and from DACCAP to FBPJ12 Open Disconnect PGA900 VDD pin from OWI signal from EVM

J25, J27 Closed If I2C is desiredJ24, J26, J28, J30 Closed If SPI/UART is desired

Table 3. Jumper Settings for PGAxxxEVM-034 in Current Mode using OWI

Jumper Setting FunctionJ16 Open Disconnect ASIC_GND from IRETURNJ19 Pins 2-3 closed Connect USBGND to IRETURNJ13 Open Disconnect PGA900 VDD pin from EVM input voltageJ6 Open Disconnect 560 pF between COMP and VOUTJ9 Closed Connect COMP to ASIC_GNDJ4 Closed Short out resistor at VOUTJ8 Open Disconnect FBN from VOUTJ5 Closed Connect VOUT to BJTJ7 Open Lift 100nF Voltage-mode load Capacitor at base of BJT

J10 Closed Connect FBP to IRETURN through 10-Ω resistorJ14 Pins 1-2 closed 100-nF capacitor from VDD to FBP and from DACCAP to FBPJ12 Closed Connect VDD in PGA900 to OWI signal from EVM

J25, J27 Open Disconnect I2C pins between USB2ANY and PGA900J24, J26, J28, J30 Open Disconnect SPI/UART pins between USB2ANY and PGA900

The PGA300 is prepared for OWI communication without need for configuration of the device.

For the PGA900, OWI in current mode can only be used with appropriate firmware programmed in thedevice. The firmware should:1. Enable the OWI interrupt and service it when the activation sequence on VDD is received by the

device.2. Set the deglitch time to the 1-ms default time (OWI_DGL_CNT_SEL = 0).3. Disconnect the DAC output from the loop by setting bit 0 of AMUX_CTRL to 0.4. Enable the OWI transceiver and reset M0 by writing 0x03 to MICRO_INTERFACE_CONTROL register.

VOUT

COMP

PGA900

FBP

AVSS

DVSS

GND

150 Q

VDD

10 Q

OWIJ20

J21

PGA900EVM

J13

J16

ASICGND IRETURN

J16: Open

J19: USBGND to ASICGND for SPI/I2C/SWD in current mode

PWR

ADDITIONAL

CURRENT

U11

OWI-Tx OWI-Rx

40 Q

J19

LOOP CURRENT

U1

ADDITIONAL

CURRENT

VBRGP

VBRGN

VINPP

VINPN

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When in 4- to 20-mA loop configuration, there is additional current from ASIC_GND (GND of PGA900) toIRETURN (return path for the loop current) due to the voltage difference created by the 40-Ω resistorinside PGA900 and the 10-Ω (R9) EVM resistor. This additional current will be due to U11 (when inSPI/I2C/SWD communication) and U1 (digital potentiometer in the resistive bridge). Figure 5 and Figure 6indicate this additional current. As a result, for accurate calibration (firmware required) in 4- to 20-mAmode, U1 should be isolated by lifting J22 and J23 and OWI should be used when using thePGAxxxEVM-034.

Figure 5. Additional Loop Current in 4- to 20-mA Mode When Using SPI/I2C/SWD as Digital Interface

VOUT

COMP

PGA900

FBP

AVSS

DVSS

GND

150 Q

VDD

10 Q

OWIJ20

J21

PGA900EVM

J12

J16

ASICGND IRETURN

J16: Open

J19: USBGND to IRETURN for OWI in current mode

PWR

U11

OWI-Tx OWI-Rx

40 Q

J19

LOOP CURRENT

U1

VBRGP

VBRGN

VINPP

VINPN

ADDITIONAL

CURRENT

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Figure 6. Additional Loop Current in 4- to 20-mA Mode When Using OWI as Digital Interface

+

20 10

OWI READ

+

10 kQ6.81 kQ

10.2k

12.4 kQ

16.2 kQ

INA138

1 kQOffset

Voltage

OWI WRITE

4 t 5 V for Communication

5 t 7.5 V for Activation

USB2ANY

UART-Tx

UART-Rx

PGA900100 nF

VDD

OPA454

OPA734

Current Compensating Voltage Copyright © 2016, Texas Instruments Incorporated

OWI www.ti.com

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4 OWIThe OWI circuitry in the PGAxxxEVM-034 allows communicating with the PGA900 and PGA300 by usingvoltage level translation and current sensing circuitry. The OWI circuitry is mainly based on a summingamplifier using the OPA454. This is mostly due to the current mode application where GND reference forthe PGA900 (ASIC_GND) is at higher potential than the reference for the OWI circuitry (IRETURN). Thisis due to the internal 40-Ω resistor and the 10-Ω (R9) EVM resistor connected to FBP. However, thisresistor could be a higher value, and as expected, the potential difference will be larger and is currentdependent. The summing amplifier principle compensates for these voltage differences so that the OWIlogic levels (with respect to ASIC_GND) always remain the same, regardless of current. The OWI circuitry,shown in Figure 7, consists of four main blocks:1. OWI write: UART data and activation pulses level translated to OWI voltage logic levels.2. Offset voltage: Constant offset voltage selected by the user to compensate for constant drops from

components such as diodes. This is only needed when operating the device in current mode. Involtage mode, the offset voltage should be set to 0 V.

3. Current compensating voltage: This additional voltage is only needed when operating the device incurrent mode to compensate for the voltage difference between the PGA900 ground and the OWIcircuitry ground due to the loop current. In voltage mode, the gain of the OPA734 should be set to unitygain.

4. OWI read: Current to voltage and voltage level translation to UART voltage logic levels.

Figure 7. OWI Block Diagram

www.ti.com OWI

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4.1 Activation PulseThe activation pulse generated by the PGAxxxEVM-034 generates the OWI interrupt needed to activatethe OWI (with the proper firmware developed by the user). Figure 8 shows the activation pulse from thePGAxxxEVM-034.• In the PGA900 GUI, to use this activation pulse, select the “Through Pulse” option from the “OWI

Activation Mode” menu and then click “OWI”. The duration of the activation pulse varies due tosoftware delays, but the minimum requirement of 1 or 10 ms is always met. If the pulse is not needed,OWI can also be enabled through I2C. To select this option, select “Through I2C” from the “OWIActivation Mode” menu, and then click “OWI”.

• In the PGA300 GUI, the activation pulse is sent as soon as you press "Activate OWI". The pulse will besent as defined in the PGA300 data sheet (SLDS204).

Figure 8. OWI Activation Pulse for the PGA900 Generated by the PGAxxxEVM-034 in Voltage Mode

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4.2 Data Sent Through OWIData through OWI can be sent to the PGA900/PGA300 at rates between 320 to 9600 bps. Figure 9 showsdata sent at 320 bps.

Figure 9. OWI Data at 320 bps; Oscilloscope Probe is Connected at TP20 in the PGAxxxEVM-034

www.ti.com XDS200 and USB2ANY Connectors

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PGAxxxEVM-034 User’s Guide

5 XDS200 and USB2ANY ConnectorsThe XDS200 is used for the single-wire debugging (SWD) feature of the PGA900. The designer must usea small breakout board (part of the XDS200 kit) to connect to J17 in the PGA900EVM-034. No externalconnections are needed. Figure 10 shows the proper connection for the XDS200 emulator.

Figure 10. XDS200 Emulator Connection to the PGAxxxEVM-034

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The USB2ANY is used for the different communication protocols offered by the PGA900/PGA300. TheUSB2ANY connects to J18 in the PGAxxxEVM-034 as shown in Figure 11. The USB2ANY hardware isbased on the TI MSP430F5529, 16-bit microcontroller with integrated USB 2.0. The PCB is a two-layer,single-sided board with minimal component count. There are two versions of the USB2ANY, shown inFigure 12, one enclosed and one open. The functionality is exactly the same for both.

Figure 11. USB2ANY Connection to the PGAxxxEVM-034

Figure 12. USB2ANY

DAC0

10 9

2

4

6

8

3

5

7

1

+5_EXT

PWM3

DAC1

P6.4/ADC0

P6.0/GPIO9/ADC2/EasyScale (AIN)

GND

P5.0/GPIO11/VREF+

P4.5/GPIO5/SPI(SOMI)/UART(RXD)

+3.3_EXT

P2.4/GPIO3/PWM2/INT0

P4.2/GPIO1/12C(SCL)

P1.2/GPIO7/PWM0/INT2

P1.0/GPIO12/CLOCK/EFC0/INT3

GND

GND

GND

P6.5/ADC1

P6.7/GPIO8/ADC3

GND

P6.1/GPIO10/VREF-

P4.4/GPIO4/SPI(SIM0)/UART(TXD)

GND

P4.0/GPIO2/SPI(SCLK)/EasyScale (DOUT)

P4.1/GPIO0/12C(SDA)

P2.0/GPIO6/SPI(CS)/PWM1/INT1

J5

J4

J3

SWS1

USB MINI-B

Status LED

JTAG

2

4

6

8

3

5

7

1

2

4

6

8

3

5

7

1

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Figure 13 shows the pinout of the USB2ANY. The ribbon cable can only be connected one way to the USB2ANY due to a latch present in thecable. A USB cable is included to connect the device to the PC. No external supply is needed.

Figure 13. USB2ANY Pinout

7.5-V Regulator 5-V Regulator 3.3-V Regulator

J20

J21

10 to 30 V

J13

J11

To PGA900 VDD

To PGA900 VDD

J15

To PGA900 VP_OTP

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6 Power Supplies in the PGAxxxEVM-034The PGAxxxEVM-034 requires an input voltage between 10 to 30 V to properly operate. Figure 14 showsthe different power options in the PGAxxxEVM-034.

Figure 14. Power Distribution in PGAxxxEVM-034

NOTE: J15 must be closed during OTP programming. This is only applicable for the PGA900. ThePGA300 has no OTP functionality.

VDD SELECTION

ASIC_GND IRETURN

PIN 36

TP41

TP19PIN 1

V7P5

INT+INT-INP+INP-BRG+BRG-

INT+

INT-

INP+

INP-

BRG+

BRG-

PIN 29

DVDD

PIN 33 TP13

TP25

TP15

TP23

TP30

TP16

TP12

TP14

TP42

TP26

0.1µFC24

TP36

PIN 28

TP17

PIN 35

PIN 34

14

17

20

23

26

29

32

35

15

16

21

22

37

25

28

31

30

34

36

27

33

11

8

5

2

13

18

19

24

12

9

6

7

3

1

10

4

XU1790-41036-101T

ASIC_GND

DACCAP

RE

FC

AP

TP28

TP32

TP31

PIN 20

PIN 19AVDD

TP33

TP38TP37

TP40

CO

MP

TP39

ASIC_GND

OUT

ASIC_GND

PIN 4

0.1µFC25

0.1µFC26

DECOUPLING CAPS

AVDDDVDD

ASIC_GND

TP11 TP10

PIN 31

PIN 30

PIN 31PIN 30

TP18

TP22PIN 27

TP24

TP21

TP34

INP+

TP35

INP-

TP29

TP27

INT-

INT+

FB-

FB+

FB-FB+

COMPCOMP

FB

-

PIN

31

PIN

30

PIN 24

PIN 25

BR

G+

BR

G-

FB

+

PIN 7

PIN 26

0.1µFC23

FB

+

ASIC_GND

J16 - OPEN FOR 4-20 mA LOOPJ16 - CLOSED FOR VOLTAGE OUTPUT

SPI/I2C COMMUNICATION

DV

SS

AVSS

GN

D

PWR

PWR

0.1µFC22

TP20

VPWROWI

Q5BSS169H6327XTSA1VPWR

1000pFC21

ASIC_GND

J11 J12 J13

J16

J15

1

2

3

J14

ASIC_GND

ASIC_GND

PIN 1

NU1

DVDD_MEM2

DVDD3

NU4

PWR5

DACCAP6

NU7

OUT8

AVDD9

GND10

FB-11

FB+12

COMP13

BRG-14

BRG+15

REFCAP16

INP-17

INP+18

NU19

NU20

INT+21

INT-22

AVSS23

NU24

NU25

NU26

NU27

NU28

NU29

NU30

NU31

DVSS32

NU33

NU34

NU35

NU36

PAD37

U17

PGA300ARHHR

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www.ti.com Schematics

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7 SchematicsFigure 15 through Figure 20 show the PGAxxxEVM-034 schematics.

Figure 15. PGAxxxEVM-034 Main Schematic

INP-

ASIC_GND

ASIC_GND

0.01µF

DNI

C3INP+

INP-

ASIC_GND

V5

PIN 36

PIN 33

BRG+

BRG-

4.99kR5

4.99kR6

4.99kR2

INP+

OUT

IRETURN

TP1

TP2 TP3

0.1µFC5

ASIC_GND

2,4

Q1BCP56-16

FB-

FB+

COMP

FB-

10.0k

R3

10.0k

R4

0.15µFC4

0.15µFC2

ASIC_GND

COMP

4-20 mA loop:Close J4, J5, J9, J10 and J14 (pins1-2)Open J6, J7, J8 and J16

Voltage mode:Close J6, J7, J8, J14 (pins 2-3) andJ16Open J4, J5, J9 and J10

DAC OUTPUT CONFIGURATIONS

RESISTIVE BRIDGE

10.0

R9

4.70kR1

0.1µFC1

J7

J8

J6

J4

J5

J9

J2

J3

J1

D4BAS70W-7-F

PWR

110

R7

560pFC6 150

R8

VDD1

AD02

WP3

W14

B15

A16

SDA7

VSS8

SCL9

DGND10

AD111

A312

B313

W314

U1

AD5252BRUZ1

J22

J23

J10

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Figure 16. Input and Output Schematic

USB2ANY

SCL

SPI_SIMO/UART_TX_U2A

SPI_SOMI/UART_RX_U2A

GPIO_OWI_TX

IN11

NO12

GND3

NO24

IN25

COM26

NC27

V+8

NC19

COM110

U11

TS5A23159DGS

GND TEST POINTS

ASIC_GND ASIC_GND USBGND USBGNDIRETURN IRETURN

TP43 TP44 TP47 TP48TP45 TP46

0.1µFC28 GPIO2/SPI(SCLK)

GPIO4/SPI(SIMO)/UART(TXD)

GPIO5/SPI(SOMI)/UART(RXD)

GPIO1/I2C(SCL)PIN 28

TP53

TP59 GPIO10/VEREF-

TP61

GPIO8/ADC3TP57ADC1

GPIO_OWI_TX0R42

TP60

GPIO9/ADC2 TP58ADC0

DAC0+5V_EXT TP49PWM3DAC1

EFC0/GPIO12/CLOCK

0R41 GPIO_OWI_ACT

GPIO7/PWM0TP51

+3.3V_EXT TP52GPIO3/PWM2 TP54

SCLTP56

GPIO0/I2C(SDA)TP55

SDASDA

PIN 29GPIO6/PWM1/SPI(CS)

TP50

TP62

OWI_TX

OWI_RX

ASIC_GND

PIN 35

PIN 34

1 2

3 4

5 6

7 8

9 10

J17

PIN 31

PIN 30

XDS200

10.0kR40

GPIO11/VEREF+

IRETURN

USBGND

J19 - USBGND TO IRETURN: OWI in 4-20 mA LOOPJ19 - USBGND TO ASIC_GND: SPI/I2C/SWD in 4-20 mA LOOP

+5

V_E

XT

GPIO_OWI_VDD

1 2 3

J19

AVDD

ASIC_GND

1

3

56

4

2

7

910

8

12 11

14 13

16 15

18 17

20 19

22 21

24 23

26 25

28 27

30 29

J18

USBGND

J25

J27

PIN 36

PIN 33

J24

J28

J26

J30NC

1

NC2

IO13

GND4

IO25

U16

TPD2E2U06DRLR

USBGND

SDA SCL

Copyright © 2016, Texas Instruments Incorporated

www.ti.com Schematics

19SLDU011A–May 2015–Revised June 2016Submit Documentation Feedback

Copyright © 2015–2016, Texas Instruments Incorporated

PGAxxxEVM-034 User’s Guide

Figure 17. USB2ANY Schematic

OWI DATA

OWI ACTIVATION PULSE AND DATA

OWI ACTIVATION

OWI_TX

V3P0

GPIO_OWI_TX

IRETURN

IRETURN

IRETURN IRETURN

IRETURN

IRETURN

GPIO_OWI_ACT

IRETURN

0.1µFC7

0.1µFC8

TP4

5.1k

R14

200kR10

100V

Q3

BSS123

2.00kR15

3.0kR19

TP6

V5

V7P5

-250V

Q4BSS192PH6327FTSA1

-250V

Q2BSS192PH6327FTSA1

IRETURN

TP5

1.00kR12

1.00kR17

2.00kR16 2

3

1A

V+

V-

84

U3ATLC352ID

POWER_AMP_IN

COM1

NC2

GND3

V+4

N.C.5

IN6

-VCC7

NO8

U2

TS12A12511DGKR

2.00kR11

V7P5

4.02kR13

8.06kR18

1

2

3

4

5

6

U15OPA734AIDBVT

0.1µF

C18

IRETURN

IRETURN

V7P5

Copyright © 2016, Texas Instruments Incorporated

Schematics www.ti.com

20 SLDU011A–May 2015–Revised June 2016Submit Documentation Feedback

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PGAxxxEVM-034 User’s Guide

Figure 18. OWI Activation Pulse and Data Schematic

POWER AMPLIFIER

CURRENT SENSING - UART RX

OWI

VPWR

OWI

IRETURN

IRETURN

0.1µFC11

IRETURN

IRETURN

IRETURN

IRETURN

IN-1

GND2

PRE OUT3

BUF IN4

OUT5

V+6

NC7

IN+8

U5

INA271AID

IRETURN

VPWR

5.1k

R21

499kR29

1.0MegR27

1.0MegR28

TP9

TP8

0.1µFC12

IRETURN

2

1

3

4

5

V+

V-

6

87

9

U7

OPA454AIDDA

TP7

0

R20

270pFC16

1000pF

C10

V3P3

0.1µF

C14

IRETURN

VPWR

4.99kR38

4.99k

R34

OU

T1

GN

D2

VIN

+3

VIN

-4

V+

5

U8

INA138NA

0.1µF

C17

IRETURN

POWER_AMP_IN

82pFC15

10µF

C13

20.0

R32

10.0

R33

IRETURN

0.1µF

C27

IRETURN

0.1µF

C19

IRETURN

SCL

SDA

GPIO_OWI_VDDOnly "1" when button to "Raise VDD duringcalibration in voltage mode" is clicked in theGUI

1000pF

DNIC20

IRETURN

GPIO_OWI_VDD

46.4kR30

40.2kR23

2

3

1A

V+

V-

84

U6A

TLC352ID

SDA7

VDD4

W2

B3

A1

SHDN5

AD08

SCL6

AD19

GND10

VSS11

O212

VL13

O114

U10

AD5280BRUZ50

V7P5

V3P3

IRETURN

IRETURN

IRETURN

V3P3

V3P3

IRETURN

OWI_RX

IRETURN

Q6BC847CLT1G10k

R25

1µFC9

IRETURN

0.027µFC39

IRETURN

V5

1

2

3

5

410

U4AOPA2734AIDGST

9

7

8

6

410 U4B

OPA2734AIDGST

V7P5

HA

1

LA

2

WA

3

HB

4

LB

5

WB

6

A2

7

VS

S8

SD

A9

SC

L10

GN

D11

A1

12

A0

13

VD

D14

U9TPL0102-100RUCR

0.1µF

C40

IRETURN

SCL SDA

20.0k

R46

1.00k

R48

10.0kR37 1.00k

R35

1.00kR24

V5

V7P5

10.0k

R26

6.81k

R31

10.2k

R39

12.4kR47

16.2k

R36

2.00k

R22

V3P3

Copyright © 2016, Texas Instruments Incorporated

www.ti.com Schematics

21SLDU011A–May 2015–Revised June 2016Submit Documentation Feedback

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PGAxxxEVM-034 User’s Guide

Figure 19. OWI Power Amplifier Schematic

10V - 30V PGA900EVM input

7.5V Regulator

5V Regulator

POWER SUPPLIES

IRETURNIRETURN

T2

T1

IRETURN

V5 T4

VPWR

IRETURN

V7p5

IRETURN IRETURN

V7P5

IRETURN

V3P3

3.3V Regulator

IRETURN

0.01µFC36

T3

IN1

GND2

EN3

BYPASS4

OUT5

U13

TPS79133DBV

IRETURN

V5

IRETURN

0.1µFC35

100VD2

1N4002-T

OUT4

ADJ1

IN3

U12

LM317MKVURG3

240R43

1.18kR44

100V

D31N4002-T

0.1µFC32

1µFC310.1µF

C29

100µFC30

1µFC37

10µFC33

IN1

GND2

EN3

NC4

OUT5

U14

TPS76950QDBVRG4Q1

1µFC34

IRETURN

0R45

10µFC38

VPWR

IRETURN

J20

SPC15363

J21

SPC15354

Copyright © 2016, Texas Instruments Incorporated

Schematics www.ti.com

22 SLDU011A–May 2015–Revised June 2016Submit Documentation Feedback

Copyright © 2015–2016, Texas Instruments Incorporated

PGAxxxEVM-034 User’s Guide

Figure 20. Power Supplies Schematic

www.ti.com Revision History

23SLDU011A–May 2015–Revised June 2016Submit Documentation Feedback

Copyright © 2015–2016, Texas Instruments Incorporated

Revision History

Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (May 2015) to A Revision ........................................................................................................... Page

• Updated Table 2........................................................................................................................... 7• Added Table 3 ............................................................................................................................. 7• Additional current discussion when in 4- to 20-mA mode............................................................................ 8• Added Figure 5 ............................................................................................................................ 8• Added Figure 6 ............................................................................................................................ 9• Added note regarding jumper for OTP voltage ...................................................................................... 16• Updated designator for J16 in Figure 15 ............................................................................................. 17• Updated designators for text in DAC Output Configurations in Figure 16 ....................................................... 18• Updated designator for J19 in Figure 17 ............................................................................................. 19

STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or

documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein.Acceptance of the EVM is expressly subject to the following terms and conditions.1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility

evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are notfinished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. Forclarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditionsset forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software

1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or productionsystem.

2 Limited Warranty and Related Remedies/Disclaimers:2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software

License Agreement.2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM

to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatmentby an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in anyway by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications orinstructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or asmandated by government requirements. TI does not test all parameters of each EVM.

2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM,or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during thewarranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects torepair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shallbe warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) daywarranty period.

3 Regulatory Notices:3.1 United States

3.1.1 Notice applicable to EVMs not FCC-Approved:This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kitto determine whether to incorporate such items in a finished product and software developers to write software applications foruse with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unlessall required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not causeharmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit isdesigned to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority ofan FCC license holder or must secure an experimental authorization under part 5 of this chapter.3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:

CAUTIONThis device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may notcause harmful interference, and (2) this device must accept any interference received, including interference that may causeundesired operation.Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority tooperate the equipment.

FCC Interference Statement for Class A EVM devicesNOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 ofthe FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment isoperated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if notinstalled and used in accordance with the instruction manual, may cause harmful interference to radio communications.Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required tocorrect the interference at his own expense.

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FCC Interference Statement for Class B EVM devicesNOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 ofthe FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residentialinstallation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordancewith the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interferencewill not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, whichcan be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or moreof the following measures:

• Reorient or relocate the receiving antenna.• Increase the separation between the equipment and receiver.• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.• Consult the dealer or an experienced radio/TV technician for help.

3.2 Canada3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210

Concerning EVMs Including Radio Transmitters:This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions:(1) this device may not cause interference, and (2) this device must accept any interference, including interference that maycause undesired operation of the device.

Concernant les EVMs avec appareils radio:Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitationest autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doitaccepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

Concerning EVMs Including Detachable Antennas:Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna typeand its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary forsuccessful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna typeslisted in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibitedfor use with this device.

Concernant les EVMs avec antennes détachablesConformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type etd'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillageradioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotroperayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Leprésent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans lemanuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antennenon inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation del'émetteur

3.3 Japan3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に

輸入される評価用キット、ボードについては、次のところをご覧ください。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page

3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certifiedby TI as conforming to Technical Regulations of Radio Law of Japan.

If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required by Radio Law ofJapan to follow the instructions below with respect to EVMs:1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal

Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule forEnforcement of Radio Law of Japan,

2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect toEVMs, or

3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japanwith respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please notethat if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.

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【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けていないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用

いただく。2. 実験局の免許を取得後ご使用いただく。3. 技術基準適合証明を取得後ご使用いただく。

なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ

ンスツルメンツ株式会社東京都新宿区西新宿６丁目２４番１号西新宿三井ビル

3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page

SPACER4 EVM Use Restrictions and Warnings:

4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOTLIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.

4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handlingor using the EVM, including without limitation any warning or restriction notices. The notices contain important safety informationrelated to, for example, temperatures and voltages.

4.3 Safety-Related Warnings and Restrictions:4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user

guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable andcustomary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to inputand output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, orproperty damage. If there are questions concerning performance ratings and specifications, User should contact a TIfield representative prior to connecting interface electronics including input power and intended loads. Any loads appliedoutside of the specified output range may also result in unintended and/or inaccurate operation and/or possiblepermanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting anyload to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuitcomponents may have elevated case temperatures. These components include but are not limited to linear regulators,switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using theinformation in the associated documentation. When working with the EVM, please be aware that the EVM may becomevery warm.

4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with thedangers and application risks associated with handling electrical mechanical components, systems, and subsystems.User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronicand/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safelylimit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility andliability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors ordesignees.

4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes allresponsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility andliability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and localrequirements.

5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurateas possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites asaccurate, complete, reliable, current, or error-free.

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SPACER6. Disclaimers:

6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THEDESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHERWARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIEDWARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANYTHIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.

6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS ANDCONDITIONS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANYOTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRDPARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANYINVENTION, DISCOVERY OR IMPROVEMENT MADE, CONCEIVED OR ACQUIRED PRIOR TO OR AFTER DELIVERY OFTHE EVM.

7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITSLICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANYHANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS AND CONDITIONS. THIS OBLIGATIONSHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANYOTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.

8. Limitations on Damages and Liability:8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,

INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESETERMS ANDCONDITIONS OR THE USE OF THE EVMS PROVIDED HEREUNDER, REGARDLESS OF WHETHER TI HASBEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITEDTO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODSOR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS,LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALLBE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED.

8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY WARRANTY OR OTHER OBLIGATIONARISING OUT OF OR IN CONNECTION WITH THESE TERMS AND CONDITIONS, OR ANY USE OF ANY TI EVMPROVIDED HEREUNDER, EXCEED THE TOTAL AMOUNT PAID TO TI FOR THE PARTICULAR UNITS SOLD UNDERTHESE TERMS AND CONDITIONS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCEOF MORE THAN ONE CLAIM AGAINST THE PARTICULAR UNITS SOLD TO USER UNDER THESE TERMS ANDCONDITIONS SHALL NOT ENLARGE OR EXTEND THIS LIMIT.

9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not ina resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicableorder, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),excluding any postage or packaging costs.

10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating tothese terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive reliefin any United States or foreign court.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2015, Texas Instruments Incorporated

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IMPORTANT NOTICE

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