Performance Enhancement of P-channel InGaAs Quantum-well FETs by

Superposition of Process-induced Uniaxial Strain and Epitaxially-grown Biaxial Strain

Ling Xia1, Vadim Tokranov2, Serge R. Oktyabrsky2, and Jesús A. del Alamo1

1 Microsystems Technology Laboratories, MIT, USA;2 College of Nanoscale Science and Engineering, SUNY-Albany, USA.

Dec. 06, 2011

Sponsors: Intel Corp. and FCRP-MSD Center. Fabrication: MTL at MIT.

Outline

• Motivation

• Mechanical simulations

• Device technology

• Experimental results

• Conclusions

2

• Interests in InGaAs CMOS – Fueled by excellent ve and µe• Key challenge for InGaAs CMOS

• Bridging performance gap between n- and p-FET.• Our approach – Introduce strain to InGaAs p-FET

• Uniaxial + biaxial compressive strain

Kuhn, IWJT, 2010

Logarithmic scale

Electron mobility

Hole mobility

Motivation

del Alamo, Nature, 20113

• Sources for strain include:– Epitaxial lattice mismatch Biaxial strain– Fabrication process Uniaxial strain

Why biaxial strain + uniaxial strain?

4

• Enhancements of µh by biaxial and uniaxial strain add superlinearly• Similar effect found in Si simulations (Wang, TED, 2006)

-2.5 -2.0 -1.5 -1.0 -0.5 0.00

20

40

60

80

100

120

GaAs

In0.24Ga0.76As

Max

<11

0> p

iezo

resi

stan

ce c

oeffi

cien

t (1

012 c

m2 /d

yn)

Epitaxial compressive biaxial strain (%)

Ge

Gomez, EDL, 2010Weber, IEDM, 2007Xia, TED, 2011Xia, ISCS, 2011 Experiments

π = ‐Δµ/(µ0σ )

InGaAs QW-FET with uniaxial + biaxial strain

• Induced stress scalable with LG (next slide)

5

• Biaxial strain in the channel as grown

• Carbon delta-doping

• Self-aligned stressor (compressively stressed)

• Self-aligned metal layer (Mo)

Mechanical stress simulations• Parameters used in simulations: tSiN = 200 nm; SiN σint = -2 GPa

6

S DCut line

LG = 2 µm

• Desirable stress type can be obtained with the proposed stressor structure• Compressive longitudinal stress µh ↑• Tensile transverse stress µh ↑

Lside = 100 nm

tSiN=200 nm

x (µm)-1 0

Longitudinal stress distribution

0%

30%

60%

90%

120%

150%

180%

10 100 1000 10000

Δµh/

µ h0

LG (nm)

FromFromTotal

Projected assuming Δµh/ µh = -π·σπ// = - 1.2x10-10 cm2/dynπ = 0.7x10-10 cm2/dyn(Xia, ISCS, 2011)

σσ//

-1,500

-1,200

-900

-600

-300

0

300

10 100 1,000 10,000

Stre

ss (M

Pa)

LG (nm)

LongitudinalTransverse

Slow increase when LG >> tSiN

Fast increase when LG ~ tSiN

Slow down due to a fixed Lside

LG scalability of induced stress at middle of gate

• LG ↓ Stress ↑ inside gate opening• Assume linear ∆µ with σ

>160% µh enhancement for LG < 50 nm7

Device technology

8

Mesa isolation

Ohmic metalization

Molybdenum (Mo) deposition

PECVD SiN stressor and SiO2Anisotropic ECR RIE SiO2/SiN

Anisotropic ECR RIE Mo

Isotropic RIE Mo

GaAs cap recess by wet etching

Gate metalization

Key considerations:• Avoid Mo layer short to gate metal• Air gap as small as possible

ChannelBarrier

Buffer

Al0.42Ga0.58As

AlGaAsIn0.24Ga0.76As

DS

SiN

Mo

SiO2

Cap : 2x1019 cm-3 Carbon doped GaAs

Channel

Cap GaAs

Buffer AlGaAsIn0.24Ga0.76As

DS

SiNSiO2

MoCap : 2x1019 cm-3 Carbon doped GaAs

SiO2

Barrier Al0.42Ga0.58As

ChannelBarrier

Buffer

Al0.42Ga0.58As

AlGaAsIn0.24Ga0.76As

DS

SiN

Mo

SiO2

Cap : 2x1019 cm-3 Carbon doped GaAs

Channel

Cap

Buffer AlGaAsIn0.24Ga0.76As

DS

SiNSiO2

MoCap : 2x1019 cm-3 Carbon doped GaAs

SiO2

Barrier Al0.42Ga0.58As

G

Device cross-section

• LG = 2 µm; channel along [-110]• Lside 400 nm

9

Artifact of imaging

Experimental parameters for devices•Split experiments:

• SiN with -2.1 GPa stress vs SiN with 0 Pa stress• SiN film stress obtained from wafer curvature measurements

• LG = 2 µm to 8 µm• Four channel orientations:

10

[-110]

[110]

S D

GS

D

G[110][-110] [010][100]

QW-FET electrical characteristics• Example: LG = 2 µm; channel along [-110]

• Significant drive current increase• Transconductance increase at all gate overdrives

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-2.0 -1.5 -1.0 -0.5 0.00

2

4

6

8

10

-I D (m

A/m

m)

VDS (V)

-2.1 GPa SiN 0 GPa SiN

VGS - VT = -0.75 V

-0.55 V

-0.35 V

-0.15 V

-0.5 0 0.50

10

20

30

40

VGS - VT (V)|g

m| (

mS

/mm

)

0 GPa SiN-2 GPa SiN

VDS = -2 V

Intrinsic

Extrinsic

Subthreshold characteristics and VT• Similar IG as chemically etched samples No RIE damage• VT shift between high- and low- stress samples

– Likely due to different anisotropic RIE overetch

12

-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.01E-5

1E-4

1E-3

0.01

0.1

1

10

With -2 GPa SiN

|I| (m

A/m

m)

LG = 2 m

VDS = -2 V

ID

With 0 GPa SiN

VGS (V)

IG

Both S = 103 mV/dec

LG dependence of gm

• Increasing enhancement observed with decreasing LG • Consistent with stress simulations + π measurements

>160% enhancement expected with LG < 50 nm13

2 4 6 80

5

10

15

20

25

30

|gm

-sat

| (m

S/m

m)

LG (m)

VDS = -2 VVGS – VT = -0.5 V

+36%

Channel along [-110]

Dots : dataLines: least-square fittings

• Observed anisotropic ∆gmi and ∆RSD– gmi extracted using gmext, RS, RD and gD– RS, RD extracted using gate current injection method

• anisotropy consistent with measurements of piezoresistance coefficients– π[-110] : π [110] = 2.6 (Xia, ISCS, 2011)

Crystal direction dependence

14

gmi_sat

kx (2/a)

k y (2

/a)

-0.1 -0.05 0 0.05 0.1-0.1

-0.08

-0.06

-0.04

-0.02

0

0.02

0.04

0.06

0.08

0.1No uniaxial-500 MPa uniaxial

Theoretical discussions• Valence band change due to strain in InGaAs

– Used k.p methods (nextnano3)– Calculated subbands in In0.24Ga0.76As quantum well

15

In-plane iso-energy contours of hh1 with and without uniaxial strain

[100]

[010] [110]

• Compressive strain parallel to channel is desirable

-0.1 -0.05 0 0.05 0.1-0.16

-0.14

-0.12

-0.1

-0.08

-0.06

Ev

(eV

)

k//[-110]k[110]

[-110] uniaxial

No uniaxial

m*// ↓m*↑

hh1

lh1

hh2

Effective mass model• Treat nonparabolic valence band using energy dependent

m* (De Michielis, TED, 2007)

From simulations:• ∆m* anisotropy induced by quantization change due to piezoelectric effect• ∆m* anisotropy consistent with gm measurements.

Gate

Pz(z)BarrierChannel

[-110] Strain

-0.1 -0.05 0 0.05 0.1-0.16

-0.14

-0.12

-0.1

-0.08

-0.06

Ev

(eV

)

k//k

[-110] uniaxial

[110] uniaxial

No uniaxial

m*// ↓m*↑

Conclusions• Developed device architecture for InGaAs p-FETs that incorporates

uniaxial strain through self-aligned dielectric stressor

• Key results:

– Biaxial strain + uniaxial strain substantial enhancements in transport characteristics

– Up to +36% ∆gm observed in LG = 2 µm device

– Strong enhancement anisotropy due to piezoelectric effect

• For further enhancement:

– Scale down LG and bring S/D closer

– Project ∆gm >160% @ LG < 50 nm

• Study useful to other p-type III-V materials (e.g. InGaSb, InSb)

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