performance analysis of full adder based 2- bit comparator using different design modules

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

1 NITTTR, Chandigarh EDIT-2015

Performance Analysis of Full Adder Based 2-Bit Comparator using Different Design Modules

Meena Aggarwal1, Amrinder Kaur2

1,2Department of ECE, SBBSIET, Jalandhar, India [email protected], [email protected]

ABSTRACT-In modern digital VLSI design, digital signal processors (DSP) and data processing application-specific integrated circuits(ASIC), comparators are important design element and arithmetic components . In this paper, a 2-bit magnitude comparator has been developed in three different style based on full adder module which is designed to provide good performance. The performance of these three different styles of comparator has been compared in terms of area and power consumption which are the important parameters that are considered while designing any digital circuit. The schematic are designed and simulated for its behavior using DSCH-3.1.The layout of simulated circuits are created using Verilog based netlist file which is then simulated in Microwind 3.1 to analyze the performance of three different styles at 45nm and 90 nm CMOS technology. Keywords- ALU, Comparators, CMOS style, Digital Arithmetic,Full Adder module, PTL logic,GDI technique.

I. INTRODUCTION Comparator is well known to be a very basic and useful component of arithmetic units of the digital systems. In such systems, comparison of any two numbers is said to be a necessary arithmetic operation that determines whether a number is greater than, equal to, or less than the other number [1]. Magnitude comparator forms a combinational circuit to compare two numbers, let A and B, and finally determine their relative magnitudes and thereby relation between the two(equal to, less than, greater than). Fig.1 depicts the basic block of two bit magnitude comparator. The result of comparison is represented by 3 binary variables that indicate whether A>B, A=B, or A<B.

Fig. 1. Block Diagram of n-Bit Magnitude Comparator

If two n-Bit numbers are to be compared then the circuit will have 2n inputs & 22n entries in the truth table. For 2-Bit numbers there shall be 4-inputs & 16- rows in the truth table, similarly, for 3-Bit numbers the truth table would comprise of 6-inputs & 64-rows [2].

II. BIT MAGNITUDE COMPARATOR 2-Bit Magnitude Comparator is meant to compare two bit numbers (let A1, A0 & B1,B0). Therefore, for such an arrangement, truth table [5] shall have 4 inputs & 16 entries as in Table 1.

Table 1. Truth Table of 2-Bit Magnitude Comparator INPUT OUTPUT A1 A0 B1 B0 A>B A=B A<B 0 0 0 0 0 1 0

0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 1 0 1 0

III. DESIGN APPROACHES

There are several approaches which will be helpful in designing CMOS comparators. Each method will offer different operating speed, power consumption, and circuit complexity. The size of the circuit depends on the number and size of the transistors and also on the wiring complexity. The wiring complexity is a function of number of connections and their lengths. All the said characteristics may vary considerably from one logic style to another and therefore proper choice of logic style is very important for desirable circuit performance [3], [4]. The main purpose of all the design styles and modifications is to bring down the transistor count, decrease the power consumption and achieve an increased speed.

IV. COMPARATOR LOGIC STYLES The work presented herein is focused on basic three styles of design which are as under: a. CMOS Logic Style b. PTL Logic c. GDI Logic Fig. 2 shows the design based on the full adder module.

Fig.2. Logic diagram of full adder module based 2-bit

comparator This logic diagram of 2-bit comparator based on full adder module consist of four Ex-or gates, two mux and two AND gates. The inverter at one input of Ex-or make it to act as a Ex-nor which is designed by using 3 transistors. A. CMOS logic style


NITTTR, Chandigarh EDIT -2015 2

Fig.3 (a) shows symbol of a CMOS Inverter. It is comprised of one NMOS & one PMOS transistor. If input A=0 (logic low) then both gates come at zero potential & PMOS is turned ON to provide low impedance path from VDD to output (Y). Therefore output (Y) approaches to high level of VDD. If input A=1 (logic high) then both the gates come at higher potential but NMOS is turned ON which provides low impedance path between ground & output (Y). Therefore, output (Y) approaches to low level of 0V. The principle of CMOS logic design represents that the Pull up network has only PMOS circuitry & Pull down network has only NMOS circuitry. The function of Pull Up Network is to provide connection between VDD & output, similarly of Pull Down Network is to provide connection between the output & GND(Ground) . Both the networks are constructed in a way such that only one network is in conducting state at a time [9]. Such a design approach produces Large Power dissipation and increase in transistor count in comparison to remaining two logic styles. The research presented in the paper includes a 2-bit comparator design using CMOS Logic Style which is shown in Fig.4.

Fig. 3(a) Fig. 3(b) Figure 3. (a) Symbol of CMOS Inverter (b) Logic Network of

CMOS Style Fig. 4 depicts the schematic of CMOS based 2-bit comparator based on full adder module and is designed by using 88 transistors that provides 3 outputs i.e, A>b, A>B, A=B.

Fig.4. Schematic of CMOS 2-bit magnitude comparator

B. PTL logic Main focus of Pass Transistor Logic is to use purely NMOS Pass Transistors network for any logic operation. The basic difference of pass-transistor logic style and the CMOS logic style is that the source of the logic transistor networks is connected to some input signals instead of the power lines. In this design approach, transistor acts as a switch and thereby passes logic levels from input to the

output [11].Such a design approach requires lesser number of transistors because one pass-transistor network (either NMOS or PMOS) is sufficient to perform any logic operation. Lesser number of transistors result in increased speed. Fig.5 shows the schematic of PTL based style. It requires 28 transistors which are very less in numbers as compare to CMOS style based comparator. So due to less transistor count, it consume less area as compare to that.

Fig.5. PTL logic based 2-bit comparator

C. GDI logic It is also one of the technique which helps in designing low-power digital combinatorial circuit with less number of transistors. Due to reduction in transistor count, it also allows in reducing power consumption, propagation delay which in turn increases the speed of the circuit, and area of digital circuits while maintaining low complexity of logic design.

Fig.6. The Basic GDI cell

Fig.6 shows the basic GDI cell which has three inputs: G i.e. gate which is common to both NMOS and PMOS), P i.e. input to the source/drain of PMOS and N i.e. input to the source/drain of NMOS . As the GDI cell consists of only two transistors , so a wide range of complex logic functions can be implemented using only two transistors. Fig.7 shows the schematic of GDI style 2-bit comparator . This comparator has been implemented by using only 30 transistors which are very less in count as compare to CMOS style.

Fig.7. 2-bit comparator using GDI logic

V. RESULTS AND ANALYSIS

The performance of above mentioned different logic styles based 2-bit comparator has been evaluated in terms of area and power on 45nm and 90nm CMOS technology by using


3 NITTTR, Chandigarh EDIT-2015

Empherical LEVEL-3 MOS model for different supply voltages. Simulation of various schematics drawn in DSCH-3.1 has been done in Microwind 3.1 . The results of simulation are shown in Table-2. Table 2. Comparison of three different logic style based 2-bit

comparator in terms of area consumption Parametes

45 nm Technology 90 nm Technology

CMOS

GDI PTL CMOS GDI PTL

Area (µm2)

930.5 260.2 140 1891.6 527.1 296.7

Layout Width

50.8 38.4 23.6 101.7 56.1 34.5

Layout Height

18.3 6.8 6.0 18.6 9.4 8.6

Op. Temp .(0C)

20 20 20 20 20 20

InputVoltage

1.8 1.8 1.8 1.8 1.8 1.8

This table shows the comparison of three logic style in terms of area at fixed input supply voltage of 1.8V operating at same temperature . It is observed from the above table that PTL based comparator has less area consumption as compared to CMOS and GDI style for both 45nm and 90nm technology. Finally, Table-3 shows the simulation results for power consumption at different supply voltages. Table 3. Simulation results of 2-bit comparator with different

logic styles Supply Voltage

Power Consumption(µW)

45 nm Technology 90 nm Technology CMOS GDI PTL CMOS GDI PTL

0.6 V .0834 .0391 .0518 .0784 .0148 .0358 0.8 V 0.153 0.111 0.117 0.225 .04798 .085454 1.0 V 0.245 0.248 0.212 0.403 0.102 0.162 1.2 V 0.371 0.462 0.334 0.688 0.213 0.277 1.4 V 0.522 0.753 0.484 1.020 0.387 0.424 1.8 V 0.915 1.509 0.864 1.884 0.931 0.784 2.0 V 1.159 1.964 1.093 2.436 1.291 0.998

From this table, it is observed that power dissipation is less at 90nm at low voltage in case of CMOS technology but in case of GDI and PTL logic 90nm has better results. It is also observed that power dissipation increases with the increase in power supply. If we compare the power consumption of different logic style then PTL style will provide better performance till 1.4V but above this voltage GDI has good results.

VI. CONCLUSION By performing simulation of all three logic styles at 45nm and 90nm technology, the final results are obtained in terms of transistor count, area and power consumption. Implementation of PTL logic lead to usage of 28 transistors which is minimum as compared to others, thereby it turns out to be area efficient. The simulation results have been obtained on LEVEL-3 model.

REFRENCES [1] Morgenshtein, A.; Fish, A.; Wagner, I.A., “Gate-diffusion input

(GDI): A Power efficient method for digital combinational circuits,” IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 10 , no. 5 ,pp. 566 - 581 , 2002.

[2] N.Weste and D.Harris, CMOS VLSI Design: A Circuits and System Perspective, 3rd ed. Reading, MA, USA: Addison-Wesley May 2004.

[3] Microwind and DSCH version 3.1, User’s Manual, Copyright 1997-2007, Microwind INSA France.

[4] H.-.M.Lam and C.-Y. Tsui, “A MUX-based high-performance single-cycle CMOS comparator,” IEEE Transaction on Circuits System II, vol.54, no.7, pp.591-595, 2007.

[5] Chiou-Kou Tung; Yu-Cherng Hung; Shao-Hui Shieh; Guo-Shing Huang, “ A low -power high-speed hybrid CMOS full adder for Embedded System,” IEEE transactions on Design and Diagnostics of Electronic Circuits and Systems, vol.13, no.6, pp.1- 4, 2007.

[6] Geetanjali Sharma, Uma Nirmal, Yogesh Mishra, “A Low power 8-bit magnitude comparator with small transistor count using hybrid PTL/CMOS logic,” International Journal of Computational Engineering & Management, vol. 2, no. 2, pp.110-115, 2011.

[7] Subodh Wairya, Rajendra Kumar Nagaria ,Sudarshan Tiwari, “Comparative performance analysis of XOR/XNOR function based high-speed CMOS full adder circuits for low voltage VLSI design,” International Journal of VLSI Design & Communication System,vol.3, no.2, pp. 221-242, 2012.

[8] Laxmi Kumre , Ajay Somkuwar, Ganga Agnihotri, “Design of low power 8 bit GDI magnitude comparator,” International Journal of Emerging Technologies in Computational and Applied Sciences (IJETCAS),vol.4,pp.102-108, 2013.

[9] Anjuli and Satyajit Anand , “2- Bit magnitude comparator design using different logic styles,” International Journal of Engineering Science Invention , vol. 2 ,no. 1, pp.13-24, 2013.

[10] Anjali Sharma,Richa Singh, Pankaj Kajla , “ Area efficient 1-bit comparator design by using hybridized full adder module based on PTL and GDI logic,” International Journal of Computer Applications, vol.82, no.10, pp. 5-13, 2013.

[11] Arkadiy Morgenshtein, Viacheslav Yuzhaninov, Alexey Kovshilovsky, Alexander Fish, “Full-swing Gate Diffusion input logic,” Integration, the VLSI journal, vol.47,pp. 62-70,2014.

[12] Pooja Singh , Rajesh Mehra, “Design analysis of XOR Gates using CMOS & Pass Transistor Logic,” National Student Conference on Advances in Electrical & Information Communication Technology, AEICT-2014,pp.264-267, 2014.

[13] K.Rajasekhar, P.Sowjanya, V.Umakiranmai, R.Harish, M.Krishna , “Design and analysis of comparator using different logic style of full adder,” International journal of Engineering Research and Applications,vol.4, no.4, pp.389-393, 2014.

[14] Anjali Sharma, Rajesh Mehra, “Area and power efficient CMOS adder design by hybridizing PTL and GDI Technique,” International Journal of Computer Applications, vol.66, no. 4, pp. 15-22.

[15] Sharma.A, Sharma.P, “Area and power efficient 4-bit comparator design by using 1-bit full adder module,” IEEE conference on Parallel, Distributed and Grid Computing, pp. 1-6, 2014.

performance analysis of full adder based 2- bit comparator using different design modules

Documents