PentiumPro 450GX PentiumPro 450GX Chipset SynthesisChipset Synthesis

Steen LarsenSteen LarsenPresentation 1 for ECE572Presentation 1 for ECE572Nov 10 2003Nov 10 2003

General MotiveGeneral Motive

Investigate processor-memory Investigate processor-memory compression methods in a “current” (Intel compression methods in a “current” (Intel pipelined FSB and DIMM) architecture to pipelined FSB and DIMM) architecture to further evaluate advantages of using further evaluate advantages of using memory compression architectures.memory compression architectures.

Quickly evaluate using FPGA synthesis Quickly evaluate using FPGA synthesis different methods of address, instruction, different methods of address, instruction, and data compression by modifying and and data compression by modifying and existing production chipset.existing production chipset.

What is memory What is memory compression?compression?

Processor reads and Processor reads and writes to main memory in writes to main memory in 32 byte cache lines.32 byte cache lines.

Optimize this path of Optimize this path of information information (instruction/address/data)(instruction/address/data)

Currently simulations, Currently simulations, and one implementation and one implementation at IBM on instruction at IBM on instruction compression.compression.

Example of many reads Example of many reads per writeper write

Example of predominance Example of predominance of “0” and “1”of “0” and “1”

Benefit of 1-2% Benefit of 1-2% improvementimprovement

More detail of 450GX More detail of 450GX DC/DPDC/DP

Why synthesis to Why synthesis to FPGA?FPGA? Quick re-synthesis and Quick re-synthesis and

adjustment to existing VHDL adjustment to existing VHDL structures (reduce simulation and structures (reduce simulation and validation cycles)validation cycles)

Rapid advancement of FPGA logic Rapid advancement of FPGA logic and internal components. and internal components. (Moore’s law on older chipset)(Moore’s law on older chipset)

Altera Cyclone deviceAltera Cyclone device

Similar to other Similar to other Altera and Altera and Xilinx devices. Xilinx devices. (LE, PLL, (LE, PLL, memory, IO, memory, IO, licensed IP)licensed IP)

Altera LE internalsAltera LE internals

Orion 450GX detailsOrion 450GX details

Focusing only on memory interfaceFocusing only on memory interface NEC ASIC written in VHDLNEC ASIC written in VHDL PLL, Dual port RAMPLL, Dual port RAM 66MHz 64bit data bus66MHz 64bit data bus 11stst generation DIMM, ECC generation DIMM, ECC DC is 208 PQFP and DP is 240 PQFPDC is 208 PQFP and DP is 240 PQFP Plan to use existing platformsPlan to use existing platforms

Scope of DC/DP logicScope of DC/DP logic

28552 .vhd/.vhdtmp files or 98MB 28552 .vhd/.vhdtmp files or 98MB (This includes a lot of testbench files!)(This includes a lot of testbench files!)

165880 VHDL lines total of 165880 VHDL lines total of entity/architecture/package/configentity/architecture/package/config

15986 entity-architecture VHDL lines 15986 entity-architecture VHDL lines in DP logic (32 files)in DP logic (32 files)

17478 package VHDL lines in DP logic17478 package VHDL lines in DP logic

Synthesis conversion Synthesis conversion from ASIC-> FPGAfrom ASIC-> FPGA File format and locations File format and locations

(separate entity/architecture, (separate entity/architecture, autogenerated packages files for autogenerated packages files for each entity architectureeach entity architecture

Packages converted from NEC Packages converted from NEC ASIC to Altera logicASIC to Altera logic

Further issuesFurther issues

PLLs are needed, need to PLLs are needed, need to regenerateregenerate

Dual Port RAM is an ASIC Dual Port RAM is an ASIC primitive and needs to be primitive and needs to be converted to Altera RAM block. converted to Altera RAM block. (Biggest time sink was conversion (Biggest time sink was conversion on unsigned on unsigned (STD_LOGIC_VECTOR))(STD_LOGIC_VECTOR))

VHDL syntax VHDL syntax differencesdifferences Maximum one WAIT statement in Maximum one WAIT statement in

a VHDL process. Was used to a VHDL process. Was used to ensure multi-clock error output ensure multi-clock error output generation. May need to correct generation. May need to correct in the long run.in the long run.

PLLs currently commented out, PLLs currently commented out, and generated off a single off-and generated off a single off-chip clock.chip clock.

Currently…Currently…

ScreenShot of layoutScreenShot of layout

Now proceeding to Now proceeding to DataControl chipDataControl chip 140 architecture files compared 140 architecture files compared

to 32 of the datapath chipto 32 of the datapath chip Main packaging conversion Main packaging conversion

difficulties should be solved.difficulties should be solved. Estimate 5-10X complexity of Estimate 5-10X complexity of

logic, so potential pitfallslogic, so potential pitfalls

What is needed What is needed beyond synthesisbeyond synthesis Simulation of basic read/write Simulation of basic read/write

processor accessprocessor access Understanding of current chipset Understanding of current chipset

errataerrata Circuit board layout (GTL Circuit board layout (GTL

translation, bus clock rate down translation, bus clock rate down from 66MHz)from 66MHz)

Boot DOS/Linux/WindowsBoot DOS/Linux/Windows Implement compression algorithmsImplement compression algorithms

Questions?Questions?

If I have seen further it is by If I have seen further it is by standing on the shoulders of standing on the shoulders of giants. giants. – Isaac Newton, Letter to Robert Isaac Newton, Letter to Robert

Hooke, February 5, 1675Hooke, February 5, 1675