penn ese534 spring2012 -- dehon 1 ese534: computer organization day 7: february 6, 2012 memories
TRANSCRIPT
![Page 1: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/1.jpg)
Penn ESE534 Spring2012 -- DeHon1
ESE534:Computer Organization
Day 7: February 6, 2012
Memories
![Page 2: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/2.jpg)
Penn ESE534 Spring2012 -- DeHon2
Previously…
• Arithmetic: addition, subtraction
• Reuse:– pipelining– bit-serial (vectorization)
• Area/Time Tradeoffs
• Latency and Throughput
![Page 3: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/3.jpg)
Penn ESE534 Spring2012 -- DeHon3
Today
• Memory– features– Area and delay intuition and modeling– design– technology
![Page 4: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/4.jpg)
Preclass 1
Penn ESE534 Spring2012 -- DeHon4
€
2000 N +N <100N
When is:
![Page 5: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/5.jpg)
Preclass 2
Penn ESE534 Spring2012 -- DeHon5
€
C1N log2(N)
m+C2m +C3N
Find m to minimize:
![Page 6: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/6.jpg)
Preclass 2
• How related?
Penn ESE534 Spring2012 -- DeHon6
€
C1N log2(N)
m+C2m +C3N
![Page 7: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/7.jpg)
Preclass 2
• Related?
• m=bw
• bw*bd=N– So bd=N/m
Penn ESE534 Spring2010 -- DeHon7
€
C1N log2(N)
m+C2m +C3N
![Page 8: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/8.jpg)
Preclass 2
• C3 is for area of single memory cell
• log2(n) is for decoder
– In red
• C1 is for gates in decoder
• C2 is for amps at bottom of row and drivers at top
Penn ESE534 Spring2010 -- DeHon8
€
C1bd log2(N) +C2bw +C3N
![Page 9: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/9.jpg)
Preclass 1
Penn ESE534 Spring2010 -- DeHon9
€
2000 N +N
€
C1N log2(N)
m+C2m +C3N
When we solved for N, we found m is proportional to √N
€
C1 N log2(N) +C2 N +C3N
If we approximate log2(N) as a constant, we get
€
C4 N +C3N
![Page 10: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/10.jpg)
Preclass 3, 4
• Delay– Scale with bd?– Scale with bw?
Penn ESE534 Spring2012 -- DeHon10
![Page 11: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/11.jpg)
Penn ESE534 Spring2012 -- DeHon11
Memory
• What’s a memory?
• What’s special about a memory?
![Page 12: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/12.jpg)
Penn ESE534 Spring2012 -- DeHon12
Memory Function
• Typical:– Data Input Bus– Data Output Bus– Address
• (location or name)
– read/write control
![Page 13: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/13.jpg)
Penn ESE534 Spring2012 -- DeHon13
Memory
• Block for storing data for later retrieval
• State element
![Page 14: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/14.jpg)
Collection of Registers
• What’s different between a memory and a collection of registers?
Penn ESE534 Spring2012 -- DeHon14
![Page 15: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/15.jpg)
Penn ESE534 Spring2012 -- DeHon15
Memory Uniqueness
• Cost
• Compact state element
• Packs data very tightly
• At the expense of sequentializing access
• Example of Area-Time tradeoff– and a key enabler
![Page 16: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/16.jpg)
Penn ESE534 Spring2012 -- DeHon16
Memory Organization• Key idea: sharing
– factor out common components among state elements
– can have big elements if amortize costs– state element unique small
wordlines
Bit lines
![Page 17: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/17.jpg)
Penn ESE534 Spring2012 -- DeHon17
SRAM Memory bit
Source: http://commons.wikimedia.org/wiki/File:6t-SRAM-cell.png
![Page 18: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/18.jpg)
Penn ESE534 Spring2012 -- DeHon18
Memory Organization
• Share: Interconnect– Input bus– Output bus– Control routing
• very topology/wire cost aware design
• Note: local, abuttment wiring
![Page 19: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/19.jpg)
Penn ESE534 Spring2012 -- DeHon19
Share Interconnect
• Input Sharing– wiring– drivers
• Output Sharing– wiring– sensing– driving
![Page 20: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/20.jpg)
Penn ESE534 Spring2012 -- DeHon20
Address/Control• Addressing and Control
– an overhead – paid to allow this sharing
![Page 21: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/21.jpg)
Penn ESE534 Spring2012 -- DeHon21
Memory Organization
![Page 22: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/22.jpg)
Penn ESE534 Spring2012 -- DeHon22
Dynamic RAM
• Goes a step further
• Share refresh/restoration logic as well
• Minimal storage is a capacitor
• “Feature” DRAM process is ability to make capacitors efficiently
![Page 23: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/23.jpg)
Penn ESE534 Spring2012 -- DeHon23
Some Numbers (memory)• Unit of area = 2 (F=2
– [more next week]
• Register as stand-alone element 4K2
– e.g. as needed/used last lecture
• Static RAM cell 1K2
– SRAM Memory (single ported)
• Dynamic RAM cell (DRAM process) 1002
• Dynamic RAM cell (SRAM process) 3002
![Page 24: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/24.jpg)
DRAM Layout
Penn ESE534 Spring2012 -- DeHon24
Source: http://techon.nikkeibp.co.jp/article/HONSHI/20071219/144399/
bitline
wordline
![Page 25: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/25.jpg)
Penn ESE534 Spring2012 -- DeHon25
DRAM Latency
µProc60%/yr.
DRAM7%/yr.
1
10
100
1000
1980
1981
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
DRAM
CPU1982
Processor-MemoryPerformance Gap:(grows 50% / year)
Per
form
ance
Time
“Moore’s Law”
[From Patterson et al., IRAM: http://iram.cs.berkeley.edu/]
![Page 26: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/26.jpg)
Penn ESE534 Spring2012 -- DeHon26
Contemporary DRAM
• 1GB DDR3 SDRAM from Micron– http://www.micron.com/products/dram/ddr3/– 96 pin pakage– 16b datapath IO– Operate at 500+MHz– 37.5ns random access latency
![Page 27: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/27.jpg)
Penn ESE534 Spring2012 -- DeHon27
Memory Access Timing
• RAS/CAS access
• Optimization for access within a row
![Page 28: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/28.jpg)
Penn ESE534 Spring2012 -- DeHon28
Contemporary DRAM
• 1GB DDR3 SDRAM from Micron– http://www.micron.com/products/dram/ddr3/– 96 pin pakage– 16b datapath IO– Operate at 500+MHz– 37.5ns random access latency
![Page 29: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/29.jpg)
Penn ESE534 Spring2012 -- DeHon29
1 Gigabit DDR2 SDRAM
[Source: http://www.elpida.com/en/news/2004/11-18.html]
![Page 30: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/30.jpg)
Penn ESE534 Spring2012 -- DeHon30
Contemporary DRAM
• 4GB DDR3 SDRAM from Micron– http://download.micron.com/pdf/datasheets/modul
es/ddr3/ksf16c256_512x64hz.pdf– Operate at 800MHz– 50ns random access latency
![Page 31: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/31.jpg)
Penn ESE534 Spring2012 -- DeHon31
DRAM Latency
µProc60%/yr.
DRAM7%/yr.
1
10
100
1000
1980
1981
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
DRAM
CPU1982
Processor-MemoryPerformance Gap:(grows 50% / year)
Per
form
ance
Time
“Moore’s Law”
[From Patterson et al., IRAM: http://iram.cs.berkeley.edu/]
![Page 32: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/32.jpg)
Penn ESE534 Spring2012 -- DeHon32
Basic Memory Design Space
• Width
• Depth
• Internal vs. External Width
• Banking– To come
![Page 33: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/33.jpg)
Penn ESE534 Spring2012 -- DeHon33
Depth• What happens
as make deeper?– Delay?– Energy?
![Page 34: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/34.jpg)
Penn ESE534 Spring2012 -- DeHon34
Banking
• Tile Banks/memory blocks
• What does banking do for us? (E, D, A)?
![Page 35: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/35.jpg)
Penn ESE534 Spring2012 -- DeHon35
Independent Bank Access
• Utility? Costs and benefits?
![Page 36: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/36.jpg)
Penn ESE534 Spring2012 -- DeHon36
Memory
• Key Idea
– Memories hold state compactly
– Do so by minimizing key state storage and amortizing rest of structure across large array
![Page 37: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/37.jpg)
Penn ESE534 Spring2012 -- DeHon37
Yesterday vs. Today(Memory Technology)
• What’s changed?
![Page 38: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/38.jpg)
Penn ESE534 Spring2012 -- DeHon38
Yesterday vs. Today(Memory Technology)
• What’s changed?– Capacity
• single chip
– Integration
• memory and logic
• dram and logic
• embedded memories
– Room on chip for big memories• And many memories…
– Don’t have to make a chip crossing to get to memory
[Patterson et al., IEEE Micro April 1997]
![Page 39: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/39.jpg)
Penn ESE534 Spring2012 -- DeHon39
Important Technology Cost
• IO between chips << IO on chip– pad spacing– area vs. perimeter (4s vs. s2)– wiring technology
• BIG factor in multi-chip system designs
• Memories nice– very efficient with IO cost vs. internal area
![Page 40: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/40.jpg)
Penn ESE534 Spring2012 -- DeHon40
On-Chip vs. Off-Chip BW
• Use Micron 1Gb DRAM as example
On Chip BW: assume 8 1024b banks? assume independent 1024×1024b banks?
![Page 41: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/41.jpg)
Memory on a Virtex-6
• 40nm process node– Last generation, 28nm sampling now
• 300,000 programmable 6-input gates (6-LUTs)
• 1,064 memory banks ~ 512×72– Total ~ 38Mbits
• Operating at 600MHz
• On chip bandwidth?
Penn ESE534 Spring2012 -- DeHon41
[image from http://www.electronicsweekly.com/Articles/08/10/2009/47137/top-10-programmable-devices.htm]
![Page 42: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/42.jpg)
Penn ESE534 Spring2012 -- DeHon42
Costs Change
• Design space changes when whole system goes on single chip
• Can afford– wider busses– more banks– memory tailored to application/architecture
• Beware of old (stale) answers– their cost model was different
![Page 43: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/43.jpg)
Penn ESE534 Spring2012 -- DeHon43
What is Importance of Memory?
• Radical Hypothesis:– Memory is simply a very efficient organization
which allows us to store data compactly • (at least, in the technologies we’ve seen to date)
– A great engineering trick to optimize resources
• Alternative:– memory is a primary
• State is a primary, but state≠memory
![Page 44: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/44.jpg)
Penn ESE534 Spring2012 -- DeHon44
Admin
• HW1 and 2 graded – note feedback (even if received perfect score)
• HW4 out today
• Reading – Was for today– Nothing new for Wed., Mon.
• Office Hours: Tuesday 4:15pm
![Page 45: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/45.jpg)
Penn ESE534 Spring2012 -- DeHon45
Big Ideas[MSB Ideas]
• Memory: efficient way to hold state
• Resource sharing: key trick to reduce area
• Memories are a great example of resource sharing
![Page 46: Penn ESE534 Spring2012 -- DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories](https://reader035.vdocuments.us/reader035/viewer/2022062517/56649ee85503460f94bf9dec/html5/thumbnails/46.jpg)
Penn ESE534 Spring2012 -- DeHon46
Big Ideas[MSB-1 Ideas]
• Tradeoffs in memory organization
• Changing cost of memory organization as we go to on-chip, embedded memories