pci express signal quality testing

PCI Express (Rev 1.1) Signal Quality and Reference Clock Test Methodology Users Guide Agilent Infiniium 54855A and Infiniium DSO80000 Series Real Time Oscilloscopes September 2006 Revision 0.82

Document Number: XXXX

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2 PCI Express Signal Quality Test Methodology, Rev 0.82 XXXX>

Contents 1 Introduction ......................................................................................................................... 8

1.1 PCI Express Signal Quality Tool ............................................................................ 8 1.2 Required Equipment............................................................................................... 8

2 Test Software .................................................................................................................... 12 2.1 Installing SigTest .................................................................................................. 12

3 Calibrating the Agilent 54855A and DSO 80000 Series Digital Storage Oscilloscopes... 19 3.1 Internal Calibration : ............................................................................................. 19 3.2 Cable and Probe Calibration: ............................................................................... 25 3.3 Channel De-skew: ................................................................................................ 34

4 Test Procedure.................................................................................................................. 40 4.1 Connecting the Signal Quality Load Board .......................................................... 40

4.1.1 For System/motherboard testing: ......................................................... 40 4.1.2 For Add-in Card testing:........................................................................ 42

4.2 Transmitter Signal Quality Test ............................................................................ 45 5 PCI Express Reference Clock Phase Jitter Test Methodology ........................................ 60

5.1 PCI Express Clock Jitter Compliance Overview .................................................. 60 5.2 Measurement Setup ............................................................................................. 60 5.3 Measuring the Clock Period Trend....................................................................... 64 5.4 Performing the Clock Phase Jitter Analysis ......................................................... 77

6 Appendix A........................................................................................................................ 78

7 Appendix B........................................................................................................................ 80

PCI Express Signal Quality Test Methodology, Rev 0.81 XXXX> 3

Figures Figure 1-1 Accessories provided with Agilent 54855A oscilloscope .................................. 9 Figure 1-2 Connectors Example 1 .................................................................................... 11 Figure 1-3 General Connection Example ......................................................................... 11 Figure 2-1 SigTest Installation File Selection ................................................................... 12 Figure 2-2 SigTest Installation Wizard.............................................................................. 13 Figure 2-3 SigTest Installation Agreement ....................................................................... 14 Figure 2-4 SigTest Installation Readme File..................................................................... 15 Figure 2-5 SigTest Installation Directory Selection........................................................... 16 Figure 2-6 SigTest Installation Confirmation..................................................................... 17 Figure 2-7 SigTest Installation Successful........................................................................ 18 Figure 2-8 SigTest Installation Restart ............................................................................. 18 Figure 3-1 Accessing the Calibration Menu...................................................................... 20 Figure 3-2 Oscilloscope Calibration Menu........................................................................ 21 Figure 3-3 Calibration Cable Connection Example (DSO80000 Series).......................... 22 Figure 3-4 Time Scale Calibration Menu .......................................................................... 23 Figure 3-5 Calibration Status Screen................................................................................ 24 Figure 3-6 Vertical Input Calibration Connections (Cable on Channel 3 not shown) ....... 25 Figure 3-7 Channel Setup Window................................................................................... 26 Figure 3-8 Probe Setup Window....................................................................................... 27 Figure 3-9 User Defined Probe Window........................................................................... 28 Figure 3-10 Probe Calibration Window............................................................................. 29 Figure 3-11 Calibration Window ....................................................................................... 29 Figure 3-12 Probe Calibration Done Window ................................................................... 30 Figure 3-13 Probe Calibration Window............................................................................. 30 Figure 3-14 Calibration Window ....................................................................................... 31 Figure 3-15 Calibration Window ....................................................................................... 31 Figure 3-16 Calibration Window ....................................................................................... 32 Figure 3-17 Calibration Window ....................................................................................... 33 Figure 3-18 De-skew Connection ..................................................................................... 34 Figure 3-19 Load De-skew Setup ..................................................................................... 36 Figure 3-20 Channel Skew ............................................................................................... 37 Figure 3-21 Skew Minimized............................................................................................. 38 Figure 3-22 De-skewing Procedure .................................................................................. 39 Figure 4-1 SMA Probing Option........................................................................................ 40 Figure 4-2 Resistor Terminations for Lanes without SMA Probing .................................. 41 Figure 4-3 Connecting Up the PCI Express Signal Quality Test Fixture .......................... 41 Figure 4-4 Rev 1.1 Compliance Baseboard (CBB1) Add-in Card Fixture ........................ 42 Figure 4-5 CBB SMA Probing Option ............................................................................... 43 Figure 4-6 CBB Active Probing Option ............................................................................. 44 Figure 4-7 Load Setup for Transmitter Test...................................................................... 45 Figure 4-8 Waveform Example ......................................................................................... 46 Figure 4-9 Waveform Clipping Example ........................................................................... 47 Figure 4-10 View Entire Waveform Capture ..................................................................... 48 Figure 4-11 Setup to Save CSV........................................................................................ 49 Figure 4-12 Opening the SigTest User GUI...................................................................... 50 Figure 4-13 Signal Quality Eye Rendering Program Main Menu...................................... 51 Figure 4-14 Import the CSV Data File .............................................................................. 52 Figure 4-15 Verify Data Button ......................................................................................... 53 Figure 4-16 Error Window Example.................................................................................. 54 Figure 4-17 Results Screen .............................................................................................. 54 Figure 4-18 Results Button ............................................................................................... 55


Figure 4-19 Test Report.................................................................................................... 56 Figure 4-20 Non Transition Eyes ...................................................................................... 57 Figure 4-21 Transition Eyes.............................................................................................. 58 Figure 4-22 Voltage Data.................................................................................................. 59 Figure 5-1 Agilent Infiniimax 1134A Socket Probe Adapter ............................................. 61 Figure 5-2 Agilent Infiniimax Probe Connection to the Compliance Load Board ............. 61 Figure 5-3 Agilent Infiniimax Probe and CLB placed in PCI-Express System Slot .......... 62 Figure 5-4 PCI-Express Reference Clock Signal ............................................................. 63 Figure 5-5 PCI Express Reference Clock Signal (after Autoscale) .................................. 64 Figure 5-6 Changing the Acquisition Setup ...................................................................... 65 Figure 5-7 Changing the Acquisition Sample Rate and Memory Depth........................... 66 Figure 5-8 Changing the Acquisition Sample Rate and Memory Depth........................... 67 Figure 5-9 Acquiring 3ms of Data ..................................................................................... 68 Figure 5-10 Invoking the Jitter Wizard .............................................................................. 69 Figure 5-11 Jitter Wizard Initial Dialog Screen ................................................................. 70 Figure 5-12 Jitter Wizard Initial Settings ........................................................................... 70 Figure 5-13 Jitter Wizard: Setting Up a Period Measurement .......................................... 71 Figure 5-14 Jitter Wizard: Setting Voltage Thresholds ..................................................... 71 Figure 5-15 Jitter Wizard: Unselecting the Measurement Histogram Function................ 72 Figure 5-16 Jitter Wizard: Selecting the Measurement Trend Function ........................... 72 Figure 5-17 Jitter Wizard: Unselecting Smoothing ........................................................... 73 Figure 5-18 Jitter Wizard: Unselecting Jitter Spectrum Function ..................................... 74 Figure 5-19 Jitter Wizard: Finishing the Setup.................................................................. 74 Figure 5-20 Showing the Clock and the Measurement Trend of the Clock Period Jitter . 75 Figure 5-21 Saving the Clock Period Jitter Trend to a File............................................... 76 Figure 5-22 Choosing a File Name................................................................................... 76 Figure 5-23 The PCI-Sig Clock Jitter Tool Startup Screen............................................... 77 Figure 5-24 Phase Jitter Test Results .............................................................................. 77


Revision History

Document No. Rev. No. Description Rev. Date

<XXXX> 0.5 Initial Draft. 8-15-2003

0.6 Updated for SigTest 2.0 Beta 10-3-2003

0.7 Formatting and minor updates 10-13-2003

0.72 Updated figures and calibration procedure, minor edits 12-04-2003

0.8 Clarified procedures with more screenshots. Change procedure to perform analysis on math function.

1-30-2004

0.81 Minor edits and corrections. 3-25-2004

0.82 Updated to reflect DSO80K Series, PCIe 1.1 Procedures for Signal Quality and Ref Clock measurement and SigTest 2.1

9-15-2006


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Introduction

1 Introduction

1.1 PCI Express Signal Quality Tool

The PCI Express Signal Quality Tool was developed to help verify product compliance to the PCI Express Base Specification and CEM Specification. The PCI Express Signal Quality Tool consists of a series of tests used to evaluate PCI Express systems/motherboards and PCI Express add-in card products. The test tool kit contains the following components:

• PCI Express Signal Quality Test Methodology documentation

• SigTest Post Capture Analysis Software, available for download at: http://www.pcisig.com/specifications/pciexpress/compliance/compliance_library

• PCI Express Compliance Load Board (CLB) for system testing.

• PCI Express Rev 1.1 compliance Base Board (CBB1) for add-in card testing. Compliance fixtures CLB and CBB1 can be ordered from the PCI-SIG at http://www.pcisig.com/specifications/order_form

• Oscilloscope Configuration Files

• Sample PCI Express Test Data

This document contains the PCI Express Signal Quality Test Procedure for gauging the signal quality of implemented designs. The following sections will contain detailed procedures on calibrating test equipment and setting up the Signal Quality Load Board as well as information on how to use the SigTest post analysis software. Sample outputs will also be provided for reference.

Note: The tests described in this document are intended to provide a quick check of the electrical health of the DUT. This testing is not a replacement for an exhaustive test validation plan.

1.2 Required Equipment

The list of equipment cited in this example is for reference purposes only. The test methodology contained in this document was developed using the following test equipment:

• Real Time Digital Storage Oscilloscope

o Any Real Time Digital Storage Oscilloscope with a minimum 6 GHz bandwidth and capable of a sampling rate of 20GS/s (50 ps sample interval) can be used. Agilent oscilloscopes meeting this requirement include the Infiniium 54855A (6GHz) , DSO80604B (6GHz), DSO80804B (8GHz), DSO81004B (10GHz), DSO81204B (12 GHz), DSO81304B (13 GHz), and all DSO80000A series Oscilloscopes.


http://www.pcisig.com/specifications/pciexpress/compliance/compliance_library

http://www.pcisig.com/specifications/order_form

Introduction

o This document was developed using the Agilent Infiniium DSO81304B 40GS/s Digital

Storage Oscilloscope. This same procedure can be use with the other supported Infiniium oscilloscopes listed above. The 54855A supports up to 1Meg record captures. Depending on the memory depth of the Agilent oscilloscope you are using, you may repeat the tests described in this document multiple times to achieve the level of statistical relevance you desire.

• Active or differential probes, qty = 1 (two probes required for common mode measurements)

o For best results, the probe bandwidth must be much greater than that of the signal being measured.

o This document was developed using the 1169A – Agilent InfiniiMax 12 GHz active probe

• Keyboard, qty = 1, (provided with the Agilent 54855A, DSO80000A series or appropriate DSO 80000B series oscilloscopes)

• Mouse, qty = 1, (provided with the Agilent 54855A , DSO80000A series or appropriate DSO 80000B series oscilloscopes)

• Precision 3.5 mm BNC to SMA male adapter, Agilent p/n 54855-67604, qty = 2 (provided with the Agilent 54855A, DSO80000A series or appropriate DSO80000B series oscilloscopes)

• Calibration cable (provided with the Agilent 54855A, DSO80000A series or appropriate DSO 80000B series oscilloscopes)

• BNC shorting cap (only necessary with the Agilent 54855A oscilloscope)

Figure 1-1 below shows a drawing of the above connector items.

Figure 1-1 Accessories provided with Agilent 54855A oscilloscope

• 50-ohm Coax Cable With SMA Male Connectors – 24-inch or less RG316/U or similar, qty = 2, matched length.

• SMA T-adapter

• BNC to SMA male adapter, qty = 1


Introduction

• Test PC Computer – Minimum configuration of Intel Pentium III 700MHz with 256MB memory

or equivalent loaded with Microsoft Windows XP Professional or 2000 Professional operating system. The PC in the Agilent 54855A, DSO80000A series or appropriate DSO80000B series oscilloscopes meets these requirements, and can be used as the Test PC Computer.

• A second monitor is required if the 54855A, DSO80000A series or appropriate DSO80000B series oscilloscopes is used as the Test PC.


Introduction

Figure 1-2 below shows an example of the above mentioned cables and connectors needed.

Figure 1-2 Connectors Example 1

Although this test methodology document features the Agilent Infiniium DSO81304B (the "test scope"), equivalent 3rd party scopes and probes can be substituted.

Figure 1-3 below shows the general connection methodology used for the signal quality test. A fixture board is used to connect the oscilloscope to a PCI Express motherboard or adapter card. The oscilloscope is used to capture a compliance signal from the device under test. A PC Windows® application is used to analysis the signal data captured by the oscilloscope, and report pass/fail criteria.

Figure 1-3 General Connection Example


Test Software

2 Test Software

2.1 Installing SigTest SigTest is the post analysis software packaged with the PCI Express Signal Quality Tool. Data captured with the Digital Storage Oscilloscope is imported into this software for analysis. SigTest is capable of rendering the signal quality eye captured with the Digital Storage Oscilloscope. The eye is then checked against the specified pass/fail boundaries.

OS Requirements: Microsoft Windows XP or Windows 2000 Professional operating system is required. If desired, SigTest can be installed on the Agilent 54855A, DSO80000A series or appropriate DSO80000B series oscilloscope’s PC, which meets these requirements.

NOTE: If SigTest is used on the Agilent oscilloscope, a second display monitor is required to be connected to the oscilloscope to display the SigTest application. The SigTest application will not fit on the oscilloscope's built-in display.

Perform the following steps to install the SigTest software…

1. Download the SitTest Version 2.x (to a subdirectory on your Windows Desktop) from:

http://www.pcisig.com/specifications/pciexpress/compliance/compliance_library 2. Open the subdirectory that the SigTest installation file was copied to, as shown in Figure 2-1 below. 3. Double click on SigTest.msi file.

Figure 2-1 SigTest Installation File Selection


http://www.pcisig.com/specifications/pciexpress/compliance/compliance_library

Test Software

4. Referring to Figure 2-2 below, perform the following steps…

a. Make sure there are no Windows programs running in the background. b. Click the Next > button to start the installation process.

Click Next

Figure 2-2 SigTest Installation Wizard


Test Software


a. Read the license agreement. b. Select the I accept the license agreement radio button c. Click on the Next > button to continue

Read Agreement

Accept Agreement

Click Next

Figure 2-3 SigTest Installation Agreement


Test Software


a. Read the Readme File b. Click the Next > button to continue.

Read Readme Document

Click Next

Figure 2-4 SigTest Installation Readme File


Test Software


a. It is recommended you use the default destination directory. However, if you would like to install SigTest in a different directory than the default locations, click the Browse button to select a different location.

b. Click the Next > button to continue.

Click Browse to install in a different directory.

Click Next

Figure 2-5 SigTest Installation Directory Selection


Test Software

8. Referring to Figure 2-6, perform the following steps…

a. Click the Next > button to start the file installations process. b. It will take a few seconds for all the files to be installed.

Click Next to install files

Figure 2-6 SigTest Installation Confirmation


Test Software


a. Click the Finish button b. Restart the computer, if prompted to as shown in Figure 2-8, by clicking Yes. c. The SigTest installation is completed.

Figure 2-7 SigTest Installation Successful

Click to Restart

Figure 2-8 SigTest Installation Restart


Calibrating the Agilent 54855A and DSO 80000 Series Digital Storage Oscilloscopes

3 Calibrating the Agilent 54855A and DSO 80000 Series Digital Storage Oscilloscopes

3.1 Internal Calibration : This will perform an internal diagnostic and calibration cycle for the oscilloscope. For the Agilent oscilloscope, this is referred to as Calibration. This Calibration will take about 20-60 minutes. Perform the following steps…

1. Setup the oscilloscope with the following steps.

a. Connect the keyboard, mouse, and power cord to the rear of the oscilloscope.. b. If SigTest is being used on the oscilloscope, then connect a second monitor to the VGA

connector located near the LAN port, on the rear of the oscilloscope. c. Plug in the power cord. d. Turn on the oscilloscope by pressing the power button located on the lower left of the front

panel. e. Allow the oscilloscope to warm up at least 30 minutes prior to starting the calibration procedure

in step 3 below. 2. Locate and prepare the accessories that will be required for the internal calibration…

a. Locate the BNC shorting cap (required for 54855 only). b. Locate the calibration cable. c. Locate the two Agilent precision SMA/BNC adapters. d. Attach one SMA adapter to one end of the calibration cable - hand tighten snuggly. e. Attach the other SMA adapter to the other end of the calibration cable - hand tighten snuggly.




a. Click on the Utilities Calibration menu to open the Calibration window.

Click here to open thecalibration window.

Figure 3-1 Accessing the Calibration Menu



4. Referring to Figure 3-2 below, perform the following steps to start the calibration… a. Uncheck the Cal Memory Protect checkbox. b. Click the Start button to begin the calibration.

Uncheck this first

Then click here to start

Figure 3-2 Oscilloscope Calibration Menu



5. Follow the on screen instructions…

a. You will be promoted to disconnect everything from all the inputs, click the OK button. b. If you own an Agilent Infiniium 54855A, you will then be prompted to connect BNC shorting

cap to a specified input. Install the BNC shorting cap by pressing it on the specified input BNC, and turning right. Click the OK button after moving the BNC cap to each specified channel.

c. Then you will be prompted to connect the calibration cable with SMA adapters between the Aux Out and a specified input, as shown in the example in Figure 3-3 below. Install the SMA adapter by pressing it on input BNC, and hand tightening the outer ring turning right. Click the OK button after connecting the cable as prompted.

Precision SMA Adapter on Aux Out

Calibration Cable

Precision SMA Adapter on Channel 1 Input.

Figure 3-3 Calibration Cable Connection Example (DSO80000 Series)



d. Early during the calibration of channel 1, you will be prompted to perform a Time Scale

Calibration, as shown in Figure 3-4 below. e. Click on the Std button to continue the calibration, using the Factory default calibration factors. f. When the calibration procedure is complete, you will be prompted with a Calibration Complete

message window. Click the OK button to close this window.

Click Std

Figure 3-4 Time Scale Calibration Menu




a. Confirm that the Vertical and Trigger Calibration Status for all Channels passed. b. Click the Close button to close the calibration window. c. The internal calibration is completed. d. Read NOTE below.

Verify Calibration Passed Close this menu

Delta CalibrationTemperature

Figure 3-5 Calibration Status Screen

NOTE: These steps do not need to be performed every time a test is run. However, if the ambient temperature changes more than 5 degrees Celsius from the calibration temperature, this calibration should be performed again. The delta between the calibration temperature and the present operating temperature is shown in the Calibration Menu.



3.2 Cable and Probe Calibration: Perform a 50-ohm direct-coupled input calibration for the SMA interface of channel 1 and channel 3. This calibration compensates for gain, offset, and skew errors in cables and probes. Perform the following steps. 1. Referring to the Figure 3-6 below, perform the following steps…

a. Locate and connect one of the Agilent precision SMA adapters to the Channel 1 oscilloscope input.

b. Locate and connect the other Agilent precision SMA adapter to the Channel 3 oscilloscope input. c. Locate and connect one end of one of the RG-316 cables to the SMA adapter on Channel 1. d. Locate and connect one end of the other RG-316 cable to the SMA adapter on Channel 3. e. Locate and connect the non-Agilent SMA/BNC adapter to the Aux Out BNC on the oscilloscope.

Both the Infiniium 54855A and DSO80000 Series support an Aux Out connector on the front panel, they are in slightly different locations. Note the label on the front panel.

f. Connect the other end of the cable attached to Channel 1 to the SMA adapter on the Aux Out.

Channel 1

Channel 3 Aux Out (54855A)

Figure 3-6 Vertical Input Calibration Connections (Cable on Channel 3 not shown)




a. Click on the Setup Channel 1 menu to open the Channel Setup window. b. Click the Probes button in the Channel Setup window, to open the Probe Setup window.

Click Setup Channel 1

Click here for ProbeSetup Menu

Figure 3-7 Channel Setup Window




a. Click the Configure Probing System button, and then click on User Defined Probes.

Click here Then click here

Figure 3-8 Probe Setup Window




a. Click on the Calibrate Probe button to open the Probe Calibration window.

Click Here

Figure 3-9 User Defined Probe Window




a. Select the Calibrated Atten/Offset Radio Button b. Click the Start Atten/Offset Calibration Button to open the Calibration window.

Select Calibrated Atten/Offset

Then Click Here

Figure 3-10 Probe Calibration Window

6. Referring to Figure 3-11 shown below, perform the following steps… a. Ignore the instructions shown in the dialog box. b. Click the OK button on the Calibration window. c. The calibration should complete in about 10 seconds.

Click OK

Figure 3-11 Calibration Window



7. Referring to Figure 3-12 below, perform the following steps… a. Click OK to close the Probe Calibration Done window.

Click to close this window

Figure 3-12 Probe Calibration Done Window

8. Referring to Figure 3-13 below, perform the following steps… a. Select the Calibrated Skew Radio button in the Probe Calibration window b. Click the Start Skew Calibration button

Select Calibrated Skew

Then Click Here

Figure 3-13 Probe Calibration Window



9. Referring to Figure 3-14 shown below, perform the following steps…

a. Ignore the instructions shown in the dialog box. b. Click the OK button on the Calibration window. c. The calibration should complete in about 10 seconds.

Click OK


10. Referring to Figure 3-15 below, perform the following steps… a. Click OK to close the Probe Calibration Done window.

Click to close this window





a. Click the Close button to close this window.

Click Close





a. Click on the Channel 3 tab.

Click on Channel 3 Tab


13. Referring to Figure 3-6, perform the following steps… a. Disconnect the RG-316 cable connected to the SMA adapter on the Aux Out. b. Connect the other end of the RG-316 cable connected to the SMA adapter on Channel 3, to the

SMA adapter on the Aux Out. 14. Repeat steps 3 through 11 of this section to calibrate the cable on Channel 3. 15. Click the Close button on the Probe Setup window (Figure 3-17) to close this window. 16. Click the Close button on the Channel Setup window (Figure 3-7) to close this window. 17. The Cable and Probe calibration is complete. 18. Read the NOTE below.

NOTE: Each cable is now calibrated for the oscilloscope channel it is connected to. Do not switch cables between channels or other oscilloscopes, or it will be necessary to them calibrate again. It is recommended that the cables be labeled with the channel there were calibrated for.



3.3 Channel De-skew: This procedure ensures that the timing skew errors between channel 1 and channel 3 are minimized. Perform the following steps.

1. Referring to Figure 3-18 below, perform the following steps.

a. Do not disconnect the RG-316 cables from either the Channel 1 or Channel 3 SMA adapters. b. If not already installed, install the non-Agilent SMA adapter on the oscilloscope Aux Out. c. Disconnect any cable connected to the SMA adapter on the Aux Out. d. Locate and connect the middle branch of the SMA Tee to the SMA adapter on the Aux Out

BNC. e. Connect the far end of the cable from the Channel 1 SMA adapter, to one branch of the SMA

Tee on the Aux Out. f. Connect the far end of the cable from the Channel 3 SMA adapter, to the other branch of the

SMA Tee on the Aux Out.

SMA Tee onAux Out

Channel 1 Channel 3

Figure 3-18 De-skew Connection




a. Select the File Load Setup menu to open the Load Setup window. b. Navigate to the directory location that contains the INF_SMA_Deskew.set setup file. If the setup

file is not available, it can be created by following the instructions in Error! Reference source not found..

c. Select the INF_SMA_Deskew.set setup file by clicking on it. d. Click the Load button to configure the oscilloscope from this setup file.

3. Then click hereto load setup file.

1. Click File Load Setup

2. Then find and selectINF_SMA_Deskew.set

Figure 3-19 Load De-skew Setup



The oscilloscope display should look similar to Figure 3-20 below. A falling edge of the square wave is shown in a 200ps/div horizontal scale. The upper portion of the screen shows channel 1 (yellow trace) and channel 3 (purple trace) superimposed on one another. The lower portion of the screen is the differential signal (green trace) of channel 1 minus channel 3. The top two traces provide for visual inspection of relative time skew between the two channels. The bottom trace provides for visual presentation of unwanted differential mode signal resulted from relative channel skew (and to a much lesser extent from other inevitable channel mismatch parameters like gain and non-linearity). Figure 3-20 is an example of exaggerated skew between channel 1 and channel 3, measured to be about 50ps with the cursor.

Skew between Channel 1and Channel 3

Differential signal notflat, indicating mismatchin skew.

Figure 3-20 Channel Skew



Figure 3-21 below shows the desired effect of no skew between the cables. Note that the channel 1 (yellow trace), channel 3 (purple trace) traces overlap, and the differential signal (green trace) is flat. If this is not the case, then perform the following steps to reduce the skew between channels 1 and 3.

Channel 1 and 3traces overlap,indicating no skewerror.

Flat differentialsignal, indicating noskew error.

Figure 3-21 Skew Minimized



3. Referring to Figure 3-22, perform the following steps to de-skew the channels…

a. Click on the Setup Channel 1 menu to open the Channel Setup window. b. Move the Channel Setup window to the left so you can see the traces. c. Adjust the Skew by clicking on the or arrows, to achieve the flattest response on the

differential signal (green trace). d. Click the Close button on the Channel Setup window to close it. e. The de-skew operation is complete. f. Disconnect the cables from the Tee on the Aux Out BNC. Leave the cables connected to the

Channel 1 and Channel 3 inputs. g. Read the NOTE below.

Click Setup Channel 1 to openthe Channel Setup window.

Then click Close when done.

Then adjust the Skew left or right tomaximize flatness of green trace.

Figure 3-22 De-skewing Procedure

NOTE: Each cable is now calibrated for the oscilloscope channel it is connected to. Do not switch cables between channels or other oscilloscopes, or it will be necessary to them calibrate again. It is recommended that the cables be labeled with the channel there were calibrated for.


Test Procedure

4 Test Procedure

4.1 Connecting the Signal Quality Load Board There are multiple pairs of SMA connectors on the PCI Express Signal Quality Test Fixtures. Each pair maps to the transmit differential pair or receive differential pair for the Add-in Card or System/motherboard transmitter lane under test.

4.1.1 For System/motherboard testing: 1. With the system/motherboard powered off, connect the Compliance PCI Express Signal Quality Load

Board into the connector under test. The PCI Express Signal Quality Load Board has edge fingers for x1, x4, x8 and x16 connectors. Not all lanes have SMA probing options. For signal quality testing of the remaining lanes you will need to use a high bandwidth differential or single ended probes (see Figure 4-6). Minimum recommended BW of 6 Ghz.

The PCI Express Signal Quality Load Board will cause a PCI Express 1.0a Base Specification System/motherboard to enter the compliance sub-state of the polling state. During this state the device under test will repeatedly send out the compliance pattern defined in the PCI Express Base Specification.

Figure 4-1 SMA Probing Option


Test Procedure

Figure 4-2 Resistor Terminations for Lanes without SMA Probing

2. Connect cables up as follows: a. Digital Storage Oscilloscope channel 1 to TX LANE 1 P (where Lane 1 is under test) b. Digital Storage Oscilloscope channel 3 to TX LANE 1 N (where Lane 1 is under test)

Figure 4-3 Connecting Up the PCI Express Signal Quality Test Fixture


Test Procedure

4.1.2 For Add-in Card testing: 1. With the PWR switch on the Rev 1.1 Compliance Base Board (CBB1) power supply switched in the

off position, connect the power supply connector to the Add-in card test fixture, and connect the device under test add-in card to the by-16 (x16) connector slot.

Figure 4-4 Rev 1.1 Compliance Baseboard (CBB1) Add-in Card Fixture


Test Procedure

Figure 4-5 CBB SMA Probing Option

2. Connect cables up as follows: a. Digital Storage Oscilloscope channel 1 to the TX LANE P under test (where Lane 1 is under test

in this example shown in Figure 4-5 above) b. Digital Storage Oscilloscope channel 3 to the TX LANE N under test (where Lane 1 is under

test in this example shown in Figure 4-5 above) 3. Connect adequate load to the power supply to assure it is regulating and turned on. Generally, one IDE

or SATA hard drive will provide adequate load. 4. Turn on the power supply and turn on the PWR switch on the CBB1 board. The DS1 LED (located

near the center of CBBB1) should turn on.


Test Procedure

Figure 4-6 CBB Active Probing Option


Test Procedure

4.2 Transmitter Signal Quality Test 1. Referring to Figure 4-7 below, perform the following steps.

a. Click File Load Setup to open the Load Setup window. b. Navigate to the directory location that contains the INF_PCIE_SMA_M2_CH13_Test1_5.set

setup file. If the setup file is not available, it can be created by following the instructions in Error! Reference source not found..

c. Select the INF_PCIE_SMA_M2_CH13_Test1_5.set setup file by clicking on it. d. Click the Load button to load button to configure the oscilloscope from the setup file.

3. Then click hereto load setup file.

1. Click File Load Setup

2. Then find and selectINF_PCIE_SMA_M2_CH13_TEST1_5.set

Figure 4-7 Load Setup for Transmitter Test

This setup will configure the oscilloscope to display channel 1 (TX+) and channel 3(TX-) in the upper window, and the differential signal (TX) in the lower window. 2. Using the INF_PCIE_SMA_M2_CH13_Test1_5.set setup file, the Digital Storage Oscilloscope will

capture 10 uS at 20 GS/s acquisition rate. This provides about 25,000 Unit Intervals of PCI Express samples.


Test Procedure

Referring to Figure 4-8 below, perform the following step to maximize use of the oscilloscope's dynamic range… a. Click on the Channel 1 sensitivity to open the numeric keypad. b. Using the keypad, adjust the Channel 1 sensitivity to maximize the Channel 1 signal (yellow

trace) amplitude without clipping. Refer to Figure 4-9 for an example of clipping traces. Repeat step a to open keypad again.

c. Click on the Channel 3 sensitivity to open the numeric keypad. d. Using the numeric keypad, set the Channel 3 sensitivity to be the same as Channel 1. e. Verify that Channel 3 is not clipping also. If necessary, reduce the sensitivity on both Channel

1 and Channel 3 to prevent clipping on Channel 3. Keep the sensitivity settings the same between Channel 1 and Channel 3.

a. Click here toadjust channel 1

b. Adjust Sensitivity

c. Click here toadjust channel 3

Figure 4-8 Waveform Example


Test Procedure

3. Referring to Figure 4-9 below, verify that the signal is a valid compliance pattern…

a. Click on the Stop button to stop data acquisition (or you can push the Stop key on the oscilloscope's control panel.)

b. A single lane device should look like the TX Differential signal (green trace) shown. This is a K28.5-, D21.5+, K25.5+, D10.2- repeating sequence.

c. Multi-lane devices will insert additional K28.5 delay symbols occasionally

ClippingClipping

Stop Button

K28.5- D21.5+ D10.2+-K28.5+

Figure 4-9 Waveform Clipping Example


Test Procedure

4. Referring to Figure 4-10 below, perform the following steps to view the entire waveform capture on

screen… a. Click on the Horizontal Timebase setting, and use the numeric keypad to set it to 1 uS b. The display should now look as shown in to Figure 4-10, showing the entire 10uS of waveform

captured.

Click here. Set to 1 uSusing the numerickeypad window.

Figure 4-10 View Entire Waveform Capture


Test Procedure

5. Referring to Figure 4-11 below, perform the following steps to save the captured differential signal as

a Comma Separated Value (CSV) file: a. Select the File Save Waveform menu to open the Save Waveform window.. b. Select XY Pairs Files (*.CSV) in the Save as type dropdown box. c. Check the Include scale factors check box d. Select Function 2 in the Source Waveform dropdown menu. e. Navigate to the desired destination folder as applicable. f. Enter a desired file name g. Click the Save button to save the function 2 CSV file.

a. Click File Save Waveform e. Navigate to desired directory.

d. Select Function 2

f. Enter filename

g. Click Save

b. Select (*.csv) format

c. Check Include scale factors

Figure 4-11 Setup to Save CSV

6. (This step is only necessary if the SigTest analysis is not being performed on the oscilloscope's PC) Copy the saved CSV files from the oscilloscope to a desired folder in the computer with the PCI Express Signal Quality Eye Rendering Program (SigTest). This can be done easily with a USB memory drive, LAN cable, or the CDRW drive in the oscilloscope.


Test Procedure

7. Referring to Figure 4-12 below, invoke SigTest (PCI Express Post Capture Analysis Software).

a. If SigTest is being used on the oscilloscope, it will be necessary to minimize the oscilloscope window to access the Windows Start button.

b. Click on the Windows Start Programs SigTest 2.0 Beta SigTest 2.0 Beta menu to launch the SigTest application.

Figure 4-12 Opening the SigTest User GUI


Test Procedure

8. Referring to Figure 4-13, perform the following steps…

a. Uncheck the Separate Files Per Channel checkbox. b. Check the Time Stamps In File box. c. Click the upper Browse button to open the Select data file window.

Select file

Check

5.0E-11 for 20 GSa/s 2.5E-11 for 40 GSa/s

Figure 4-13 Signal Quality Eye Rendering Program Main Menu


Test Procedure

9. Referring to Figure 4-14 below, perform the following steps to select the desired file for analysis…

a. Navigate to the directory where the CSV files are stored b. Click on the desired file to select it c. Click the Load Button

Select directory

Select file

Click Load

Figure 4-14 Import the CSV Data File


Test Procedure


a. Click on the Verify Valid Data File button. This runs some quick checks to see if valid test data was selected. If the data is the correct format, the TEST button will become selectable. Otherwise, it will report “Unable to process data file.” in the program status bar at the bottom of the screen, and the error window shown below in Figure 4-16 will be displayed:

b. Select the Test All check box unless you are debugging test failures. c. In the Template File selection window, select the template that corresponds to the probing

location template that you wish to test to… 1. For add-in card testing, select the PCIEX_TX_ADD_CON_250UI template. 2. For system testing, select the PCIEX_TX_SYS_CON_250UI template.

d. Click the Test button.

a. Click Verify

c. Pick template

b. Pick technology

d. Click Test

Figure 4-15 Verify Data Button

:


Test Procedure

Figure 4-16 Error Window Example

When the program is finished analyzing the test data, a results window is displayed as shown in Figure 4-17 below.

Displays Test Report

Figure 4-17 Results Screen

The program status bar at the bottom of the screen also should indicate the following:


Test Procedure

The eye violations field indicates the number of data points that fall within the eye pattern exclusion areas (Red Zones in eye plots).

The other fields are direct calculations of parameters obtained from the test data. The radio buttons next to the results field will be green if the item is within the limits set in the template file. The button will be red if they item fails.

The values in the template file can be defined by the user to accommodate the probing location (for example, transmitter eye diagram) and any margin the designer wishes to test for.

Referring to Figure 4-18 below, if the the results window is closed, it can be recalled by clicking on the Results button on the Signal Test window.

Displays Transition Eyes

Displays Non Transition Eyes

Displays Voltage Data

Displays Full Test Results

Figure 4-18 Results Button


Test Procedure

Selecting the View HTML Report button in the results screen (Figure 4-13) will open the report that is generated by the SigTest tool. An example of this report is shown in Figure 4-19 below. This report includes an eye diagram plot of the worst non-transition signal eye, worst transition signal eye, the signal data plot and the following test summary.

Figure 4-19 Test Report


Test Procedure

Selecting the Worst Non Transition Eyes button on the Signal Test window (Figure 4-18), will allow you to view the eye diagram for de-emphasized bits (data bits that do not follow a transition of the data lines), as shown in Figure 4-20 below.

The non-transition and transition eye pattern windows have 6 display options. The VIEW ALL EYES display is the default option and is an overlay of all of the other 5 eye patterns that can be selected. Each of the 5 worst case eye patterns are created from the 250 UI of contiguous data. The data is the center 250 UI within a 3500 UI window of the exported scope record.

The individual eye diagrams can be viewed separately or all together by clicking on the appropriate button at the bottom of the screen.

Figure 4-20 Non Transition Eyes


Test Procedure

Selecting the Worst Transition Eyes button on the Signal Test window (Figure 4-18) will allow you to view the eye diagrams for the bits following a transition in the differential signal, as shown in Figure 4-21 below. Note that the specification defines different eye template requirements depending on whether the data is a transition or non-transition (de-emphasis) bit.

The individual eye diagrams can be viewed separately or all together by clicking on the appropriate button at the bottom of the screen.

Selecting the WORST JITTER button displays the eye pattern associated with those transitions that have the worst case jitter on them for all of the test data that was analyzed. In general, one should expect the jitter of a transition bit to be the worst case since the voltage of the signal prior to the transition can vary depending on whether it was a de-emphasized bit or not.

Figure 4-21 Transition Eyes


Test Procedure

Selecting the Voltage Data button on the Signal Test window (Figure 4-18) displays the differential signal voltage for the test data that was analyzed, as shown in Figure 4-22 below. Location of eye failures will be identified with red dots on this display.

Figure 4-22 Voltage Data

Repeat the process for all other Lanes to be tested.


PCI Express Reference Clock Phase Jitter Test Methodology

5 PCI Express Reference Clock Phase Jitter Test Methodology

5.1 PCI Express Clock Jitter Compliance Overview For Measuring the phase jitter of the PCI Express Reference Clock you will be using the Intel developed Compliance Load Board (or CLB) along with you target. A typical target is assumed to be a PCI Express motherboard. You will use your DSO 80000 series real time oscilloscope to take a measurement trend of the clock period. This data is then saved in a file and a PCI-SIG clock jitter tool is then used to calculate the clock’s phase jitter. Under Rev 1.1 of the PCI Express Specification, the clock should not have more than 86ps of phase jitter between 1.5 and 22MHz.

5.2 Measurement Setup To perform the PCI Express Reference Clock measurement you will need the following.

• Agilent DSO 80000 Series Infiniium Oscilloscope (Minimum of 6GHz of bandwidth)

• EZ-JIT Software Jitter Package for the scope

• Agilent 1134A 7GHz Infiniimax Probe with socket probe head adapter (an 1169A 12Ghz Probe Amplifier can be substituted)

• PCI-SIG CLB

• PCI-SIG Clock Jitter Tool

The first step is to connect the Agilent 1134A probe to the PCI-SIG CLB.

It is important to make sure the socket probe head adapter for connecting to the reference clock header pins is properly connected to the Infiniimax socked probe tip.



Figure 5-1 Agilent Infiniimax 1134A Socket Probe Adapter

Once you have the probe tip and socket probe tip adapter the next step is to connect the probe to the CLB.

Figure 5-2 Agilent Infiniimax Probe Connection to the Compliance Load Board

Connect the socket probe tip to the REFCLK header pin on the CLB. There are two REFCLK access points on the CLB via headers. One is on the x16 side of the CLB (shown above) the other is on the x1 side of the CLB. Some motherboards require the presence signal to be asserted before the reference clock

Infiniimax Socket Probe Tip

Infiniimax Socket Probe Tip adapter for header pins

Note Polarity. P (Positive) signal from REFCLK needs to be connected to + input on probe

Place jumper here to enable presence if necessary.

2pf Compliance Load Capacitor

Connect to REFCLK header on the CLB (x1 or x16 side)



will be enabled. If you connect up the probe into your system and do not see a clock when you turn the system on, you may want to try putting a jumper on the presence enable header.

With the probe properly connected to the correct header, you then place the CLB and probe assembly into your target motherboard. Make sure your motherboard or system is turned off and unpowered when you insert the CLB.

CLB Inserted into x16 slot on motherboard

Figure 5-3 Agilent Infiniimax Probe and CLB placed in PCI-Express System Slot

Be careful to ensure that you do not bend the header pins or cause any shorts and be sure to seat the CLB properly.

Connect the Agilent 1134A Infiniimax probe amplifier to Channel 1 on your DSO80000 series oscilloscope. Press the “Default Setup” button and turn on your target system. You should now see a clock signal being measured on your oscilloscope (see figure 2-4).



Figure 5-4 PCI-Express Reference Clock Signal

While placing the mouse cursor on top of the clock signal shown, press the right mouse button and select “Autoscale Vertical”.

You should see a waveform similar to the one below:



Figure 5-5 PCI Express Reference Clock Signal (after Autoscale)

5.3 Measuring the Clock Period Trend Now that the scope is setup to properly display your target’s PCI Express reference clock, the next step is to setup the scope to capture sufficient data to resolve the reference clock adequately in the frequency domain. To do this you first need to change the acquisition sample rate to 4GSa/s. Since the CLB uses two 2pf capacitors to form a compliance load, a low pass filter is being applied to the reference clock with a 3db frequency of approximately 1.6 GHz. The DSO 80000 series oscilloscope supports up to 64 Million Points of acquisition memory at 4GSa/s, which is an appropriate acquisition, speed for this type of signal.

To change the acquisition speed and memory depth select the Setup->Acquisition menu pick.



Figure 5-6 Changing the Acquisition Setup

Next set the sampling rate to “manual” and adjust the rate to 4 GSa/s. Following that, set the memory depth to “manual” as well and set the depth to 12 million points. Sine(x)/x can be turned on or off as the jitter measurement you will make later will automatically turn it on.



Sin(x)/x selection is a don’t care.

Set Memory Depth to 12Mpts

Set Sample Rate to 4GSa/s

Figure 5-7 Changing the Acquisition Sample Rate and Memory Depth

Now that you have 12M points of memory you can change the horizontal time base to 300us per division to show the complete depth of the record of data you can now acquire.



Set the horizontal time base to 300us by left clicking on this box with the mouse

Figure 5-8 Changing the Acquisition Sample Rate and Memory Depth

Next you want to setup a measurement trend of the clock period. To do this you will need to invoke Ez-Jit. Ez-Jit is an optional jitter package for the DSO 80000 series oscilloscope. You invoke it by selecting Analyze->Jitter from the pull down menu.



Figure 5-9 Acquiring 3ms of Data

Next Click the Jitter Setup Wizard Button



Invoke the Jitter Wizard by pressing this button

Figure 5-10 Invoking the Jitter Wizard

The jitter wizard makes it easy and straightforward to setup a clock jitter measurement trend. Once you invoke the wizard you will be presented with a number of screens as shown below. Press the appropriate buttons as shown. You want to setup a clock period measurement and then display a measurement trend of the clock period analysis. The trend will show variations in the clock period over the entire measurement acquisition. Differences in clock period phase are manifested in this trend.

When you invoke the jitter wizard you will see the screen below. Click Next.



Click Next

Figure 5-11 Jitter Wizard Initial Dialog Screen

Click Next

Figure 5-12 Jitter Wizard Initial Settings

Next press the “Select Measurement” button and then select the timing/clock period measurement.



Select the “Clock Period” Measurement

Click Next

Figure 5-13 Jitter Wizard: Setting Up a Period Measurement

Click Next

Figure 5-14 Jitter Wizard: Setting Voltage Thresholds



Click Next

Figure 5-15 Jitter Wizard: Unselecting the Measurement Histogram Function

Now select the Measurement Trend and then click Next.

Select the Measurement Trend Check Box

Then click Next

Figure 5-16 Jitter Wizard: Selecting the Measurement Trend Function



Click Next again

Figure 5-17 Jitter Wizard: Unselecting Smoothing



Click Next again

Figure 5-18 Jitter Wizard: Unselecting Jitter Spectrum Function

Now click “Finish”

Figure 5-19 Jitter Wizard: Finishing the Setup

At this point you have correctly setup the measurement trend of the clock period. The scope will then automatically split the display into two screens. On the top you will see the original signal, on the bottom you will see the measurement trend. This may take a few minutes for the scope to calculate.



Original Clock Signal

Measurement Trend of the Clock Period

Figure 5-20 Showing the Clock and the Measurement Trend of the Clock Period Jitter

Now you need to save the clock period measurement trend into a data file (.csv format) for later analysis using the PCI Sig Clock Jitter tool. To save the data simply right click on the measurement trend waveform and select “Save Waveform” as shown below.



Figure 5-21 Saving the Clock Period Jitter Trend to a File

Then just save the waveform as a .csv file in the directory of your choice.

Select .CSV FormatInclude Scale Factors

Figure 5-22 Choosing a File Name

The scope will take a few minutes to save the data. Once the data is saved the next step is to load the saved waveform file into the Clock Jitter Measurement Tool.



5.4 Performing the Clock Phase Jitter Analysis

The PCI Express Clock Jitter measurement is performed by a simple clock jitter analysis utility provided by the PCI-SIG. This lab assumes you have the utility loaded on the PC you are using for analysis. To analyze the clock jitter of your motherboard you will need to invoke the utility and then load in the .csv file you just saved.

Figure 5-23 The PCI-Sig Clock Jitter Tool Startup Screen

The clock jitter tool will apply a filtering transfer function in the frequency domain to focus on jitter that lies between 1.5 and 22 MHz. Then, after transforming the filtered signal back into the time domain, the amount of eye closure is calculated. The PCIe 1.1 specification states that 86ps is the limit for 10^-6 BER.

Figure 5-24 Phase Jitter Test Results

Select the .csv file you want to analyze.

Click here to analyze the file

Header lines should = 40

Time Stamps are in the file


Appendix A

6 Appendix A INF_SMA_DESKEW.SET setup file details:

Start from a default setup by pressing the Default Setup key on the front panel. Then configure the following settings…

Acquisition Averaging on number of averages 16 Interpolation on

Channel 1 Scale 100.0 mV/ Offset –350mV Coupling DC Impedance 50 Ohms

Channel 3 Turn Channel On; Scale 100.0 mV/ Offset –350m V Coupling DC Impedance 50 Ohms

Time base Scale 200 ps/sec

Trigger Trigger level –173mV Slope falling

Function 2 Turn on and configure for channel 1 subtract channel 3,

Vertical scale 50 mV/ Offset 100.000 mV


Appendix A


Appendix B

7 Appendix B INF_PCIE_SMA_M2_CH13_Test1_5.set setup file details:

Start from a default setup by pressing the Default Setup key on the front panel. Then configure the following settings…

Acquisition

Memory depth manual 200000 pts

Sampling rate manual Sampling rate 20.0 GSa/s

Sin(x)/x Interpolation off

Channel 1 Scale 70.0 mV/

Channel 3 Turn channel on; Scale 70.0 mV/

Time base Scale 5 nS/

Trigger Trigger level 50.0 mV

Function 2 Turn function on, channel 1 subtract channel 3

Vertical scale 150 mV/ Offset 0.0 V

Display Set display window quantity = 2, drag Function 2 trace to lower window.


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