pcfl (1)

ModiconProcess ControlFunction LibraryUser GuideGM-PCFL-001 Rev. A

MODICON

ModiconProcess ControlFunction LibraryUser GuideGM-PCFL-001 Rev. A

December, 1992

MODICON, Inc.One High StreetNorth Andover, Massachusetts 01845

Table of Contents

Chapter 1 introduction

Introduction 2Overview 2

Advanced Calculations 2Signal Processing 3Regulatory Functions 3Differences Between PCFL and Traditional DX Modules 3

Related Documents 4Ladder Logic Requirements 4Function List 6

Chapter 2 System Architecture 9

System Architecture 10DX Architecture 10User Interface 11

Modsoft Support 11

Chapter 3 Core Library 13

Core Library 14Function Summary 14

Chapter 4 Specifications 17

Status Register Allocation 18Flag Definition for All Functions 18

OUTPUT Flag bits: 18INPUT Flags 19Using Flag bits in Logic 19

PCFL Function Block Descriptions 20

GM-PCFL-001 A Table of Contents v

Advanced Calculations 20AVER 20AVER Block Description 20AVER Application 22CALC 25CALC Block Description 25CALC Application 27EQN 29EON Block Description 29EQN Application 33

Signal Processing 36ALARM 36ALARM Block Description 36ALARM Application 39AIM (Analog Input) 41AIN Block Description 41AIN APPLICATION 44AOUT (Analog Output) 46AOUT Block Description 46AOUT Application 48DELAY 49DELAY Block Description 49DELAY Application 51LKUP 53LKUP Lookup Block Description 53LKUP Application 55INTEG (Integrator) 57INTEG Block Description 57INTEG Application 59LLAG (Lead / Lag Filter) 61LLAG Block Description 61LLAG Application 62LIMIT 64LIMIT Block Description 64LIMIT Application 65LIMV 67LIMV Block Description 67LIMV Application 69MODE 70MODE Block Description 70MODE Application 71RAMP 72Ramp Block Description 72RAMP Application 73

vi Table of Contents GM-PCFL-001 A

RMPLN (Logarithmic Ramp Generator) 76RMPLN Block Description 76RMPLN Application 78RATE 79RATE Block Description 79Rate Application 80SEL (Select) 81SEL Block Description 81SEL Application 82

Regulatory Control Block Descriptions 84ONOFF 84ONOFF Block Description 84ONOFF Application 86PID 88PID Block Description 88Option/Feature Comparison: 91PID Application 95

Customer Service & Technical Assistance 97

Appendix A Execution Times 99

Appendix B Examples 101

EQN (Equation) Example 102AGA3 Example 104

Formula Decomposition 104Ladder Development 106Ladder Implementation 106Alphabetic Operand List 109

PID Example 111Main PID Ladder Logic 112Simulated Process 113PID Parameters 114

GM-PCFL-001 A Table of Contents vii

Figures

Figure 1 Standard DX Block Nomenclature for PCFL 2Figure 2 Modsoft Programming Element List 4Figure 3 Selecting the PCFL DX entry 5Figure 4 PCFL Selected, Function List 5Figure 5 PCFL DX Block Programming Element 6Figure 6 Block and LEN Function Assignment 12Figure 7 PCFL Function Status Register 0 18Figure 8 AVERage PCFL Function Block 20Figure 9 Register 2/3 Status Bits For AVER Function 22Figure 10 AVER Data DX Zoom Screen 23Figure 11 Example of Ladder Diagram Reference Data 24Figure 12 CALC PCFL Function Block 25Figure 13 Status Register Usage CALC Function 27Figure 14 DX Zoom for Calculation 28Figure 15 CALC DX Zoom Screen Page 2 28Figure 16 CALC PCFL Function Block 29Figure 17 Register 2 Status Output 30Figure 18 Register 3 Input Status 31Figure 19 DX Zoom register display for the EQN Block 34Figure 20 Ladder Diagram of EQN Block with Example Data 34Figure 21 Input and Equation String Update screen 35Figure 22 ALARM PCFL Function Block 36Figure 23 Register 2 Status Output bits 38Figure 24 Register 3 Status Input Bits 38Figure 25 ALARM Signal and Setpoint Threshold 39Figure 26 DX Zoom Display of ALARM Block Data Example 40Figure 27 AIN PCFL Function Block 41Figure 28 Register 2 Status Output Bits 44Figure 29 Register 3 Status Input Bits 44Figure 30 Analog Input (AIN) DX Zoom Screen Example 45Figure 31 Analog Input (AIM) DX Zoom Screen Example Page 2 45Figure 32 AOUT PCFL Function Block 46Figure 33 Register 2/3 Status Bits 47Figure 34 Analog Output (AOUT) DX Zoom Display Example 48Figure 35 DELAY PCFL Function Block 49Figure 36 Register 2 Output Status Bits 50Figure 37 Register 3 Input Status Bits 51Figure 38 DX Zoom Parameter Entry / Observation Screen Example . . 51

viii Table of Contents GM-PCFL-001 A

Figure 39 Delay Queue DX Screen Page 2 52Figure 40 LKUP PCFL Function Block 53Figure 41 Register 2 Input Output Status Bits 54Figure 42 LKUP Block DX Zoom Screen Page 1 55Figure 43 LKUP Block DX Zoom Screen Page 2 56Figure 44 INTEG PCFL Function Block 57Figure 45 Typical timer Ladder implementation 58Figure 46 Register 3 Status Bits 59Figure 47 INTEG DX Zoom Screen 60Figure 48 LLAG PCFL Function Block 61Figure 49 Register 3 Status Bits 62Figure 50 LLAG DX Zoom Screen Example 63Figure 51 LIMIT PCFL Function Block 64Figure 52 Register 2 Status Bits 65Figure 53 LIMIT DX Zoom Screen Example 66Figure 54 LIMV PCFL Function Block 67Figure 55 LIMV Register 2 Status Bits 68Figure 56 LIMV DX Zoom Display Data Example 69Figure 57 MODE PCFL Function Block 70Figure 58 MODE Register 2/3 Status Bits 71Figure 59 MODE DX Zoom Display Example 71Figure 60 RAMP PCFL Function Block 72Figure 61 Ramp Register 2/3 Status Bits 73Figure 62 Example Ramp Generator 74Figure 63 Ramp DX Zoom Screen 75Figure 64 Log RAMP PCFL Function Block 76Figure 65 Log RAMP Register 2/3 Status Bits 77Figure 66 Log Ramp Setpoint Interaction 78Figure 67 RMPLN DX Zoom Display Data 78Figure 68 RATE PCFL Function Block 79Figure 69 Rate Register 2/3 Status bits 80Figure 70 RATE Block DX Zoom Display 80Figure 71 SELect PCFL Function Block 81Figure 72 Select Register 2/3 Status Bits 82Figure 73 SELect DX Zoom data Display 83Figure 74 ONOFF PCFL Function Block 84Figure 75 ON-OFF Register 2/3 Status Bits 86Figure 76 On/Off DX Zoom screen 87Figure 77 PID PCFL Function Block 88Figure 78 Simple Control Loop 89Figure 79 PID Block Diagram In Typical ISA Structure 90Figure 80 Register 2 Bit Definition 94Figure 81 Register 3 Bit definition 94

GM-PCFL-001 A Table of Contents ix

Figure 82 Register 5 Input Flags 95Figure 83 PID DX Zoom Display 96Figure 84 Flow Instrumentation 102Figure 85 qv1 and qv2 defined 105Figure 86 Timer controlled Extract of Live data table 107Figure 87 Pipe Orifice and Upstream Temperature and Pressure 107Figure 88 Pipe and Flange Beta with Provision for Manual Override ... 108Figure 89 Acoustic Ratio Calculation and Setup for qv Calc 108Figure 90 Equations for qv1 and qv2 109Figure 91 Main Logic for PID Control 111Figure 92 Simulated Process Variable under Loop Control 112Figure 93 Typical LKUP Results 112Figure 94 Simulated Process for PID Control 113

Tables

Table 1 PCFL Function Library Summary 14Table 2 AVER Register Assignment 21Table 3 CALC Register Assignments 26Table 4 Equation (EON) Register Assignments 29Table 5 ALARM Register Assignments 38Table 6 AIM Register Assignments 44Table 7 AOUT Register Assignments 47Table 8 DELAY Register Assignments 50Table 9 LKUP Register Usage 54Table 10 INTEG Register Usage 59Table 11 LLAG Register Usage 62Table 12 LIMIT Register Usage 65Table 13 LIMV Register Usage 68Table 14 MODE Register Usage 70Table 15 RAMP Register Usage 73Table 16 RMPLN Function Register Usage 77Table 17 RATE Block Register Usage 79Table 18 SEL Block Register Usage 82Table 19 ONOFF Register Usage 85Table 20 PID Register Usage 93

Table of Contents GM-PCFL-001 A

Chapter 1Introduction

a This chapter introduces you to the general functionality providedby the Modicon Process Control Function Library and an over-view of control requirements in general.

a PCFL is implemented in firmware in the Modicon PC-E984-685and PC-E984-785. The interface to the controller is provided byModicon Modsoft software. Numerous graphics are used to helpvisualize the control and setup requirements for the PCFL func-tions. Modsoft release 1.2 can not produce the graphics in thisdocument without updating specific PCFL files in the Modsoftruntime directory. The graphics in this user guide will be includedin the next release of Modsoft i.e. >1.2

GM-PCFL-001 Rev. A Chapter 1 Introduction 1

Introduction

Overview

This document describes the Process Control Function Library (PCFL). The func-tion is inherent in the 984 "E" controller family executive software, and is initiallyprovided in the PC-E984-685 and PC-E984-785 controllers. PCFL appears as asingle 3-node DX block (Figure 1) in ladder logic with the name 'PCFL.

Enable

Disable

FUNG

4XXXX

PCFL

LEN

Done

Error

Figure 1 Standard DX Block Nomenclature for PCFL

Like EMTH, this one DX can be used to reference an entire library functions.PCFL is geared toward continuous process control dealing with analog values.

Functions in PCFL are subdivided into three major categories:

a Advanced Calculations

o Signal Processing

o Regulatory Control

Advanced CalculationsAdvanced calculations are used for general mathematical purposes and are notlimited to process control applications. Calculations allow the user to create cus-tom signal processing algorithms, derive states of the controlled process, derivestatistical measures of the process, etc. Simple math routines have already beenoffered in the EMTH function block already available in slot mount controllers.

Introduction GM-PCFL-001 Rev. A Chapter 1

EMTH consists of individual math functions such as +,-,*,/ as well as transcenden-tal functions and trigonometric functions. The major addition to calculation capa-bilities included in PCFL is a textual equation calculator that allows the user towrite his own equations instead of doing math operations one by one.

Signal ProcessingSignal processing functions are used to manipulate process and derived processsignals. They can do this in a variety of ways; they linearize, filter, delay, andotherwise modify a signal. This category would include functions such as an Ana-log Input/Output, Limiters, Lead/Lag, and Ramp generators.

Regulatory FunctionsRegulatory functions perform closed loop control in a variety of applications. Typi-cally, this is a PID {Proportional Integral Derivative) negative feedback controlloop. PCFL currently supports only one PID algorithm, the same algorithm offeredby the Modicon A500 controller. It has the same general functionality of the PID2function, but uses floating point math, and represents some options differently.There is a learning curve requirement for customers making a transition to thePCFL PID aigorithm. However, most applications can still use PID2 as is. PIDwould be beneficial for those cases where PID2 is not suitable because of numeri-cal concerns such as roundoff, etc..

Differences Between PCFL and Traditional DX ModulesA very important difference between this library and most other Modicon DX mod-ules is that PCFL requires floating point mat.h PCFL uses the same floating pointlibrary as EMTH. Since ali floating point processing is done via emulation and notby an onboard 80x87 chip, these functions take a comparatively long time to ex-ecute. Users must access the speed requirements of an application on an inde-pendent basis. However, speed becomes a non-issue for traditional process con-trol applications where solution times are measured in seconds, not milliseconds.

Modsoft 1.2 includes basic panel programming support for PCFL. There will beadditional support for expanded PCFL functions (such as the Equation Calculator)in subsequent Modsoft releases.

GM-PCFL-001 Rev. A Chapter 1 Introduction

Related Documents

Modicon 984 Programmable Controller Systems ManualGM-0984-SYS

Modicon Modsoft Programmer User Manual (Rev. C for release 1.2)GM-MSFT-001

Ladder Logic Requirements

Using the Modsoft panel software in a program development mode you can selectthe DX Element Pulldown selection as in Figure 2

Sag. 5 #1

lUtility 1PLC Ops lElement ^Command IRef•Fl -—F2 r—Elements [Ladder Diagram

^Relays»T im/Cnt>Ma.th

DXables

MacroSpecials

Figure 2 Modsoft Programming Element List

With the DX selected you are given a display list of all available DX built-ins ofwhich you select PCFL.


-tUtility IPLC Ops iElement ICommand iRei INetF4- Ladder Diagram 6- /

|Seg. 5 #1

R->T

ANDREADCKSMAD1B

SU1B CMU16

DV1B

TESTITOFFT 01T->R

ORVRITT->T

CMPR-EH12

PCFO"~5CKM

SE^SEMTHFINMBITBLKT

POUTCOMPLABMSTRSRCHXORJSRTBLKSTATBROTRET

\

//

I

Figure 3 Selecting the PCFL DX entry

On the initial PCFL selection, the available PCFL Library functions are posted tothe display as a select list illustrated in .

iUliltty 1PLC Ops lElement iCorattianrf iRef -INstwork IF2 F3 F4- Ladder Diagram 6

Seg. 1 #3 /8

AINAOUTALARMAVERCALCDELAYEQN

INTEGLLAGLIMITLIMVLKUPMODERAMP

RMPLNRATESELONOFFPID

(

Figure 4 PCFL Selected, Function List

When you have determined the function you want to program the DX Block sym-bol is displayed.

GM-PCFL-001 Rev. A Chapter! Introduction 5

iUt i l i ty iPLC Ops lElement ICommand IRef INFl F2 F3 F4- Ladder DiagramSeg. 5 #1

lx ' ' i~ Done

r Error40B31IPCFL#8611-1

Figure 5 PCFL DX Block Programming Element

The PCFL block accepts one input (Top = Enable/Disable) and produces one oftwo outputs

Top = DONEBottom = ERROR.

The body of the function block will have:

FUNG The name of PCFL library function to use is displayed inthe top node. In the above example CALC was chosen.

4XXXX First holding register for parameters for PCFL.

LEN Length of register table to process for PCFL

All parameters used by a given function must be transferred via the defined 4xxxxregister and it's associated LENgth of holding registers.

Modsoft support provides mnemonics for each function in PCFL. Therefore, theuser may enter a function name instead of remembering a specific function num-ber. Without Modsoft, the function code must be entered.

Function List

The name of each function is given below as it appears in Modsoft.


Advanced Calculations:AVE AverageCALC Preset calculationsEQN Equation calculator

Signal ProcessingAIM Analog InputALARM Alarm HandlingAOUT Analog OutputDELAY Delay QueueLKUP Lookup TableINTEG IntegratorLLAG Lead/Lag FilterLIMIT LimitLIMV Velocity LimiterMODE Auto/Manual Transfer StationRAMP Ramp GeneratorRMPLN Logarithmic Ramp GeneratorRATE Rate of Change (i.e. Derivative)SEL High/Low/Ave. Selector

Regulatory ControlONOFF On/Off ControllerPID PID Controller

You can have as many as 20 Blocks in a network.

GM-PCFL-001 Rev. A Chapter 1 Introduction

Chapter 2System Architecture

a This Chapter defines how PCFL functions are handled as theyare implemented in Ladder Logic.

GM-pcFL-001 Rev. A chaPier2 System Architecture 9

System Architecture

DX Architecture

The DX architecture of the PCFL function block is rather straightforward. ThePCFL library functions are solved immediately when encountered in ladder logic.The only difference in how functions are executed lies in the way functions behavewith respect to time dependencies. It is possible to impact scan time therefore us-ing timers to enable the function to be properly scheduled is recommended

There are four layers that are traversed for each function once the DX is sched-uled to solve in the E984:

a Function Dispatcher

a Timer Calculation (for time-dependent functions only)

o The Function Itself

a Floating point functions (called from each PCFL function when necessary)

If more than 16 bits are required, the status output register is always first registerand the status input register is second. The PID function, has two status outputand two status input registers.

To determine if a function is ready to solve, the timing layer makes a comparisonbetween the elapsed time and the target solution interval If it is not time to solve,the DX updates the timing information and returns, reducing the function over-head. If it is time to solve, the function itself is executed.

Note it is important to put a timer in front of PCFL blocks to reduceload on system if solve time is large. Timing is accomplished by using984 10 ms clock written into second register every scan. Accumulatedtime since the last scan is stored as an unsigned long in ms. Using thisscheme you can skip solves unless required in you process.

10 System Architecture GM-PCFL-OOI Rev A chapter 2

An example of a Time Dependent function is INTEG, the stand-alone integrator. Ifthe solution interval is set at 1.500 seconds, each time the PLC scans the INTEGDX, the timing layer will add the efapsed time to the time since last solve until thisvalue is greater or equal to the solution interval. At that time the INTEG functionwill solve, using the actual elapsed time.

Note the target solution interval must be equalled or exceeded beforethe function will solve. Therefore, a setting of 1000 mSec will forcesolves at the first scan that produced a value at or above 1000 mSec.For example, the integrator starting at 0.0 with an input of 1.0 and witha solution interval of 1000 mSec would be expected to produce an out-put of 1.0. In practice, the controller will solve at the actual elapsedtime which may be 1020 mSec causing the output to read 1.02.

User Interface

Mod soft Support

Most of the PCFL User Interface is handled by Modsoft via the DX-Zoom feature.There are several new features introduced in Modsoft 1.2 to support PCFL:

a Function Recognition

a Length Parameter Fill-in

o Equation support (Not available in Modsoft 1.2. Will be in next revision )

When Modsoft recognizes a PCFL DX, the top node is linked to a pop-up windowto allow the transparent selection of the PCFL function. This mnemonic translatesinto a function number that the DX will use. When a programming panel is usedwithout this support, only a number will be visible. The pop-up menu will appearwhenever a new PCFL block is entered or when any key is pressed while the cur-sor is over the top node.

The length feature is related to the above enhancement. Once the top node of thefunction has been chosen, Modsoft will choose the minimum number of registersnecessary to use that function. Once the middle node has been programmed (orcursor moved passed it), this length is automatically entered in the bottom node.

GM-pcFL-001 Rev. A chapter 2 System Architecture 11

Program panels without this feature would require the user to allocate at least theminimum number of registers necessary for the block to solve. The only exceptionis the Equation calculator which is currently initialized with the maximum numberof registers that can be used by the function.

To illustrate the above two enhancements, if you want to use the Analog Inputfunction, you need not know that function number is #31. AIN will appear as achoice in a pop-up window during configuration and will be displayed when view-ing Ladder Logic. The appropriate function number will be passed to the PCFLDX through a look-up table, as well as the length parameter that is to be used inthe bottom node.

iUt i l i ty IPLC Ops lElement ICommand IRef INrFl F2 F3 F4- Ladder Diagram'Seg. 1 #8 /8

TAIN

40061• |PCFL#8014'

Figure 6 Block and LEN Function Assignment

There is an offline utility for programming the EQN Block but it is not available inModsoft release 1.2. The function of the utility is implemented in the next Modsoftrevision, and will not be required separately after that release. This Utility allowsyou to input a string (the desired equation) and the 4x register for the EQN Block.Using the utility the EON Block can be programmed over Modicon Modbus PiusCommunications networks (standard Modbus can not be used). You have the op-tion to save the EQN to a file or to read an EQN from a file. The utility calculatesthe minimum LEN (registers) required for the bottom node of the DX Block and in-forms you what that number is.

If you have a requirement for this utility contact Modicon Customer Service

Note The notation you will see in the block descriptions as FLT32means a 32 bit Floating Point values.

12 System Architecture GM-PCFL-001 Rev. A Chapter 2

Chapter 3Core Library

This Chapter gives a brief description of the existing PCFL Li-brary functions. This Library is dynamic and will grow as otherprocess related requirements are defined.

GM-PCFL-001 Rev. A Chapter 3 Core Library 13

Core Library

Function Summary

This Chapter gives a list of Process Control functions that have been programmedfor PCFL. An asterisk after the function name denotes that the function is time de-pendent. The translated function code is also listed followed by the number of reg-isters needed by the module and a short description. For further information seethe full specification in Chapter 4.

Table 1 PCFL Function Library Summary

Function Code # Registers Description

Advanced CalculationsAVE 01 24

CALC 02

EQN 03

14

64 Max.

Signal ProcessingALARM 30 16

AIN 31 14

AOLJT 32

DELAY' 33 32

14 Core Library

Average of set of weighted inputs (up to 4)

Calculation block for pre-set programmedformulas.

Postfix notation calculator for userprogrammed equations. Includes four internalvariables which can set up from other sectionsof logic. Length depends on the userequation, but limited to 64 registers,(can be up to 255 with EQN utility)

Centra! alarm block LL, L, H, HHavaiiable forDeviation, Process Var.

Interface for input modules. Converts input toscaled engineering units, including a provisionfor process SORT.

Interface for calculated Signals with outputmodules by converting an output Signal toa value between 0 and 4095.

Pure delay for use with time-delaycompensation

GM-PCFL-001 Rev. A Chapter 3

Table 1 PCFL Function Code (Cont)Function Code # Registers Description

LKUP 34

INTEG* 35

LLAG* 36

LIMIT 37

LIMV* 38

MODE 39

RAMP' 41

RMPLN* 42

RATE* 43

SELECT 44

39

16

20

10

14

14

16

14

14

Regulatory Control:ONOFF* 73 14

PID* 75 44

A look-up table for up to 8 points

Integrate an input at a given interval

First order lead/lag filter

Limiter for process var., LL, L, H, HH

Velocity limiter for process var. changes,L, H

Allow user to put an input in either manual orauto mode

Ramp generator, ramps to a given set point ata constant rate, used for set point filtering

Logarithmic ramp generator, ramps to a givenset point, approximately 2/3 closer to the setpoint for each time constant, used for set pointfiltering

Derivative over specified time period, for ratecalculations

Hgh/Low/Ave. selector

On/Off two position deadband User canspecify "On" and "Off" values

ISA Non interacting PID Features includeAuto/Manual Bumpless Transfer, outputlimiting, Anli-reset-windup, derivative filtering,summing junction, halt/manual/auto operationmodes

GM-PCFL-001 Rev. A Chapter 3 Core Library 15

Chapter 4Specifications

o This Chapter describes each entry in the Process Control Func-tion Library. The general arrangement of the description is:

Block graphic with assigned register length.Block Description and formula.Table of register usage.Application via Modsoft DX Zoom screens.

GM-PCFl-001 Rev A Chapter 4 SpCClfiCatJOHS 17

Status Register Allocation

The status register contains standard output flag bits and function specific inputand output flag bits. Output flags begin at the low bit, inputs at the high bit. Thestatus register(s) follow the Input register which is the first register in thetable. Functions exist in which there are more than 16 flag bits, in these casestwo registers are used. The status output register is always the first register andstatus input Is second. A further exception is the PID function which will be dis-cussed later.

Input Flags *• •* Output Flags

bit 1 2 3 4 5 6 7 8 9 10 11 12 131415 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB LSB

12-16 fixed for all functions

9-11 used for time dependent functions only

Figure 7 PCFL Function Status Register 0

Flag Definition for All Functions

OUTPUT Flag bits:00000001 or Hex 0001 bit 16

00000010 or Hex 0002 bit 15

00000100 or Hex 0004 bit 1400001000 or Hex 0008 bit 13

00010000 or Hex 0010 bit 12

Means an Error has occurred, passes poweron DX Block Error outputMeans the size of the allocated register tableis too small, return DX Block Error,ReservedUnknown PCFL function, return DX BlockErrorMeans a Math error, invalid floating point inputor output return DX Block Error.

18 Specifications GM-PCFL-001 Rev. A Chapter 4

For Time Dependent Functions

00100000 or Hex 0020 bit 11

01000000 or Hex 0040 bit 10

10000000 or Hex 0080 bit 9

Illegal solution intervalReservedInitialization working

INPUT Flags00010000 or Hex 1000 bit 400100000 or Hex 2000 bit 3

01000000 or Hex 4000 bit 210000000 or Hex 8000 bit 1

ReservedTimer OverrideReservedFirst Scan: Initialize, 0=do initialization,1 =complete or in progress

For Time Dependent Functions

00001111 or Hex OFOO bits 5,6,7and8 Function Specific (outputs/inputs)

Note Your Ladder Logic should have a timer in front of PCFL func-tion blocks whose solve time can create a load on system i.e., the solu-tion interval is large. Timing is controlled by using 984 10 ms clockwritten into second register every scan. Accumulated time since thelast scan is stored as an unsigned long in ms.

Non Time Dependent functions:

00001111 11100000 or Hex OFEO bits 5,6,7,8,9,10 and 11 Function Specific

(outputs/inputs)

Using Flag bits in LogicTo use Output flags in logic you may detect them with a SENS DX Block. Con-versely, to set an Input flag from Ladder logic, you may use an MBIT DX Block. Asan alternative you could read or write the entire register to contacts or coils.

GU-PCFL-001 Rev. A Chapter 4 Specifications 19

PCFL Function Block Descriptions

Advanced Calculations

AVERWhen this function is selected from the PCFL Library, the DX block illustrated inFigure 8 is displayed. The block name is posted in the top node and the cursor ison the middle node (?????) where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

Enable

disableDone

Error

Figure 8 AVERage PCFL Function Block

AVER Block DescriptionThis function can calculate up to four weighted inputs using the formula:

O k + W1 X1 + W2 X2 + W3 X3 + W4 X4Result = .

1 + W1 + W2 + W3 + W4Where W= Weight

X = Inputk = Constant

When the calculation is complete the block Done node passes power.


Note Weight is only used when its input is enabled. The 1 in the de-nominator is only used when the constant is enabled.

Table 2 AVER Register Assignment

Register Description

Reg 0,1 Reserved2 Status Output3 Status Input

Input Flags where 1 = activated 0 = deactivatedBit 9 = ConstantBit 8 = Input 1Bit 7 = Input 2Bit 6 = Input 3Bit 5= Input 4

4,5 Input 16,7 Input 28,9 Input 310,11 Input412,13 Constant14,15 Weight 116,17 Weight 218,19 Weights20,21 Weight 4

Reg 22,23 Result

GM-PCFL-001 Rev. A Chapter 4 Specifications 21

Status Input*- Bit 5 Input 4 ActiveBit 6 Input 3 ActiveBit? Input 2 ActiveBit8 Input 1 ActiveBit 9 Activate Constant

bit 1 2 34 5 6 7 8 9 10111213141516

Status Reg0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB LSB

•* Status Output

Bit 11 Result Positive / Negative (0/1)Bit 10 No inputs activated, return

DX Block Error

Figure 9 Register 2/3 Status Bits For AVER Function

AVER Application

If the value to be calculated is variable it should be an input with no constant. Aweight of 0 is the equivalent of deselecting the input.

Assuming you have put the register value 40600 (can be whatever you require) inthe middle node of the function block and you want to average input 1 to 4, put theladder diagram cursor on the AVER block, select the DX Zoom and make the en-tries as illustrated in the DX Zoom screens illustrated while in the Online mode,You move the Zoom screen cursor using the up and down arrow keys. The Resultis the solution to the values entered. If you return to the ladder diagram you cansee the power flow at the block done (or error) output.


Util ity iPLC Ops Hex

INPUT FLAGS, 1=ACTIVATEDCONSTANT:INPUT 1:INPUT 2:INPUT 3:INPUT 4:

INPUT, CONSTANT:

INPUTS:1: 48694 FLT32 = 2.2: 49606 FLT32 = 33: 43668 FLT32 = 44: 4S610 FLT32 = 5

AVERAGE:

ERROR, 1=YES 9=NO:

>ec Bin Page

AVERAGE

, 3=DEACTIVATED:40603 EIT0940603 BITB849603 BIT6749603 BIT0640603 BIT05

40612 FLT32

VEIGHTS:1: 406142: 406163: 406184: 40628

40622 FLT32

40692 BIT16

Quit

PAGE 1Z 2

- 1

- 1

= 1

= 1.

FLT32 - 1.FLT32 - 1.FLT32 = 1.FLT32 = 1.

= 3.

- 6

lUtility IPLC OpsFi - F2

Hex Dec Bin PageF4 Reference Editor

AVERAGE

OUTPUTS FLAGS:MATH ERROR:NO INPUTS ACTIVATED:RESULT NEGATIVE:

Quit3-DEBUG-F3-1-

PAGE 2 /

Figure 10 AVER Data DX Zoom Screen

When the DX block is displayed, you can also observe the status register bits di-rectly on the ladder diagram display using Modicon Modsoft functionality. If youselect the Reference Data editor from the Utility Menu options you can enter thereference, offset from the middle node (which is the table starting register refer-ence) for either status Output or Input register. Continuing with the referencescreen choose the format option for binary display. The binary values in the statusregister will display (See Figure 11) in the reference data portion of the display andwhen you put the cursor over the middle node reference of the DX block, the reg-ister contents are displayed in the upper right area of the logic display.

The options described in this paragraph are common to all PCFL DX Func-tions.


Seg. 1 #8 /8

AVER

48680•|PCFL

F4- Ladder Diagram -8-DEaUB-F9-l-

lio Symbol/Comment available-Reference Data

Figure 11 Example of Ladder Diagram Reference Data


CALCWhen this function is selected from the PCFL Library, the DX block illustrated inFigure 12 is displayed. The block name is posted in the top node and the cursor ison the middle node (?????) where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

Enable

disableDone

Error

Figure 12 CALC PCFL Function Block

CALC Block DescriptionCalculation block for various math forms with up to 4 inputs. Grouped in two forms:miscellaneous algebraic and engineering. The CALC block is meant to relieve someof the burden of common calculations. Most equations should be solvable with acombination of 2 or 3 math or CALC blocks. This DX Block Currently supports 13calculation structures and returns power flow to the top node when finished.

You select the desired formula by setting selected bits #7->10 which have a rangeof 0 to 15 binary.

Miscellaneous algebraic formula

BINARY DEC FORMULA

0001001000110100010101100111

12

34

5

67

AB + CDA B - C DA B / C DA / B C DA B C / DA B C DA + B + C + D

GM-PCFL-001 Rav.AChapter4 Specifications 25

Engineering formula

1000 8 A B ( C - D )

1001 9 A [ ( B / C ) A D ]

1010 10 ALN(B /C )

1011 11 [ (A-B) - (C-D) ] /L N [ ( A - B ) / ( C - D ) ]

1100 12 A / B E X P ( - C / D )

1101 13 ( A - B ) / ( C - D )

Formula:

a Output = f( A, B, C, D } Where A = registers 4,5

B = registers 6,7C = registers 8,9

D = registers 10,11

Table 3 CALC Register Assignments

Register

Reg

Reg

0,12

34,56,7

8,910,1112,13

Description

ReservedStatus OutputStatus InputInput aInput bInput cInput dOutput


Input Flags •»• •* Output Flagsbit 1 2 34 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB LSB

Bit 11 Bad input code chosen, returns DXBlock Error

Bit 5,6 Reserved for futureBits 7,8,9,10 Formula select code 0 through 15 (binary).

0 0 0 1 = Formula 1 etc.

Figure 13 Status Register Usage CALC Function

CALC ApplicationYou can test and observe results of your Selected DX PCFL function block, by us-ing the Modsoft DX Zoom feature from the ladder diagram menu.

Assuming you have put the register value 40600 (can be whatever you like) in themiddle node of the function block and you want to apply formula 1, put the ladderdiagram cursor on the CALC block, select the DX Zoom and make the entries asillustrated in the DX Zoom screen. The Output is the solution to the Equation se-lected. You can see the block power flow by returning to the Ladder diagram.

GM-PCFL-001 Rev A Chapter 4 Specifications 27

Dec Bin Page-F4 Reference Editor

CALCULATION

Quit-F7

lUtility iPLC Ops HexF1 F 2 F 3—

INPUTS:FORMULA CODE:VARIABLE A:VARIABLE B:VARIABLE C:VARIABLE D:

SEE NEXT PAGE FOR FORMULA SELECTION CODES

OUTPUT: 40810 FLT32 = 14.75

-F6-DEBUG-F3-1-PAGE 1 /

48861 07:19 - 1FLT32 - 2.FLT32 = 3.FLT32 = 2.5FLT32 - 3.5

DEC

OUTPUT FLAGS:MATH ERROR:BAD FORMULA CODE:

ERROR, 1=YES 0=NO:

40001 BIT12 = 040001 BIT11 = 0

40001 BIT16 - 0

Figure 14 DX Zoom for Calculation

Page 2 of the DX Zoom screen (Use the PgDn key) is a summary of availableequations.

iUti I ityrFl

VALID

1 =2 -3 =4 -5 -6 -7 =8 =9 -10 =11 ='12 =13 =

iPLL Ups Hex Uec am Kage guit-F2 F3 F4 Reference Editor F7 F8-OEBUG-F9-1-

CALCULATION PAGE 2 /

FORMULA SELECTIONS ARE:

A B + C DA B - C DA B / C DA / B C DA B C / DA B C DA + B + C + DA B ( C - D )A [( B / C ) ' D]A LN ( B / C )[( A - B ) - ( C - D )] / LN [( A - B ) / ( C - D )]A / B EXP ( - C / D )( A - B ) / ( C - 0 )

Figure 15 CALC DX Zoom Screen Page 2


EQNWhen this function is selected from the PCFL Library, the DX block illustrated inFigure 16 is displayed. The block name is posted in the top node and the cursor ison the middle node (?????} where you must assign the table starling register ref-erence number. When you complete the middle node assignment the Initial num-ber of registers assigned to this function is automatically placed in the bottom nodefor you. If you do not make the entry and press the return key the register total isstill displayed but no power can pass until the block is fully configured.

Enable

disableDone

Error

Figure 16 CALC PCFL Function Block

Table 4 Equation (EQN) Register Assignments

Register

Reg 0,1234,56,78,910,1112,131415-64

Description

ReservedStatus Output registerStatus Input registerInput AInput BInput CInput DOutputFirst formula codeOther formula codes

EQN Block DescriptionEQN is a formatted Equation Calculator block for user defined equations. Thisfunction complements the CALC block by allowing you to input an equation withfloating point and integer inputs as well as operators (similar to those available inMath Library). It is primarily used for equations that cannot fit into the CALC for-mat, and have 4 or less variables.

GM-PCFL-001 Rev. AChapter4 Specifications 29

The calculation is performed on registers arranged for EQN. A Selection Codespecifies whether there is an input to push on the stack or whether an operationwill be performed on the stack. Registers 12,13 are reserved for the FLT32 Output,while Registers 4-11 are reserved for the four FLT32 variable inputs.

Inputs may be either real or signed integers. For unrecognized codes, floatingpoint is assumed. If the input code is zero, the operator code is used.

Passes power to the DX Block Done output when finished.

Standard

Outputs

bit 1 2 3 4 5 6 7 8 9 10 11 12 131415 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Output Status

MSB LSBBit 12 Math Error

Bit 11 Input out of range set block error

Bit 10 Reserved

Bit 9 Bad Operator select code set block error

Bits 3-8 Function code of the last error logged(corresponds to operator code)

Bit 2 Stack Error set block error

Figure 17 Register 2 Status Output

a Input codes:

An Input Register (for Input or Operator Code Selection) is needed to format eachentry to the stack. The structure of this register is given below. The Input Selec-tion Code is configured to accept either a 32 bit floating point or 16 bit integer In-put, and has been extended to recognize Variables A, B, C, and D in FLT32 form.If the Input Selection Code is not recognized it will default to FLT32.

30 Specifications GM-PCFL-001 Rev A Chapter 4

Expert If a formula is entered with an integer place holder, you canset up logic to update a variable that is not explicitly an A,B,C or D in-put

An example of the above note, good for integers or floating point, is to programSORT (x), where (x) is an integer:

Program the formula SQRT(1) by setting4x+14 to 0300H Get integer4x+15to1 Integer4x+16to0018H SORT

The above allows you to set up a register transfer to make the integer behave asa variable! The result of the operation is still in 32 bit floating point.

bit 1 2 3 4 5 6 7 8 9 10 11 12 131415 16

Input Status0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB LSB

Figure 18 Register 3 Input Status

Input Status Register

bit #1 Deg/Rad option for TRIG

The following bits are associated with the reference that defines the formula andare not part of the Input Status.

bits #5-8 Input Selection Code5678

0001 OlOOhex FI132 input0011 OSOOhex Int16 input, signed10XX 0800-0900-OAOO-OBOOhex Variables A, B, C, D

bits #9-10 Operator Code Extension

GM-PCFL-001 Rev. A Chapter 4 SpBClf iCatJOHS 31

bits #11-15 Operator Code Selection1213141516 (decimal) Function0 0 0 0 0 0 NOP N o Operation0 0 0 0 1 1 ABS absolute0 0 0 1 0 2 ADD addition0 0 0 1 1 3 DIV division0 0 1 0 0 4 EXP exponent0 0 1 0 1 5 Reserved0 0 1 1 0 6 Reserved0 0 1 1 1 7 L N Natural Logarithm0 1 0 0 0 8 LOG logarithmic0 1 0 0 1 9 MULT multiply0 1 0 1 0 1 0 NEG negate0 1 0 1 1 1 1 POW power0 1 1 0 0 1 2 SORT square root0 1 1 0 1 1 3 SUB subtract0 1 1 1 0 1 4 SIN sine0 1 1 1 1 1 5 COS cosine1 0 0 0 0 1 6 TAN tangent1 0 0 0 1 1 7 ARCSIN

1 0 0 1 0 1 8 ARCCOS1 0 0 1 1 19 ARCTAN

Note The operator code NOP yields a No Operation and can be usedas a placeholder if programmed manually. However, if a NOP is thefirst formula code it has a different meaning. In this case it means thatthe EQN has not been programmed completely, or not programmed atall. Modsoft will flag an error to indicate this condition. When you finishprogramming the equation, change the NOP to the correct 1st formulacode.

O Formula:

Interpreted formula based on EQN formatted inputs. Calculator Interpreter sup-plies EQN structure.

32 Specifications GU-PCFL-001 Rev. A Chapter 4

EON ApplicationFor Example for Deg C to Deg F temperature conversion:

"A * (9 / 5) + 32"Translates into the following register use:

Register(s) Contents

0.1 Reserved2 Status Output Register3 Status Input Register

4,5 Variable A -> DegC = 25 set up by ladder logic implementation6,7 Variable B8,9 Variable C10,11 Variable D12,13 Output, Deg F Determined by CALC_EQN14 Input Code (0x0800) - VAR A, Deg C15 input Code (0x0300) - INT1616 917 Input Code (0x0300) - INT1618 519 Input Operator Code (0x0006) - DIV20 Input Operator Code (0x0012) - MULT21 Input Code (0x0300} - INT1622 3223 Input Operator Code (0x0004) - ADD

Using the DX Zoom and Ladder Diagram Reference data edit capability of Modsoftas illustrated (Figure 19) the example data can be entered and the equation issolved.


l U t i l i t y iPLC

INPUTS:TRIG UNITS:VARIABLE A:

VARIABLE B:VARIABLE C:VARIABLE D:

Hex Dec Bin Page-F4 Reference Editor

EQUATION

Quit-F8-DEBUG-F9-1-

PAGE I/ 2

B=DEGPEES, 1-RADIANS 406634060440606

25.0.0.

BITB5FLT32FLT32FLT32FLT32 = 0.

STRING ENTRY FDR EQUATION IS NOT VET SUPPORTEDFORMULA CODES BEGIN AT REGISTER OFFSET 4X •+• 14PLEASE CONSULT PCFL DOCUMENTATION FOR PROGRAMMING

40610

OUTPUT:OUTPUT FLAGS:

MATH ERROR:INPUT OUT OF BOUNDED RANGE:EQUATION NOT PROGRAMMED:BAD OPERATOR SELECTION CODE:FUNCTION CODE OF LAST ERROR:STACK ERROR:

ERROR, 1=YES 0-NO:

40612 FLT32 = 77

48602 BIT12 = 040602 BIT11 - 040602 BIT10 = 040602 BIT09 = 040602 84:08 = 040602 BIT01 = 040602 BIT16 - 0

DEC

Figure 19 DX Zoom register display for the EQN Block

A more detailed example is found in Appendix A.

lUt i l i ty iPLC Ops iElement ICommand iRef INetuiork iZoom Quitrfl F2 F3 F4- Ladder Diagram 6 F7 FB-DEBUG-F9-1-Seg. 1 #8 /3 40600 0

h-M—i—00803 EQN

I

| PCFL#0064'

Mo Symbol/Comment avai lable-

4061440615406164061740618• Format iDecimal

8380 Hex8380 Hex8089 Hex8300 Hex8005 Hex

Reference Data4061946620406214062240623

8003 Hex0012 Hex0308 Hex32 Dec4 Dec

Read from PLC Range : 1

Figure 20 Ladder Diagram of EQN Block with Example Data

34 Specifications GM-PCFL-OO! Rev. A Chapter 4

If you have the Modsoft 1.2 PCFL update disk or Modsoft 2.0, you will see theData represented in Figure 21.

U t i l ity iPLC Ops Hexr . i-ir i - - - -- - r 4

Dec Bin Page

EQUATION

Quit

PAGE 2 /

FUNCTION CODES, BITS 12-16:0 NOP, NO OPERATION 10123456769INPUT

ABSADDDIVEXPRESERVEDRESERVEDLNLOGMULTSELECTIONaiae HEX0390 HEX0B00 HEX0900 HEX0A00 HEX0B90 HEX

111213141516171819

CODES, BITS 5-6:FLOAT, 32 BITINTEGER, 16 BIT,VARIABLE AVARIABLE BVARIABLE CVARIABLE D

NEGROWSQRTSUBSINCOSTANARCSINARCCOSARCTAN

SIGNED

Figure 21 Input and Equation String Update screen

You can enter the formula in Post Fix notation similar to a scientific calculator.


Signal Processing

ALARMWhen this function is selected from the PCFL Library, the DX block illustrated inFigure 22 is displayed. The block name is posted in the top node and the cursor ison the middle node (?????} where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

Enable

disableDone

Error

Figure 22 ALARM PCFL Function Block

ALARM Block DescriptionThis is a central block for alarm handling. You can set switches for a given input(i.e. process variable): H, L, HH, LL. Your default operating mode is: NORMAL,which operates directly on input. You may choose to base an alarm on max DEVI-ATION allowed which operates as a function of change between the current inputand the last input. Normal mode overrides other selections.

In conjunction with these choices, you can specify whether to use just the H/L orboth H/L, HH/LL options, and/or use deadband around these limits. When in devi-ation mode, the deadband option will not be recognized, so effectively, db=0. Aflag is set when the input or deviation equals or crosses the corresponding limit.

Note If the deadband option is used, the given LL, L, H, HH limitswill be adjusted internally for crossed limit checking and hysteresis.


When enabled, the Deadband is incorporated into the HH/H/L7LL limits. These cal-culated limits will be inclusive with the more extreme range. For example, if the in-put was previously in the high range and then hits the calculated H limit, the outputwill remain at HIGH and will not transition! In the same way points at the calcu-lated HH, L, and LL positions will return HH, L, and LL flags respectively, regard-less of their previous state.


Table 5 ALARM Register Assignments


Reg 0,1 Input register2 Status Output register3 Status Input register4,5 High, High6,7 High8,9 Low10,11 Low, Low12,13 deadband

Reg 14,15 last input

bit 1 2 34 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6

Output Status0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB LSB

Figure 23 Register 2 Status Output bits

bit #11 Invalid limits (i.e. LL= > L= > H = > HH), return DX Block Errorbit #10 HIGH HIGH: X>=HH (If HH/LL Option}bit #9 HIGH: X >= H (or H < = x < HH if HH/LL option)bit #8 LOW: X < = L (or LL < x < = L if HH/LL option)bit #7 LOW LOW: X < = LL (If HH/LL Option)bit #6 If deviation option is chosen with deadband, default to deviation

without deadband, combination not allowedbit #5 DB set to a negative #, return DX Block Error

bit 1 2 3 4 5 6 7 8 9 10 11 12 131415 16

Input Status0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB LSB

Figure 24 Register 3 Status Input Bits

bit #5 Normal/Deviation alarm (0/1)bit #6 Both H/L and HH/LLbit #7 Enable/Disable deadband (1/0)


ALARM ApplicationEach of the four possible setpoints can bracketed by a zone called a deadband.The deadband is the setpoint + and - the deadband value. Increasing valueschange at the higher band limit and decreasing values at the lower.

HH deadband

LL deadband

Time

Figure 25 ALARM Signal and Setpoint Threshold

You can use the DX Zoom feature while in Online Debug to enter data in theALARM function registers and verify the operation by changing the variable data inthe input register while observing the changes in the output status register Alarmcrossover points. For example the conditions Illustrated in Figure 26 illustrate ahigh and low alarm setting and a defined deadband. The input in 40600 a value of4 turns on the low alarm bit (8) in output status register 40602.


llJtM ity IPLC Ops Hex

INPUT FLAGS:DEVIATION MODE,LIMITS ENABLED,DEAOBAND AROUND

INPUTS:INPUT, X:DEADBAND:

ALARM SETTINGS:HH: 4B664HIGH: 46666LOW: 46668LL: 46610

OTHER OUTPUT FLAGS:MATH ERROR:INVALID LIMITSDEVIATION MODE

Dec Bin Page

ALARM

1-YES:B=H/L, 1-HH/LL:LIMITS, 1=YES:

406034060340603

4069949612

F7~r t

BITB5BIT6SBIT67

FLT32FLT32

Quit

PAGE 1 /

- 6= 6- 1

= 4.= 1.

OUTPUTS :FLT32 = B,FLT32 - IB.FLT32 - 5.FLT32 - 6.

HH <= H <= L <- LL:WITH DEADBAND:

DEADBAND LESS THAN ZERO:ERROR, 1=YES 6-NO:

40602406024068240692

4069240692406924669246602

BIT19BIT69BITB3BIT67

BIT 12BIT11BITB6BITB5BIT1S

= B= B= 1= B

= B= B= B- a- a

Figure 26 DX Zoom Display of ALARM Block Data Example


AIN (Analog Input)When this function is selected from the PCFL Library, the DX block illustrated inFigure 27 is displayed. The block name is posted in the top node and the cursor ison the middle node (?????) where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

Enable

disable

Done

Error

Figure 27 AIN PCFL Function Block

PCFL AIN Function Block Register Usage

Range Choices

bits5678 Resolut

0001 0 1/4096

0010 1 1/4096

0011 2 1/8192

0100 3 1/60000101 4 1/7500

0110 5 1/100CX

0111 6 1/150CX

iNormai Range1-4095

4096-8191

1-8191

1-5999

1-7499

1-9999

1-14999

Under000040950000

COOO hex

COOO hex

COOO hex

COOO hex

Over

4096

8192

8192

8000 hex

8000 hex8000 hex8000 hex

AIN Block DescriptionAIN interfaces with 984 Input modules such as the B873-001, B873-002,B875-001, B875-011, B875-101 and B875/7-111. The function scales the binaryinput produced by the module to an engineering value to be used in subsequentcalculations. Over/Under values are handled differently as explained later. All in-valid outputs not consistent with their selected range are flagged as errors.

You have the option of specifying a manual value in engineering units to be substi-tuted for the calculated output. The manual value must be within the limits set bythe high and low engineering units to take affect. You also have the option of tak-

GU-PCFL-001 Rev. A Chapter 4 Specifications 41

ing the process square root of the input to linearize the signal before scaling. Thisoption is useful when dealing with non-linear transducers.

Note The process SORT will encompass the entire normal range notjust SQRT(4095) as in the EMTH library.

Most analog modules report outputs in the 0->4096 range. With 0 as the underrange value and 4096 as the over range value. However, the B875/7-111 offerssome extra ranges:

4096: Normal 4096: Elevated0 ->4096 4096 -> 8192

6000: Offset 7500: UniPolar 15000: BiPolar0 -> 6000 0 -> 7500 0 -> 15000

10000: Scaled decimal of above0 -> 10000

and the B873/5-011 offers:

4096: Normal 8192: Normal0 ->4096 0 ->8192

D Over/Under Values:

Over and Under values are handled in various ways depending on which modeand output range is selected. For the full decimal ranges, the extended range be-haves differently as well. In either case an error is returned if the input is outsidethe accepted range.

In MANUAL mode, a flag is set based on the engineering value that is to be usedas the output. If the Manual value is outside the specified Hi/Lo engineeringrange, the output will be clamped to the appropriate value. This behavior is con-sistent for all range selections. If the extended range has been enabled, it will notbe used to modify the Hi/Lo range.

In AUTO mode, a flag is set based on either the actual binary input {i.e. for Nor-mal or Elevated ranges) or the range bits (i.e. Extended ranges of Full resolutionand Decimal). When extended ranges are used for the full resolution options


(6000, 7500, 10000, 15000), Over/Under values can be read in raw units in therange of +/- 2.4 % of the range. When the extended range is enabled, the outputcalculated can be above or below the Hi/Lo engineering ranges specified. Thisgives the user the ability to use inputs signals that are still in hardware's linearrange. He has the option to disallow the extrapolated scaling in which case overrange outputs are disallowed. If the extended range is not selected, only the fullrange is allowed. Any other ranges would be flagged as an error.

For Example.:

Hi/Lo Eng. =20/10 Range: 1 -9999 Scale: 10,000Input = 1100 0000 0000 1000 Extrapolate Auto mode

The two MSB are stripped leaving 0x0008 = 88 converts to 0.008 in Engineeringunits. An UNDER value is specified, so the output is 9.992.

Note There are some specific concerns involving modules that usethe 2 MSB's for Over/Under Info. The OVER and UNDER valuesmarked by the hardware will appear as large decimal numbers in theinput register when displayed. You must be careful to recognize thatthese bits are used as flag information.

The values 0x8000 (32768) and OxCOOO (49152) and their associatedextended ranges are the exceptions. Other values outside the ex-tended range will be flagged as invalid inputs. This might occur if datawere being corrupted and spurious values were being used for the realinput.


Table 6 AIN Register Assignments


Reg 0 Input, from 3X reg. (Copy Traffic Copped Register to here)1 Reserved2 Status output3 Status input ,4,5 Scaling 100% Eng.6,7 Scaling 0% Eng.8,9 Manual input10,11 Auto input

Reg 12,13 Output

bit 1 2 34 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6

Reg 2 Output Status0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB LSB

Figure 28 Register 2 Status Output Bits

bit #12 Math Errorbit #11 Crossed limits, return DX Block Errorbit #10 Invalid output mode, errorbit #9 Echo Over Range from input modulebit #8 Echo Under Range from input modulebit #7 Input out of range

bit 1 2 3 4 5 6 7 8 9 10 11 12 131415 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg 3 Input Status

MSB LSB

Figure 29 Register 3 Status Input Bits

bits #6-8 Module Output Range Formatbit #9 Process Square Rootbit #10 Manual/Auto Mode (1/0)bit #11 Extrapolate/Clamp {1 /O) For Auto mode,

AIN APPLICATIONYour Ladder Diagram DX Zoom function lets you enter and observe results whilerunning the controller Online. Figure 30 illustrates a simple binary raw input


(40600) that is in the functional range and is scaled to a decimal output (40612}value.

JUti l ity iPLC OpsrF 1 - F 2

HexF 3— -F7-

Dec Bin Page-F4 Reference Editor —

ANALOG IN

INPUT FLAGS:PROCESS SQUARE ROOT: 49603 BIT09 =MANUAL/AUTO MODE, 1-MANUAL: 49603 BIT10 =EXTENDED RANGE, 1=YES: 49663 BIT11 =MODULE OUTPUT FORMAT: 40663 36:68 -

SEE NEXT PAGE FOR SELECTION CODES

Quit-F8-DEBUG-F9-1-

PAGE 1 /

DEC

INPUTS:RAW INPUT:HIGH ENGINEERING UNITS:LOV ENGINEERING UNITS:MANUAL INPUT:AUTO INPUT:

SCALED ENGINEERING OUTPUT:

40609 UINT - 009000111111111140604 FLT32 - 4995.40606 FLT32 = 0.40608 FLT32 = 0.40619 FLT32 = 1922.75

49612 FLT32 = 1022.75

49602 BIT16 = 1

Figure 30 Analog Input (AIM) DX Zoom Screen Example

iUtil ity IPLC OpsFl F2

Bin Page-F4 Reference Editor —

ANALOG IN

OUTPUT FLAGS:MATH ERROR:OVER RANGE:UNDER RANGE:INVALID INPUT FORMAT:HIGH <- LOV LIMIT:INPUT OUT OF RANGE:

VALID INPUT FORMAT SELECTIONS ARE:40963192

8192

59997499999914999

0 =>1 => 49962345

0901093109910901

-F7-Quit

-F8-DEBUG-F9-1-PAGE 2 /

49862 BIT1249662 BIT0949662 BIT0840662 BIT1640662 BIT1140662 BIT07

Figure 31 Analog Input (AIM) DX Zoom Screen Example Page 2


AOUT (Analog Output)When this function is selected from the PCFL Library, the DX block illustrated inFigure 32 is displayed. The block name is posted in the top node and the cursor ison the middle node (?????) where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

Enable

disableDone

Error

Figure 32 AOUT PCFL Function Block

AOUT Block DescriptionThis function is an Interface to output modules. AOUT supports outputs of:

4096: 0->4095 B872-011(V},002(mA)

The function works with inputs of Engineering units and produced binary output.A conversion is performed with 4096 resolution. For 4096, output is boundedfrom 0 to 4095. The function Returns power flow to the top node when finished.


Table 7 AOUT Register Assignments


Reg 0,1 Input in engineering units2 Status output register3 Status input register4,5 High engineering units6,7 Low engineering units

Reg 8 Output

Status Input .̂ Standard bit assignments

bit 1 2 34 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Status registers 2/3

MSB LSB

•» Status Outputbit #12 Math errorbit #11 Crossed limits, return DX Block Errorbit #9 Clamped highbit #8 Clamped low

Figure 33 Register 2/3 Status Bits

GM-PCFL-001 Rev. A Chapter 4 SpCClf iCatlODS 47

AOUT Application

Util i ty IPLC Ops Hex Dec

INPUTS:ENGINEERING INPUT:HIGH ENGINEERING UNITS:LOW ENGINEERING UNITS:

OUTPUT :

OUTPUT FLAGS:MATH ERROR:HIGH <= LOV LIMIT:OUTPUT CLAMPED HIGH:OUTPUT CLAMPED LOV:

ERROR, 1-YES 0-NO:

Bin Page

ANALOG OUT

402504025440256

40258

40252402524B25240252

40252

FLT32 = 2046FLT32 = 4095FLT32 = 8.

UINT - 2049

BIT12 - 0BIT11 - 0BIT09 - 6BIT08 = 0

BIT16 - 9

Qui t-F8-QEBUG-F 9-1-

PAGE 1 /

Figure 34 Analog Output (AOUT) DX Zoom Display Example


DELAYWhen this function is selected from the PCFL Library, the DX block illustrated inFigure 35 is displayed. The block name is posted in the top node and the cursor ison the middle node {?????) where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilidisplayed but no power can pass until the block is fully configured.

Enable

DisableDone

Error

Figure 35 DELAY PCFL Function Block

DELAY Block DescriptionThe Delay block can build up a Queue of delayed readings, for use with time-de-lay compensation. You enter the number of sampling instants to delay input (up to10 sampling periods). Function will carry along all values in 984 registers. Func-tion can be reset by toggling First_Scan bit. Returns power flow to the top nodewhen calculation is complete.

Note The 10th delay period does not need to be stored. When the10 period of delay has take place, the value in x(n-9) can be moved tothe output directly. Also note that x(n-O) is the "current" sampled input.

Formula: y (n) = x (n-k), k = # sampling periods delayed


Table 8 DELAY Register Assignments


Reg 0,1 Input at time n2 Status Output register3 Status Input register4 Reserved5 Last time6,7 Elapsed time since last solve (ms}8,9 Solution interval (ms)10,11 delayed OT12,13 delayed 1 T14,15 delayed 2 T16,17 delayed 3 T18,19 delayed4T20,21 delayed 5 T22,23 delayed 6 T24,25 delayed 7 T26,27 delayed 8 T28,29 delayed 9 T

Reg 30,31 Output register

DELAY Function Block Register Usage

bit 1 2 34 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg 2 Output Status

MSB LSB

bits #5-8 # of registers left to be initializedbit #4 K out of range, set k = 10

Figure 36 Register 2 Output Status Bits

50 Specifications GM-PCFL-OOI Rev A Chapter 4

bit 1 2 3 4 5 6 7 8 9 10 11 12 131415 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB

Reg 3 Input Status

L.SB

bit #1-4

bits #5-8

bits #9-12

Standard Input defined bitsTime delay, K stepsEcho # of registers left to beinitialized

Figure 37 Register 3 Input Status Bits

DELAY ApplicationAs a simple example (Figure 38) you can use the DX Zoom while Online tocreate real readings. In this example a time interval of 2 seconds is set and youcan change the value in 40600. the original value will remain until the delay ex-pires then the new value is output in 40630 as well as rippling through the delaytable. These conditions are displayed in Figure 39. You can change the number ofdelay intervals in 40603 bits 5 through 8 and observe the effect on the output.

..Utility IPLC Ops Hex Dec Bin

DELAY

INPUTS:# OF DELAY INTERVALS, K:CLEAR TO INITIALIZE:LIVE INPUT, X:SAMPLED INPUT, X(N):SOLUTION INTERVAL (MS):TIME SINCE LAST SOLVE (MS):

OUTPUT, X (N-K) :

OUTPUT FLAGS:MATH ERROR:INITIALIZATION WORKING:ILLEGAL SOLUTION INTERVAL:K OUT OF RANGE:# OF REG LEFT FOR INIT:

ERROR, 1-YES 0=NO:

Pageid i top ~~

QUEUE

40303403034030040310403084030B

43330

4030240302403024030240302

40302

nr !"

05:08 -BIT01 =FLT32 =FLT32 =INT32 =INT32 =

FLT32 =

BIT12 =BIT09 =BIT11 =BIT04 -05:08 -

BIT16 =

2153625362

1696789

5662

60000

0

QuitFQ HFRIII^—FQ 1-r o — UC.D uu — r 3— j.-*

PAGE 1 /

DEC

DECDEC

DEC

Figure 38 DX Zoom Parameter Entry / Observation Screen Example


The second screen illustrates an input value summary and you can see the vaiueschange as you change the input. NO TAG represents the queue shortly afterchanging 40600 to a value of 6000.

To properly visualize the effect of Delay you have to use ladder logic to set a solveinterval i.e. 1 second then change the input at a longer interval like 5 seconds, theresult is the values in the output on page 2 ripple through the delay bins.

lUtil ity IPLC OpsF 1 F°

LIVE INPUT, X:OUTPUT, X(N-K)

Hex DecF3 F~1 PC

# OF DELAY INTERVALS, K:

SAMPLED NPUT,SAMPLED I, DUT,SAMPLED INPUT,SAMPLED INPUT,SAMPLED INPUT,SAMPLED INPUT,SAMPLED INPUT,SAMPLED INPUT,SAMPLED INPUT,SAMPLED INPUT,

• •

X(N) :X(N-l):X(N-2):X(N-3):X(N-4)iX(N-5):X(N-6):X(N-7):X(N-B):X(N-9):

Bin Page

DELAY QUEUE

405004063040603

40610406124061440616406184062040622406244062640628

FLT32 =FLT32 =05:08 =

FLT32 =FLT32 =FLT32 =FLT32 =FLT32 =FLT32 =FLT32 -FLT32 =FLT32 -FLT32 -

60002048

2

6000600620486000204860002048506220485062

Qui t-F 8— DEBUG— F 9—1—

PAGE 2 /

DEC

Figure 39 Delay Queue DX Screen Page 2


LKUPWhen this function is selected from the PCFL Library, the DX block illustrated inFigure 40 is displayed. The block name is posted in the top node and the cursor ison the middle node {?????) where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

Enable

disableDone

Error

Figure 40 LKUP PCFL Function Block

LKUP Lookup Block DescriptionThis function is a look up table function generator which uses a linear algorithm tointerpolate between points. The function is set up for a variable point interval aswell as a variable number of points to use (2 -> 8). If the input, x, is outside of thefunctions range xO -> xN (the defined points), the output, y, will be clamped to thecorresponding output yO or yN. If the table size entered is too small or the numberof points is out of range, the function will not check the xN because the informationfrom that pointer is invalid.

Note No sorting is done on the lookup table, so that the values en-tered will be use blindly. For best operation, the independent variabletable values should be in ascending order, otherwise gaps that cannever be reached may result. This function returns power flow to thetop node when finished.


Table 9 LKUP Register Usage


Reg

Reg

0,12345,67,89,1011,1213,1415,1617,1819.2021,2223,2425,2627,2829,3031,3233,3435,3637,38

InputStatus output registerStatus input registerNumber of point pairsInput point X1Output Point Y1Point X2Point Y2Point X3Point Y3Point X4Point Y4Point X5Point Y5Point X6Point Y6Point X7Point Y7Point X8Point Y8Output

•» Output Flagsbil 1 2 34 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB LSB

12-16 fixed for all functions

bit #11 Invalid # of points, return DX BlockError

bit #10 Input out of table's range, clamped

bit #9bit #8

ReservedReserved

Figure 41 Register 2 Input Output Status Bits


LKUP ApplicationYou can make a simple table to observe the plotted points given the establishedvalues of X and Y. For example make:

X Y

0.0 0.01.0 5.02.0 10.03.0 15.04.0 20.0 (See Figure 42 and Figure 43}

An input of 0.5 will return an output of 2.5 etc,. If the input is out of the tablesrange, the output will be either 0 for an x lower than 0 or 20 for an x higher than4.0.

lUtility IPLC OpsFl F2-

Hex Dec Bin Page-4 Reference Editor —

LOOKUP TABLE

INPUTS:NUMBER OF POINTS TO USE:INPUT, X:

OUTPUT, Y:

OUTPUT FLAGS:MATH ERROR:INVALID # OF POINTS:OUT OF TABLE'S RANGE:

ERROR, 1=YES 6-NO:

-F7-

46664 INT = 5FLT32 = 6.5

Quit-F8-DE8UG-F9-1-

PAGE 1 /

DEC

40637 FLT32 - 2.5

49682 BIT12 - 640682 BIT11 - 640682 BIT18 - 6

40692 BIT IB = 0

Figure 42 LKUP Block DX Zoom Screen Page 1


Uti l i ty_P1•r l *™

X L

XI:X2:X3iX4:X5:X6:X7:X8:

IPLC Ops Hex Dec Bin Page

INPUT40600

TABLE

4063540639406134061749621496254862940633

LOOKUP TABLE

Quitco TiFRl IE FQ_1— T D— U C D U U— T y— 1 —

PAGE 2 i

OUTPUTFLT32 = 0.5

DATA TABLE:

INPUTS

FLT32 - B.FLT32 - 1.FLT32 - 2.FLT32 - 3.FLT32 - 4.FLT32 - 8.FLT32 = 0.FLT32 = 0.

Y:

Yl:Y2:Y3:Y4:Y5:Y6:Y7:Y8:

49637

TABLE

4B5074061140615496 1940623406274063140635

FLT32 =

OUTPUTS

FLT32 -FLT32 -FLT32 ;FLT32 -FLT32 =FLT32 =FLT32 -FLT32 -

2.5

0.5_10.15.29.0.e.8.

Figure 43 LKUP Block DX Zoom Screen Page 2

The result of your table definition is the availability of output values at a known lin-earity.


INTEG (Integrator)When this function is selected from the PCFL Library, the DX block illustrated inFigure 44 is displayed. The block name is posted in the top node and the cursor ison the middle node (?????} where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

EnableDone

IM ll-fiDisable

Error

Figure 44 INTEG PCFL Function Block

INTEG Block DescriptionUsing this block you may integrate over a specified time interval with NO protec-tion against integral windup (exceeding the highest limit}. You may set flags to ei-ther initialize or restart after an undetermined downtime and reset integral sum,when desired. If the initialize option is used, a reset value must be specified (i.e.zero or last output in case of power failure, DX Block Error) and calculations willbe skipped for one sample. Returns power flow to the top node when calculationis complete.

Note When initialize is performed, the reset value is copied into theoutput register. If you want to retain the current output you must trans-fer those registers to the reset input in ladder logic.

Dynamic inputs will change on every scan (i.e. xn), while calculated outputs will beleft as is (i.e. yn, tn). When the function is ready to solve, yn will be saved locallyas yn_1 (i.e. it is 1 solve old) and calculations for the new yn done. There is noneed to save yn_1 in the table because whenever the function is solved, the valuelabeled yn will be 1 solve old. On the other hand, xn_1 must be saved each solvebecause xn is dynamic from live inputs.


i U t i l i t y 4PLC Dps lElemsnt iCormiand IRef -INetworK IZoomFl F2 F3 FA- Ladder Diagram 6 F7Seg. 1 #8 /8

C )—#00101 I MEG

__|\|_|T.BlU |BB613 40003J 46600

|PCFL

60

( ) —00020

Qui t;8-DEBUG-F9-l-

Reference Data

Figure 45 Typical timer Ladder implementation


Table 10 INTEG Register Usage


Reg 0,1 Current input2 Status Output3 Status Input4 Current time5 Reserved6,7 Elapsed time since last solve (ms)8,9 Solution Interval (ms)10,11 Last Input12,13 Resetvalue

Reg 14,15 output result

Input Flags *•bit 1 2 3 4 5 6 7 8 9 10 11 12 131415 16

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Registers Status

MSB LSB

bit #1-4 Standard Assignmentsbit #5 Reset sum of integration only (for on the

fly reset)

Figure 46 Register 3 Status Bits

INTEG ApplicationYou can enter test data or monitor operation of the function by using the DX Zoomscreen from the ladder diagram menu.


Hex Dec Bin Page-F3 F4 Reference Editor —

INTEGRATOR

INPUT FLAGS:RESET SUM ONLY:CLEAR TO INITIALIZE:

INPUTS:RESET VALUE:LIVE INPUT, X:LAST SAMPLED INPUT, X(N):SOLUTION INTERVAL (MS):TIME SINCE LAST SOLVE (MS):

OUTPUT FLAGS:MATH ERROR:INITIALIZATION WORKING:ILLEGAL SOLUTION INTERVAL:

ERROR, 1=YES 0=NO:

-F7-Quit

-FB-DEBUG-F9-1-PAGE 1 /

46693 BIT05 = 646603 BIT01 = 1

46612 FLT32 - 10.0166140630 FLT32 - 1.40610 FLT32 - 1.

INT32 = 1000INT32 = 789

DECDEC

40614 FLT32 - 556.05

40602 BIT12 - 040602 BIT09 = 040602 BIT11 - 048602 BIT16 - 1

Figure 47 INTEG DX Zoom Screen


LLAG (Lead / Lag Filter)When this function is selected from the PCFL Library, the DX block illustrated inFigure 48 is displayed. The block name is posted in the top node and the cursor ison the middle node (?????) where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

EnableDonei i an

Disable

Error

Figure 48 LLAG PCFL Function Block

LLAG Block DescriptionThis function is used to pass an input value through a lead/lag filter. The filter iscomprised of a lead term (numerator) and a lag term (denominator) in the frequen-cy domain and then multiplied by a gain. The terms are independent of one anoth-er, i.e. either one can be set to zero to cancel out it's effect.

The purpose of this function is to provide dynamic compensation for a known dis-turbance. The function usually appears in a feed-forward algorithm or as a dy-namic filter. You can also use the function to simulate a first order process.

You specify the LEAD, LAG, GAIN and the solution interval, Ts. The function usesthe previous output for use by the algorithm on the next call. The function returnspower flow to the top node when calculation is complete. The resolution is gov-erned by the system 10 Ms clock.

Note When testing, be sure to vary the process input Xn. Don't justzero out the output. A negative response will result from a bump.


Table 11 LLAG Register Usage


Reg 0,1 Current input2 Status Output register3 Status Input register4 Current Time5 Reserved6,7 Elapsed time since last solve (ms)8,9 Solution interval (ms)10,11 Last input12,13 Lead term14,15 Lag term16,17 Filter gain

Reg 18,19 Output

Input Flags •*•bit 1 2 3 4 5 6 7 8 9 10 11 12 131415 16

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register 3 Status

MSB LSB

bit #1-4 Standard Bit Assignment


LLAG ApplicationIn Online Mode you can do a DX Zoom on the LLAG Function Block to verify ortest operational values.

62 Specifications GM-PCFL-001 Rev. A Chapter d

Ut t l ity J.PLC Ops Hex Dec Bin

LEAD

INPUTS:CLEAR TO INITIALIZE:INPUT, X(N):LEAD TERM:LAG TERM:GAIN:SOLUTION INTERVAL (MS):TIME SINCE LAST SOLVE (MS):

OUTPUT, Y(N) :


ERROR, 1=YES 0=NO:

Page-r\ \ tnr_u 1 LUI ~^

LAG

40603406004661246614466164660B40606

4061B

46602406024068240602

mr r

BiTai = iFLT32 - 2.FLT32 - 1.FLT32 - 1.FLT32 - 1.INT32 - 1000INT32 - 670

FLT32 = 2.

BIT12 = 9BIT09 = 0BIT 11 = 0BIT 16 = 0_

Quit-F8 DEBUG— F9— 1—

PAGE 1 /

DECDEC

Figure 50 LLAG DX Zoom Screen Example

GU-PCFL-001 Rev A Chapter 4 Sp6CJf JCatiOHS 63

LIMITWhen this function is selected from the PCFL Library, the DX block illustrated inFigure 51 is displayed. The block name is posted in the top node and the cursor ison the middle node {?????) where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

Enable

Disable

Done

Error

Figure 51 LIMIT PCFL Function Block

LIMIT Block DescriptionThis function establishes a Limit bound input between high and low values. Thefunction also keeps track of actual parameter if outside limits by keeping separateinput and output registers. If High or Low limit reached, the High or Low flag is set,and the output is clamped. The function returns power flow to the top node whenfinished.


Table 12 LIMIT Register Usage


Reg 0,1 Input register2 Status Output register3 Status Input register4,5 Low limit6,7 High limit

Reg 8,9 Output

•» Output Flagsbit 1 2 3 4 5 6 7 8 9 10 11 12 131415 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB

Register 2 Status

LSB

bit #12

bit #11

Math error

If limits are crossed (i.e. Low > = High,etc.), return DX Block Error

bit #10 Input > high limitbit #9 Input < low limit


LIMIT ApplicationIn the simplest sense, you can examine if an input is within a range by setting andor observing the function using the DX Zoom Screen. In Figure 53 You can see alow limit of 25 and a high of 75. by setting the input in 40600 over the high limit theoutput flag at 40602 bit 10 is set to 1.


lUtil i ty IPLC Dps Hex

INPUTS:HIGH LIMIT:LOV LIMIT:INPUT, X:

OUTPUT, Y:

OUTPUT FLAGS:MATH ERROR:INPUT > HIGH LIMITINPUT < LOW LIMIT;HIGH LIMIT <= LQV

ERROR, 1=YES 0-NO:

Dec Bin Page— F4 Reference Editor —

LIMITER

406064060440600

46608

40662: 40602

40602LIMIT: 46602

40662

FLT32 - 75.FLT32 - 25.FLT32 = 80.

FLT32 = 75.

BIT12 = 0BIT18 = 1BIT09 - 6BIT 11 = 0

BIT 16 - 0_

Quitrft—flFRI IR_FQ_1_^r O~UCDULJ— T J~l~

PAGE 1 /

Figure 53 LIMIT DX Zoom Screen Example


LIMVWhen this function is selected from the PCFL Library, the DX block illustrated inFigure 54 is displayed. The block name is posted in the top node and the cursor ison the middle node {?????) where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

Enable

DisableDone

Error

Figure 54 LIMV PCFL Function Block

LIMV Block DescriptionLimit velocity of change of input variable between high and low values by limitingthe input variable based on its rate of change. Keep track of actual parameter ifoutside limits by keeping separate input and output registers. If High or Low limitreached, set the flag, and clamp the output. This function returns power flow tothe top node when finished.

GM-PCFL-001 Rav. A Chapter 4 Specifications 67

Table 13 LIMV Register Usage


Reg 0,1 Current input2 Status Output Register3 Status Input Register4 Current Time5 Reserved6,7 Elapsed time since last solve (ms)8,9 Solution interval (ms)10,11 Velocity Limit per sec

Reg 12,13 Result

•» Output Flagsbit 1 2 3 4 5 6 7 8 9 10 11 12 131415 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register 2 Status

MSB LSB

bit #6 Negative velocity limitbit #7 Input < low limitbit #8 Input > high limitbit #9 Initialization workingbit #11 Illegal solution intervalbit #12 Math error

Figure 55 LIMV Register 2 Status Bits

bit #1-4 Register 3 Standard Status Input Assignment


LIMV Application

U t i l i t y IPLC Ops Hex Dec Bin Pager * tr o cii MA D-.f*~. -. rr j : * ~ cr i ( £_• ™ T o~~ • p*-i ntrT tr tf i lut? CulLur r

VELOCITY LIMITER

INPUTS:CLEAR TO INITIALISE:VELOCITY LIMIT (/SEC):INPUT, X ( N ) :SOLUTION INTERVAL (MS):TIME SINCE LAST SOLVE (MS):

OUTPUT, Y(N) :

OUTPUT FLAGS:MATH ERROR:INITIALIZATION WORKING:ILLEGAL SOLUTION INTERVAL:INPUT > HIGH LIMIT:INPUT < LOV LIMIT:NEGATIVE VELOCITY LIMIT:

ERROR, 1-YES 0-NO:

4960340610406004060840605

40612

406024360248632466324668246662

46662

BIT01FLT32FLT32I NT 32I NT 32

FLT32

BIT12BIT99BIT11BIT08BIT87BIT0B

BIT1B

Qui t

PAGE 1 /

- 1- 20.- a.= 5969 DEC- 246 DEC

= 6.

= 6= 8= 0- 0- 9- 0

- 9_

Figure 56 LIMV DX Zoom Display Data Example

GM-PCFL-OO! Rev.AChapter4 Specifications 69

MODEWhen this function is selected from the PCFL Library, the DX block illustrated inFigure 57 is displayed. The block name is posted in the top node and the cursor ison the middle node (?????) where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stil!displayed but no power can pass until the block is fully configured.

Enable

Disable

Done

Error

Figure 57 MODE PCFL Function Block

MODE Block DescriptionThis function sets up a Auto/Manual station to enable or disable automatic datatransferal to the next block. This block acts as a BLKM by moving either a manualor auto value (in floating point) to the output register. In auto mode, the auto inputis copied to the output. When put in manual, the output is overwritten by theuser's entry. The function enables power flow to the top node when finished.

Table 1 4 MODE Register Usage

Register

Reg

Reg

0,123

4,56,7

Description

Auto inputStatus output registerStatus input registerManual inputOutput register


Input Flags *• bit #5 Set Auto/Manual mode

bit 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Status

MSB LSB

•* Output Flags

bit #11 Echo Auto/Manual mode (1/0)bit #12 Math Error

Figure 58 MODE Register 2/3 Status Bits

MODE Application

Fl- -F4 Reference Editor F7-6UTO/MANUAL STATION

INPUTS:MODE: B-AUTD, 1-MANUflL:AUTO INPUT:MANUAL INPUT:

OUTPUT

OUTPUT FUGS:MATH ERROR:OUTPUT MODE:

0=AUTO, i-MANUAL:

40603 BIT05 = 140B00 FLT32 - 0.40604 FLT32 = 3.

40606 FLT32 = 3.

40682 BIT12 = 040692 BIT11 - 1

40692 BIT1B = 9

Z8-DEBUG-F9-1-PAGE 1 /

Figure 59 MODE DX Zoom Display Example


RAMPWhen this function is selected from the PCFL Library, the DX block illustrated inFigure 60 is displayed. The block name is posted in the top node and the cursor ison the middle node (?????) where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

EnableDone

UAMM

Disable

Error

Figure 60 RAMP PCFL Function Block

Ramp Block DescriptionThis function conditions data to approach a new target set point linearly given therale of approach. At each successive call, calculate the output until it is within aspecified deadband of the target. At that point set Yn = Ysp.

You must provide both the target value and the sampling rate, manually or fromanother block. You must specify the rate, towards the new set point. The blockterminates when the input reaches the new set point. You can specify a decreas-ing approach to the new set point choosing a set point lower than the current out-put.

Note The target value must be in the same units as input register andthe rate is in engineering units/sec.

You may set a flag to initialize after an undetermined downtime by storing a newsample and wailing for one cycle to collect the second sample. In this case, calcu-lations will be skipped for one sample and the output left as is. This function re-turns power flow to the top node when the calculation is complete.

72 Specifications GW-PCFL-001 Rev. A Chapter 4

Table 15 RAMP Register Usage


Reg 0,1 Set point input2 Status output register3 Status input register4 Current Time5 Reserved6,7 Elapsed Time (ms)8,9 Solution interval (ms)12,13 Ramp rate (per sec)

Reg 14,15 Output

Status Register Bits

Status Input bit #1-4 Standard Bit Assignment

bit 1 2 3 4 5 6 7 8 9 10 11 12 131415 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register 2/3 Status

MSB LSB

•» Status Output

bit #8 Ramping upbit #7 Ramping downbit #6 Ramp complete, done/working (1/0)bit #5 Ramp rate set to a negative number,

Block Errorbit #9 Initialization workingbit #11 Illegal solution intervalbit #12 Math Error

Figure 61 Ramp Register 2/3 Status Bits

RAMP ApplicationIn Online Mode you can enter parametric data and observe results by displayingthe Ramp Generator registers using the DX Zoom feature of the Ladder Diagram


Menu. For example the Dx Zoom screen illustrated in Figure 62 has the entry for:Output = 8Set Point of 20Rate of Ramp at 0.5 secAnd a Solution Interval of 1 sec (1000 MS)

When you clear bit one in the status register the function is initialized and the out-put Y{n) returns the value 8. these parameters represent a ramp that looks like:

Outpu25

20

15

10

5

0

= Y(n)

o ^*/• output at each .5 sec.

X"" Time20 40 60

Figure 62 Example Ramp Generator

Every 1 second the output increases by 0.5. An output flag is set indicating thatthe ramp is going up.

74 Specifications GM-PCFL-OOI Rev. A chapter 4

Util i ty iPLC Ops Hex Dec Bin Page Quitrr t 1=1 1=0 HAD~f - r= j : -i „ in I=Q ni=Qi ir* i=n -ir i r £. — • r o "T^-t rt?T ti trn

RAMP

INPUTS:CLEAR TO INITIALIZE:SET POINT, SP:RATE OF RAMP (/SEC):SOLUTION INTERVAL (MS):TIME SINCE LAST SOLVE (MS):

OUTPUT, Y(N):

OUTPUT FLAGS:MATH ERROR:INITIALIZATION VORKING:ILLEGAL SOLUTION INTERVAL:RAMP COMPLETE:RAMPING UP:RAMPING DOVN:NEGATIVE RAMP RATE:

. ERROR, 1=YES 0=NO:

^t; L_U i LUI —

GENERATOR

4016340160401704016840166

46172

4616246162461624616246162461624816246162

PAGE 1 /

BIT01FIT 32FLT32INT32I NT 32

FLT32

BIT 12BIT69BIT 11BIT66BIT68BIT67BIT6SBIT 16

- 1= 20.= 6.5- 1006 DEC= 250 DEC

- 20.

- 0- 0= 0- i= 0- 8- 0- 0

Figure 63 Ramp DX Zoom Screen

GM-PCFb-001 Rev. A Chapter 4 Specifications 75

RMPLN (Logarithmic Ramp Generator)When this function is selected from the PCFL Library, the DX block illustrated inFigure 64 is displayed. The block name is posted in the top node and the cursor ison the middle node (?????) where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

Enable

DisableDone

Error

Figure 64 Log RAMP PCFL Function Block

RMPLN Block DescriptionThis function conditions the signal to approach new target set point logarithmicallygiven the rate of approach. At each block activation, calculate the output until it iswithin a specified deadband. At that point set Yn = Ysp.

You must provide both the target value and the sampling rate. You must specifythe time constant for the logarithmic ramp to reach 63.2% of the new set pointThe block process completes when the input reaches the new set point +,- a spe-cified deadband. You can also specify an increasing or decreasing approach tothe new set point.

Note The target value must be in same units as input register and therate time constant is in seconds.

You may set a flag to initialize after an undetermined downtime by storing a newsample and waiting for one cycle to collect the second sample. In this case, calcu-lations will be skipped for one sample and the output is left as is. The function re-turns power flow to the top node when the calculation is complete.


Table 16 RMPLN Function Register Usage


Reg 0,1 Input Set Point2 Status Output register3 Status Input register4 Current Time5 Reserved6,7 Elapsed time since last solve (ms)8,9 Solution interval {ms}12,13 Time constant of rate of change towards set point (sec)14,15 Deadband {eng. units)

Reg 16,17 Output

Status Input*, bit #1 First scan initializebit #2 Power up set delta t = 0

bit 1 2 3 4 5 6 7 8 9 10 11 12 131415 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Status

MSB LSB

•* Status Outputbit #4 A parameter is negative #, return

DX Block Error

bit #6 Ramp complete, done/working (1 /O)bit #7 Ramping downbit #8 Ramping upbit #9 Initialization workingbit #11 Illegal solution intervalbit #12 Math error

Figure 65 Log RAMP Register 2/3 Status Bits


RMPLN Application

In Online Mode you can enter parametric data and observe results by displaying

the Ramp Generator registers using the DX Zoom feature of the Ladder Diagram

Menu. In Figure 66 with a set point of 25 and deadband of 2 the output (Yn)

clamps to the setpoint at 23 thereby guarding against a possible asymptotic ap-

proach.

Output = Y(n)

25

\ Deadband

Time

20 40 60

Figure 66 Log Ramp Setpoint Interaction

lUtility iPLC Ops Hex Dec Bin Page

LOGARITHMIC RAMP GENERATORINPUTS:

CLEAR TO INITIALIZE:SET POINT, SP:TIME CONSTANT OF RAMP (SEC):SNAP TO SP, WIDTH:SOLUTION INTERVAL (MS):TIME SINCE LAST SOLVE (MS):

OUTPUT, Y(N):OUTPUT FLAGS:

MATH ERROR:INITIALIZATION WORKING:ILLEGAL SOLUTION INTERVAL:RAMP COMPLETE:RAMPING UP:RAMPING DOVN:NEGATIVE SNAP VIDTH/TIME CONSTANT:

ERROR, 1-YES 0=ND:

49603 BIT0149609 FLT3249619 FLT3249612 FLT3240603 INT3240606 INT32

40614 FLT32

40602 BIT1240602 BIT6940602 BIT1140602 BIT0B40662 BIT0840682 BIT0740662 BIT04

49602 BIT16

Quit

PAGE 1 /

- 1- 25.- 6.5- 2.= 1608 DEC- B89 DEC

= 25.

- 6= 6= 6= 0= 0- 0= 0

- 0

Figure 67 RMPLN DX Zoom Display Data


RATEWhen this function is selected from the PCFL Library, the DX biock illustrated inFigure 68 is displayed. The block name is posted in the top node and the cursor ison the middle node (?????) where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

EnableDone

MA I t-

Disable

Error

Figure 68 RATE PCFL Function Block

RATE Block DescriptionThis function calculates the rate of change (i.e. derivative) between the last two in-put values read. If the initialization flag is set, function will record a sample and setappropriate flags. The function returns power flow to the top node when finished.

An error flag is set if there is divide by zero, and the function returns DX Block Er-ror.

Table 17 RATE Block Register Usage

Register

Reg 0,1234

56,78,910,11

Description

Current inputStatus Output registerStatus Input registerCurrent TimeReservedElapsed time since last solveSolution interval (ms)Last input

(ms)

Reg 12,13 Output Result


Status Input*- bit #1-4 Standard Bit Assignment

bit 1 2 34 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Status

MSB LSB

•* Status Output

bit #9 Initialization working

bit #11 Illegal solution intervalbit #12 Math errorbit #16 standard error

Figure 69 Rate Register 2/3 Status bits

Rate Application

In Online Mode you can enter parametric data and observe results by displaying

the RATE function registers using the DX Zoom feature of the Ladder Diagram

Menu.

lUtility iPLC Ops Hex Dec Bin Page-3 F4 Reference Editor —

RATE (DERIVATIVE)-F7-

INPUTS:CLEAR TO INITIALIZE:LIVE INPUT, X:LAST SAMPLED INPUT, X(N):SOLUTION INTERVAL (MS):TIME SINCE LAST SOLVE (MS):

RATE (/SEC):


ERROR. 1-YES 0=NO:

40663 BIT01 - 140606 FLT32 - 19.40610 FLT32 - 19.40608 INT32 =40686 INT32 =

Q u i t-F8-DEBUG-F9-1-

PAGE 1 /

DECDEC

40612 FLT32 = 1.9

40502 BIT12 = 040602 BIT09 = 040602 BIT11 - 0

40602 BIT16 - 0

Figure 70 RATE Block DX Zoom Display


SEL (Select)When this function is selected from the PCFL Library, the DX block illustrated inFigure 71 is displayed. The block name is posted in the top node and the cursor ison the middle node (?????) where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

Enable

DisableDone

Error

Figure 71 SELect PCFL Function Block

SEL Block DescriptionThis function compares up to four inputs and selects either the highest, lowest, oraverage to take action on. The user chooses which individual inputs to selectfrom. For Bumpless transfer, use the output of the selector as the input to the de-selected loops.

The output register is a copy of the selected input. The function returns powerflow to the top node when finished.

o Formula:

if ( high select) :if (low select) :if ( average select}

y = Max (active inputs)y = Min (active inputs): y = ave (active inputs)

GM-PCFL-001 Rev. A Chapter d Specifications 81

Table 18 SEL Block Register Usage

Register

Reg

Reg

0,1234,56,78,910,1112,13

Description

ReservedStatus Output registerStatus Input registerInput x1Input x2Input x3Input x4Output y

Status Input Flags bit # 5 Input 1 activated = 1bit # 6 Input 2 activated = 1bit # 7 Input 3 activated = 1bit # 8 Input 4 activated = 1bit #9,10 select 0 = ave, 1 = low, 2 = high

bit 1 2 3 4 5 6 7 9 10 11 12 131415 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Status

MSB LSB

•* Status Output Flags

bit #10 Invalid selection choicebit #11 No inputs selected, set Block Errorbit #12 Math errorbit #16 Standard error

Figure 72 Select Register 2/3 Status Bits

SEL ApplicationIn Online Mode you can enter parametric data and observe results by displayingthe RATE function registers using the DX Zoom feature of the Ladder DiagramMenu.


LJ t i l i ty iPLC Ops Hexr •• n r iT 1 r £. r J

INPUT FLAGS, INACTIVATEDINPUT 1:INPUT 2:INPUT 3:INPUT 4:SELECTION CHOICE:

0=AVE, 1=LOWINPUTS:

INPUT 1;INPUT 2:INPUT 3:INPUT 4:

OUTPUT:OUTPUT FLAGS:

MATH ERROR:NO INPUTS SELECTED:

3ec Bin Page"4 RsT^rGncE tdiTor r /-

HIGH/LOW/AVE SELECTER, 0-DEACTIVATED:

49603 BIT05 -49603 BIT06 =49603 BIT07 -40603 BIT08 =40603 09:19 =

, 2=HIGH

40604 FLT32 =40606 FLT32 =40608 FLT32 =40610 FLT32 =

40612 FLT32 -

40602 BIT12 -40602 BIT11 -

INVALID SELECTION CHOICE: 49602 BIT 10 =ERROR, 1=YES 0-NO: 49692 BIT16 =

r

11112

0.6.4.2.

6.

0000

QuitR^TlFRI irc—FQ_1Q"™Ut DU U"*r :J— l —

PAGE 1 /

DEC

Figure 73 SELect DX Zoom data Display

GM-PCFL-001 Rev A Chapter 4 Specifications 83

Regulatory Control Block Descriptions

ONOFFWhen this function is selected from the PCFL Library, the DX block illustrated inFigure 74 is displayed. The block name is posted in the top node and the cursor ison the middle node {?????} where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

Enable

DisableDone

Error

Figure 74 ONOFF PCFL Function Block

ONOFF Block DescriptionThis function is implemented to control an input signal between two limits. Thereare 2 states control can be in, fully ON or fully OFF. You have the option for direct/reverse configuration. For the direct configuration, when Input < setpoint - (db),the output is set to ON, and when Input > setpoint + (db), the output is set to OFF .For the reverse configuration, the opposite is true. The controller will exercisethese limits with hysteresis via a deadband {db). When the input is inside thedeadband, no change is made. If no deadband is desired, the DB should be set tozero.

You can also elect to force the output manually to either On or Off. There are twobits that control this option: the high bit puts the block in manual and the low bitforces the On or off state.

Status Register bits 6 7

1 11 0

84 Specifications

Manual force OnManual force Off

GM-PCFL-001 Rev. A Chapter 4

0 1 Auto0 0

Two of these blocks can be used together to produce a three mode controller withhysteresis. Your logic must detect each controllers output and select the one thatisn't zero.

D Formula:

Manualif Manual force is on

y = Onelse if Manual force is Off

y = Off

Direct:if (X < YSP - DB)

y = ONelse if (X> YSP + DB)

y = OFFelse Y = Previous {ON,OFF] - refreshed

Reverseif (x<YSP-DB)

y = OFFelse if {X> YSP + DB}

y = ONelse Y = Previous {ON,OFF} - refreshed

Table 19 ONOFF Register Usage


Reg 0,1 Current Input2 Status Output register3 Status Input register4,5 Set point6,7 Deadband around setpoint8,9 ON (max output)10,11 OFF (rnin output)

Reg 13,14 Output, ON or OFF


Status Input*- bit #5 0=direct 1 = reversebit #6 0=auto 1=manualbit #7 Offeree off 1 = force on

bit 1 2 34 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6

Status0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB LSB•* Status Output

bits #16-12 Standard Output Flagsbit #11 Output set to ON=1 OFF=0bit #10 Echo manual override Manual=1 Auto = 0bit #9 Deadband set to negative number, return

DX Block Error

Figure 75 ON-OFF Register 2/3 Status Bits

ONOFF ApplicationIn Online Mode you can enter parametric data and observe results by displayingthe ONOFF function registers using the DX Zoom feature of the Ladder DiagramMenu.


ILItil ity iPLC Ops HexrF 1 F 2 F 3—

Dec Bin Page-F4 Reference Editor

ON/OFF CONTROLLER

INPUT FLAGS:B=DIRECT, 1-REVERSE:MODE, 0=AUTO, l^MANUAL:MANUAL, 8-FORCE OFF, 1-FORCE ON:

INPUTS:DEADBAND:'ON' OUTPUT:'OFF' OUTPUT:SET POINT, SP:INPUT, PV:

OUTPUT, Y:OUTPUT FLAGS:

MATH ERROR:MODE, 0=AUTO, 1=MANUAL:ECHO OUTPUT, 0=OFF, 1-ON:NEGATIVE DEADBAND:

Quit-F8-DEBUG-F9-1-

PAGE 1 /

48603 BIT05 = 049603 BIT66 = 049603 BIT07 - 6

48606 FLT32 = 1.48608 FLT32 = 6040610 FLT32 =48604 FLT32 =48600 FLT32 =40612 FLT32 =

48602 BIT12 = 040602 BIT10 = 040602 BIT11 = 040602 BIT09 = 0

40602 BIT1S = 0

64.62.65.64.

Figure 76 On/Off DX Zoom screen

An example of direct configuration is a thermostat for temperature control. Whenthe temperature (x) is below the low threshold the heater (y) is turned On(x < SP-db). While the temperature begins to climb, the heater stays on until thetemperature crosses the high threshold.

You can exercise the example above by using the DX screen and entering varia-tions in input 40600 while observing the control at the Output.


PIDWhen this function is selected from the PCFL Library, the DX block illustrated inFigure 77 is displayed. The block name is posted in the top node and the cursor ison the middle node (?????) where you must assign the table starting register ref-erence number. When you complete the middle node assignment the total numberof registers assigned to this function is automatically placed in the bottom node foryou. If you do not make the entry and press the return key the register total is stilldisplayed but no power can pass until the block is fully configured.

Enable

DisableDone

Error

Figure 77 PID PCFL Function Block

PID Block DescriptionPID is used to control an analog loop to balance the amount of energy or materialbeing supplied to a process against the amount of energy or material consumedby the process.

This is accomplished by comparing a measurement, termed the Process Variablecontrol input X(n) with a "setpoint". The difference between the measured inputand setpoint is termed the "error".

The error value is passed into a control algorithm that calculates the control value(output) Y(n) necessary to set the controlled process so that the measurement isequal to the set point. Figure 78 Illustrates the major components of a simple con-trol loop.


Control Input

Controller

Output Y(n)ControlProgram

SP

Measurement

Setpoint

Figure 78 Simple Control Loop

PID is made up of three control types:

Proportional (P) - Provides an output which is proportional to the error.

Integral (I) - An addition to the proportional output based on how longthe measurement has been away from the set point.

Derivative (D) An addition to the proportional output based on how fastthe measurement is moving away from the set point.

Process control is seldom satisfied in simple terms as illustrated above and oftenincludes multiple controlled inputs as well as a combination of two or all three ofthe PID algorithms. The interrelationship of these components is better illustratedin Figure 79.


Figure 79 PID Block Diagram In Typical ISA Structure


a Basic comparison between PID and PID2:

PID2 runs as a loadable in the 984, is based on integer math and requires 30 reg-isters. PID was developed to run using floating point math and requires 44 regis-ters. As a part of PCFL functionality PID is currently available on thePC-E985-685 and PC-E984-785 controllers.

There are three major differences between PID and PID2:

a PID uses DIN/ISA Standard structure for a non interacting PID algorithm, whilePID2 does not.

o PID uses floating point math while PID2 uses integer math. PID trades off ex-ecution speed for precision enabling it to be used in complex situations whereprecision and accuracy are important. It is not meant for high speed loopswhich can run with reduced accuracy.

a The P, I and D constants are represented differently. PID2 uses a proportionalband for tuning, common with analog controllers. PID uses a gain instead, morecommon with digital controllers. The proportional band is just 100/Gain. PID de-fines the integral time as seconds/repeat, while PID2 has repeats/minute. Alsoa larger integral time constant in PID decreases the integral action but in PID2 alarger value increases the Integral action. PID uses a derivative time constant inseconds as opposed to PID2 which measures in minutes.

Option/Feature Comparison:

OPTIONS/FEATURES PID/PCFL PID2

Structure DIN/ISA Standard InteractingNon interacting

Arithmetic 32 bit Floating Point Integer (16, 32, 48}

Solve Time Medium-Slow (> 1 Sec.) Fast (< 1 second)

Modularity:Separate P Yes No

Yes YesYes No

GM-PCFL-001 Rev A Chapter 4 SpCClfiCatJODS 91

OPTIONS/FEATURES PID/PCFL PID2

Process VariableScalingAlarming

Tuning constant units:P

No-Separate functionNo-Separate function

Gain (Unitless)SS

YesYes

Proportional Band %/%Mirr1

Min

Tuning Constant Range

D

No LimitationNo LimitationNo Limitation

5-500%0-99.99 Min0-99.99 Min

Solution Interval RangeMinimumMaximumMin Increment

Integral Preload

100msNo Limitation10msNot directly

100ms25.5seconds100msYes


Table 20 PID Register Usage


Reg 0,1 Controlled input2 Output Status3 Output error flags4 Reserved5 Input Status

PID Register Definition (Cont)Inputs

6,7 Set point8,9 Manual Output Y10,11 Summing Junction

Outputs12,13 Control difference, Deviation14 Previous mode

15,16 Elapsed time since last solve, (ms)17,18 Previous system deviation19,20 Previous input21,22 Integral part for Output Y23,24 Differential part for Output Y25,26 Proportional part for Output Y27 Previous operating status

Timing Information28 Current time29 Reserved30,31 Solution interval (ms)

Inputs,32,33 Proportional gain34,35 Reset time36,37 Derivative action time38,39 High limit for Output Y40,41 Low limit for Output Y42,43 Manipulated control output


bit 1 2 3 4 5 6 7 9 10 11 12 131415 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register 2 Status Output

MSB LSB

bit #16 Means an Error has occurred, returnDX Block Error

bit #15 Means the size of the allocated registertable is too small, return DX Block Error.

bit #14 Reservedbit #13 Unknown PCFL function, return DX

Block Errorbit #12 Means a Math error, invalid floating

point input or output set DX Block Error.

For Time Dependent Functionsbit #11 Illegal solution intervalbit #10 Reservedbit #9 Initialization workingbit #3 Output highbit #2 Output lowbit #1 Error marker set

Figure 80 Register 2 Bit Definition

bit 1 2 34 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register 3 Error Word

MSB LSB

Error word = 23 Negative Derivative set Block Error= 22 Negative Integral set Block Error= 21 High Limit < = Low Limit

Figure 81 Register 3 Bit definition


bit 1 2 3 4 5 6

1 0 0 0 0

MSB

bit#1bit #2bit #3bit #4bit #5bit #6bit #7bit #8bit #9bit #1 0bit #11bit #12

7 8 9 10 11 12 131415 16

0 0 0 0 0 0 0 0 0 0 0 Register 5 Input Flags

LSB

First Scan:ReservedTimer overrideReservedReservedManual modeHalt modeReservedProportionalIntegralDerivativeDerivative based on XD/X (0/1)

Figure 82 Register 5 Input Flags

PID ApplicationExecution times based on floating point emulation were calculated using times es-timates from an emulation package and estimates for the floating point interfacedeveloped

GM-pcFL-001 Rev. A chapter 4 Specifications 95

lUtlHty iPLC Ops Han Dec

MODES;MANUAL OVERRIDE:0=AUTO, L=HALT:PROPORTIONAL:INTEGRAL:DERIVATIVE:

TUNING CONSTANTS:GAIN, KP:INTEGRAL TIME (SEC/REPEAT),DERIVATIVE TIME (SEC), TD:

INPUTS:MANUAL OUTPUT:SOLUTION INTERVAL (MS), TSSET POINT, SP:CONTROLLED INPUT, X(N):

OUTPUTS:CONTROLLER OUTPUT, Y (N) :

ERROR, UYES 0-NO:

Bin Pag

PID

40605"10605•=10605•1060540605

•10632Tl : 40634

10636

10608•10630•106064B60B

40642

4B602

P7_

BIT06 =BIT07 -BIT09 =EIT1S =BJT11 -

FLT32 =FLT32 =FLT32 =

FLT32 -INT32 =FLT32 -FLT32 -

FLT32 =

BIT16 =

Quit..— ,,pg fjFBLJG— F9— 1—

PAGE 1 /

e0

09e

7.510.

0.2

25.1BS0 DEC21.3.521529

0.

1

J U t i l i t y J.PLC Ops Hen Dec

DERIVATIVE BASIS, 0=XD OR 1=X:SlI+iING JUNCTION:HIGH LIMIT FOR OUTPUT:LOV LIMIT FOR OUTPUT:

CONTROL SUMMARY:SET POINT, SP:CONTROLLED INPUT, X(N):DEVIATION, X D :P CONTRIBUTION:I CONTRIBUTION:0 CONTRIBUTION:

CONTROLLER OUTPUT, Y(N):TONING CONSTANTS:

GAIN, KP:INTEGRAL TIME (SEC), TI:DERIVATIVE TIME (SEC), TD:

Bin Pagnee Editor —

PID

40605406104063640640

496064060040612406254062140623

40642

406324063440636

e_

BIT12 =FLT32 =FLT32 =FLT32 -

FLT32 -FLT32 =FLT32 =FLT32 -FLT32 -FLT32 -

FLT32 =

FLT32 -FLT32 =FLT32 -

QuitFB— DEBUG— F^l- *

PAGE 2 /

00.2B0.

-2B0.

21.3.52452917.475470.

0.0.

0.

7.510.0.2

J U t i l i t y IPLC Ops Hex Dec B i npfl F2 ' F3 F4 Referenca E

PID

OUTPUTS:ERROR:ERROR VORD:

21 = HIGH LIMIT <- LOV LIMIT22 = NEGATIVE INTEGRAL TIME23 = NEGATIVE DERIVATIVE TIME

MiTH ERROR:INITIALIZftTION VORKING:ILLEGAL SOLUTION INTERVAL:OUTPUT HIGH:OUTPUT LOV:

TIMER DATA:CLEAR TO INITIALIZE:SOLUTION INTERVAL (MS), TS:TIME SINCE LAST SOLVE (MS):

CONTROLLER OUTPUT, Y(N):

PagJitor -

4960240603

40602106024B6024060240602

406054063040615

40642

eF7

BIT 16 = 0INT = 0

BIT12 = 0BIT09 = BEIT11 - 06IT03 = 0EIT02 - 0

BIT01 = 1I NT 32 = 10B0INT32 = SB8

FLT32 ; 9.

Q u i t— FB-OEBUG-F 9-1-

PAGE 3 /

DEC

DECDEC

Figure 83 PID DX Zoom Display


As described in prior functions, the controller firmware was updated after Modsott1.2 release and some register assignments were altered, this document illustratesthe registers as they will appear in Modsoft release after 1.2. If you require the useof this function with Modsoft 1.2 use the update disk AS-PCFL-000. If any prob-lem is encountered contact Modicon Customer Service.

Customer Service & Technical Assistance

MODICON telephone numbers are as follows:

O To call us from anywhere in North America except from within the state ofMassachusetts: 1-(800)-468-5342

a To call us from within Massachusetts or from outside North America:1-{508}-975-5001

Customer Service - When calling the Modicon telephone number, ask for servicefrom the list below.

When calling the 800 number, you will get a recording asking you to enter a onedigit code for the type of service you want (listed below). However, this only workswith a "touch tone" phone. If using a dial phone, hang on and the operator will in-tercept after a short pause.

The service categories - and extra digit code responses for push-button phones -are:

1 - Hardware or software technical support

2 - Order entry, buying hardware or software

3 - Return/exchange status inquiries

4 -Training/course registration inquiries

5 - General information other than above.


Appendix AExecution Times

a The following solution time estimations are provided to help thedesigner in choosing the ladder solution to a control problem.

GM-PCFL-001 Rev. A Execution Times 99

Execution times for PCFL Functions

This table gives an estimate for solution times for PCFL functions.

NOTE: All times are in mSec. for a full solve.

Func # Name Estimate

0102

03

3031

32

33

34

35

3637

3839

41

42

43

44

73

75

AVE

CALCEQN

ALARMA_INA_OUTDELAYLKUPINTEGL_LAGLIMITLIM^VMODE

RAMPRMPLNRATESELECT

ONOFFPID

4.7

3.83.4 - 70 (15+ mSec Typical)

3.7

3.4

3.8

2.35.0

2.9

6.8

1.7

3.80.7

3.35.1

2.1

2.7

2.4

7.5

100 Execution Times GM-PCFL-001 Rev. A

Appendix BExamples

a This Appendix uses the individual tools described in Chapter 4in applications that approximate real world process control re-quirements.

GM-PCFL-001 Examples 101

EQN (Equation) Example

This Example illustrates a flow calculation using a Pitot tube.

Ui

Figure 84 Flow Instrumentation

*IL.T

Po

Pi

The Equation for velocity is derived from the Bernovlli equation which is:

U, = C-

Where:

Ui is the Velocity in ft/sec

gc is the gravitational constant = 32.174

P is the fluid pressure in psia

P. is the static pressure in psia

p is the density of the fluid in lt>m

C is an empirical constant

Program the equation such that

The PCFL Variable

A = Po

B = P.i

C = C

lbmft

102 Examples GM-PCFL-001

The desired EQN to be programmed is:C x SORT (2x32.174 x (A-B)/D)

To convert units of psia to Ibf/ft2 Multiply by 144 an then multiply the constants toget the final equation.:

C x SORT f 9226.1 x (A-BJ/D)

The table of equation codes generated is:

Register Hex contents Operation4x+12

+13

+ 14+15+ 16+ 17+ 18+19

+20+21

+22

+23

OAOO

0100

9266.1

0800

0900

001 A

0012

OBOO

0006

0018

0012

GetCGet Flt32

Get AGetBSUBMULTGetDDivideSQRTMULT

You set up Ladder logic to transfer data to the variables A, B, C, and D

Given:Water at 250 Degrees F has a density of 58.9 Ibm/ft3

Use measured pressures of Pi = 15 psiaand Po = 100 psia. The constant is taken as 0.61

Then the result in 4x+2,3 is 70.539 ft/s

GM-PCFL-O01 Examples 103

AGA3 Example

Formula Decomposition

This example is intended to illustrate a PCFL Solution for a gas flow calculation.This calculation is common with natural gas applications. It demonstrates how theAGA3 gas flow equations would be implemented. The Modsoft program is namedAGA3.

American Gas Association - Report 3 which corresponds toANSI/API 2530 Standard andGPA 8185-85 Document

Given the following volumetric flow equation (for flow through an orifice when gasis known, Ideal):

q v = N 3 x K x Y ! d 2 [ T b x Z b / P b ] [ P f 1 x A P / G i x Z f 1 x Tf ] °-5

AGA3 quation 56 Page 37

K is determined from a lookup table, based on it's Pipe Beta (ratio of orifice diam-eter to pipe diameter). You set up the look up table for this or determine a manualvalue. Once set, the value does not change. One central table can be configuredto do the lookup, and a block move when ever a particular type is needed.

The Flange tap equation is: Y, = 1 - ((0.41 + 0.35B4) x Acoustic Ratio)

The Pipe taps equation is:YT = 1 - ((0.333 + 1.145 x{ B2+0.7B5 + 12 x B13)) x Acoustic Ratio

where: Acoustic ratio = (dp/usp) / (cp/cv) = dp/usp(cp/cv)

Note Obtain the cp/cv ratio for the gas you are dealing with. Oncedetermined, it would be treated as a constant.

In preparation for ladder logic implementation the A, B, C, and D terms are identi-fied and the main equation is separated int two equations:


qv2:

qv = N3 x K x Y, x d2 x (Tb x Zb / Pb)

t t tB C D

Figure 85 qv1 and qv2 defined

ccv

cvPPPPmv

mvPcvmv

N3 = 18.891 3K, = 0.75Y, = 0.95d, = 2.5Tb = 288.7Zb = 0.99949Pb = 101.563Pf, = 101

AP=14G| = 0.55392Zf, = 0.9996Tf =298

ConstantFlow Coefficient, K = (d,pd) (look up table)Expansion factor upstream tap treat as variable[=] mm orifice diameter constant for applicationBase Temperature KelvinBase Compressability factorBase Pressure [=] kPaUpstream static pressure [=] kPa

Differential pressure [=] kPaSpecific gravity of Gas {air = 1) ref. table 5 pg.48Upstream Gas CompressibilityGas Temperature Kelvin

c = constantcv= calculated variableP = parameter (User entered)mv= Measured variable

Other parameters are:P Pd = 0.05 mm. Pipe DiameterP cp/cv = 1.307 Specific heat ratio

GM-PCFL-OO! Examples 105

cv Pipe Betacv Acoustic ratio

Ladder Development

the two parts of the equation that program in PCFL control logic as:

qv1 = SORT { ( A x B } / 6.55392 x C x D )

which should be written to the equation at the example reference 40600. the func-tion codes begin at 40614.

The second part of the equation is:

qv2 = 0.0000534694 x C x C x (DA2) x A

In manual mode (ie all 3 AJN functions are set to manual in network 2 and the twomode functions are set to manual in Networks 3 and 5), Equation 2 solves to be:.

qv2 = 0.05646 m3/s

Ladder Implementation

The equations developed above are implemented in five ladder logic networks.These networks are presented for example and as a means of illustrating an in-stance of logic development using the PCFL library together with the standardcontroller logic functions.

106 Examples GM-PCFL-OOI

Quit•M —Seg.

1- 'I 1- Id [-1-1 #1 /I

#0009 06091_jXj_|T0.lU00001 40061-1

03001 40010

4001B

00002 #0008J

40019 46019 40319

46100 40130 40050IBLKM |BLKM IBLKM#0961-1 #0001J #0001-1

60002

Reference Data

Figure 86 Timer controlled Extract of Live data table

LUti l i ty J.PLC Ops lElement ^Command iRef INetwork iZoom QuitrFl F2 —Seg. 1 #2 /2

•^0120

4̂0122^EMTHDIVFP-I

1

F3 F4- Ladder Diagram 6 F7 FB-CEBU&-F9-1-

AIN— 1

401001- IPCFL

AIN

140130

-IPCFL

AIN

148050

-IPCFL -#0014-1 #0014J #00WJ

4011214030BIBLKM

40142143364IBLKM

40062140610IBLKM

#0002-1 #6002-1 #0002J

rence .

Figure 87 Pipe Orifice and Upstream Temperature and Pressure


Uti l i ty J-PLC Ops Êlement IL

Seg. 1 #3 /3

B8010 46124

140150| BLKM#9002-1

0B010 40124

49250BLKM

#0092-

LKUP

149150IPCFL#9039-1

LKUP

49258IPCFL#9839-1

Suite

ommand -IRef iNetuork iZoom Quit4- Ladder Diagram 6 F7 F8-OEBUG-F9-1-

09010 0 E

40

40E

#0f

482

48E|BL#8E

h on pipe

f-

87

56KM

87

58KM82âpe

49124

49406IBLKM#9662-1

40124

40586IBLKM#6382-1

(fJC) o flange

MODE 48

1 146356 48IPCFL -|B#6088-1 #9

tap (NO)

856

736LKM002-J

Figure 88 Pipe and Flange Beta with Provision for Manual Override

lUtil ity IPLC Ops Êlement iCommand iRef iNetuork IZoom QuitFl F2 F3 F4- Ladder Diagram 6 F7 FB-DEBUG-F9-1-Seg. 1 #4 /4 40312 13146

CALC

140300IPCFL#0014-1

49312

140404

-|BLKM#0962J

46312

146584IBLKM#6082-1

48112

140604IBLKM#0802-1

40142

140686IBLKM#6882-1

flcRat io Acoustic ratio-Reference Data

Figure 89 Acoustic Ratio Calculation and Setup for qv Calc


Util ity 1PLC Ops J-Ele

Sea. 1 #5 /Sh |

06010 EQN

4 34 08IPCFL#0064-1

00010 EQN!40560IPCFL#0064'

40412140B00

#0062-

46512140800-|BLKM#0002-1

ment ^Command iRefF4- Ladder Di

MODE 40806 40121 1 149800 4070B 4071

#0008-1 #8002-1 #000

Switch on pipe ta

J-Netuork iZoom Qu i t

60019 9 E

0 EQN 40612 EQN1 1 1

0 46606 40704 4B796

2-1 #6926J #9692-1 #0026-1

Figure 90 Equations for qv1 and qv2

Alphabetic Operand List

Modsoft Ladder development provides users the oportunity to annotate registerreference useage as a documentation function. The Lister can output variousforms of documentation depending on your requirements and selections. The fol-lowing documentation was taken from a symbolic reference listing of the program.

000010 Switch on pipe tap (NC) or flange tap (NO) Calc400002 Constant Sweep Target400003 Actual scan time, to the nearest 10 ms400010 Table of Live Data400019 Live Data400050 AIN Raw Upstream Temperature400062 Tf K Upstream temperature400100 AIN Raw Upstream static pressure, usp400112 usp KPa Upstream static pressure400120 d mm Orifice diameter, d400122 pd mm Pipe diameter, pd400124 Beta Pipe Beta, B400130 AIN Raw differential pressure, dp


400142 dp KPa400150400187 K_pipe400250400287 KJIange400300400304 KPa400308 KPa400310cp_cv400312AcRatio400400

400404

400406

400412 Y1_pipe400500

400504

400506

400512 Y1_flange400600

400604 KPa

400606 KPa

400608 Zf 1

400610 K

400612

400618 Gi

400700

400704

400706

400708

400710 mm

400712 qv mA3/s

400800

400804

400806

400850

400854

400856

differential pressureLKUP Input for Pipe Beta, range of 0.100-0.700K for Pipe Beta range 0.100 - 0.700LKUP Input for Flange Beta range of 0.100-0.700K for Flange Beta range 0.100 - 0.700CALC for Acoustic ratio, dp/usp*(cp/cv)Differential Pressure input for AcRatioUpstream pressure input for AcRatioSpecific heat ration for gas, Cp/CvAcoustic ratioEQN pipe tap Y1 calculationAcoustic ratio input for Y1 pipe tapPipe Beta input for Y1 calcY1 pipe calculationEQN flange tap Y1 calculationAcoustic ratio input for Y1 flange tapFlange Beta input for Y1 calcY1 flange calculationEQN for 1 st part of qvUpstream static pressure input for qv calcdifferential pressure input for qv calccompressibility factor for qv calcTemperature input for qv calcqv1 outputSpecific gravity of gas, air=1, methane=0.55392EQN for 2nd part of qv, includes 1 st part1 st part input for qv calcK input for qv calcY1 input for qv calculationd input for qv calculation

Volumetric flowMODE, Input allows manual override for Y1Y1 input for manual overrideY1 used for qv EQNMODE, Input allows manual override for KK input for manual overrideK used for qv EQN


PID Example

This example illustrates how a typical PID Loop could be configured.(Refer to illustrations of the Ladder Logic)

prior to the detailed logic there is some set up logic to define the timing and simu-late the field input value. The actual calculation logic begins with the AIN block(Figure 91) which takes raw input, simulated to cause the output to run betweenapproximately 20 and 22 when the engineering unit scale is set to 0-100. The Pro-cess variable over time should look something like Figure 92.

^Ut i l i ty iPLC Ops lElement iCommand IRef INetwork IZoom QuitrFl F2 F3 F4- Ladder Diagram 6 F7 F8-DE8UG-F9-1-Seg. 2 #1 /3

#00B3| AIN

H\r— |T0.iH00100 40185J 40196

IPCFL

LKUP

149126

-IPCFL

RAMP

140160

-IPCFL

_

MODE

140190

-IPCFL

PIO1402B0

-IPCFL

60UT 69106

146256IPCFL -

#6914-1 #0039J #0014-1 #000BJ #0944-1 #6909-1

00100 46112

146126IBLKM

40157

1402B0IBLKM

40172

140199IBLKM

40196

140266IBLKM

40242

146250IBLKM

#0002-1 #0002J #0002J #6962-1 #0002-1

ren e [

Figure 91 Main Logic for PID Control


ProcessVariableValue

20

Time

Figure 92 Simulated Process Variable under Loop Control

Main PID Ladder LogicThe output of the AIN block is block moved to the LKUP block which is used toscale the input signal recognizing that the input sensor is not likely to producehighly linear readings. The result is an ideal linear signal. Figure 93 illustrates thetypical results of using the LKUP function.

7 Points DefinedIn Look Up table

100

80

6050 Linearized Signal

Actual Input40

20

Input2040 50 60 80 100

Figure 93 Typical LKUP Results

The Lookup Table output is block moved to the PCFL RAMP function. The Rampfunction is used to control the rise (or fall) of the setpoint for the PID Controllerwith regard to the rate of ramp and the solution interval. In this example the set-point is established in another logic section to simulate a remote setting. The


MODE function is placed after the Ramp so you can elect to switch between theRamp generated Setpoint or a manual value.

The PID Block is actually controlling the process simulated by the logic inFigure 94.

Seg. 2 #2 /4

#3063-|\MT-ei00103 4Q188-I

LLAG

48268j PCFL

LLAG

402B0-IPCFL

DELAY

140309

-IPCFL

AOUT

140348

-|PCFL

00103

-#8020-1 #0020-1 #0032-" #0009J

00103 40242

140260[BLKM#0002-1

|

40278

140280IBLKM

1

40298

140300IBLKM

40330

140340IBLKM

1

40348

148100IBLKM

#0002-1 #0002-1 #0002J #0001-1

n_, n.j..

40100 878 Dec

Figure 94 Simulated Process for PID Control

Simulated ProcessThe process sinulator is comprised of two Lead/Lag PCFL function blocks that actas a filter and input to a delay queue which is also a PCFL function block. This ar-rangement is the equivalent to a second order process with dead time. The solu-tion intervals for the Lead/Lag filters do not affect the process dynamics and werechosen to give fast updates. The solution interval for the Delay Queue is set at1000 Miliseconds with a delay of 5 intervals i.e. five seconds. The Lead/Lag filterseach have a lead term of four seconds and a Lag term of 10 seconds. The gain foreach is 1.0.

In process control terms the transfer function can be expressed as:


(4S+1) (4S+1)e-5S

GpfS) =(10S+1) (10S+1)

The AOUT function block is only used to convert the simulated process outputcontrol value into a range of 0-4095 which simulates a field device. This integersignal is used as the process input in the first network

PID ParametersThe PID controller was tuned to control this process at 20.0 by using the "Ziegler-Nichols" tuning method. The resulting controller gain is 2.16. This is equivalent toa proportional band of 100 / 2.16 = 46.3 %. The Integral time is set at 12.5 sec-onds / repeat, or 4.8 repeats pre minute. The Derivative time was initially 3 sec-onds but was reduced to 0.3 seconds to de-emphasize the derivative effect.

An AOUT PCFL function block is used following the PID block to condition the PIDcontrol output by scaling the signal back to an integer for application as the controlvalue.

The entire control loop is proceeded by a 0.1 second timer. The target solution in-terval for the entire loop is 1 second, and the full solve is 1 second. However, thenon time dependent functions that are used, AIM, LKUP, MODE and AOUT do notneed to be solved evry scan. To reduce the scan time impact of these functions, itis important that they are scheduled to solve less frequently. The example has aloop solve every 3 seconds reducing the average scan time dramatically. It is stillimportant to be aware of the maximum scan impact. When programming otherloops you would not want all of the loops to solve on the same scan.


Index

A LAlarm Block, 36 Lead-Lag Filter Block, 61Analog Input, 41 Limit Block, 64Analog Output, 46 Limit Velocity Block, 67Average Block, 20 Log Ramp Block, 76

Look up Table, 53B Lookup Block, 53

Block Error, 6, 18 Lookup Table, 53Block Parameters, 6Bumpless, 81 M

Manual/Automatic Mode Block, 70C Modicon Customer Service, 97

Calculation Block, 25 Modsoft, 4Control Loop, 88 Modsoft 1.2 Note, 97

D NDeadband, 36, 39, 72 NOp. 32

Delay Block, 49Derivative, 79 ODX Block, 2 On/Off Block, 84DX Zoom, 11 Output Flags, 18

E PE984, 1 PCFL, 2EMTH, 3 PCFL Function Library, 14Engineering Units, 46 PCFL Function List, 7Equation Block, 29 PID, 3

PID Block, 88p PID2/PID Comparison, 91

Floating Point, 3, 12 Power Flow. 22

Force Manual, 84 Process Variable, 88

I QInput Flags, 19 Queue, 49Integrator Block, 57

GM-PCFL-001 Index 115

R Solution Interval, 11,61Ramp Generator Block, 72 Status Register, 18Rate Block, 79 Status Registers, 10Reference Data Display, 23Reference Data Editor, 23 U

Use of Timer, 10, 19s

Select Block, 81 ZSetpoint, 39, 88 Zoom Screen, 22Setpoints, 39

116 Index GM-PCFL-001

pcfl (1)

Documents

calc block description

pid block description

ramp block description

llag block description

integ block description

aout block description

onoff block description

alarm block description