pcb design guidelines for the bluenrg-lp device ......l4 u1 bluenrg-lp pb3 1 pb2 2 pb1 3 pb0 4 pa11...
TRANSCRIPT
![Page 1: PCB design guidelines for the BlueNRG-LP device ......L4 U1 BlueNRG-LP PB3 1 PB2 2 PB1 3 PB0 4 PA11 5 PA10 6 PA9 7 PA8 8 PA0 9 PA1 10 PA2 11 PA3 12 VDD2 13 RF1 14 VDDRF 15 OSCOUT 16](https://reader033.vdocuments.us/reader033/viewer/2022060823/609ce84063eee514947046f2/html5/thumbnails/1.jpg)
IntroductionThe device members of the BlueNRG family are very low power Bluetooth® Low Energy (BLE) devices compliant with Bluetoothspecifications.
The BlueNRG-LP is an ultra-low-power Bluetooth low energy (BLE) 2.4 GHz RF transceiver with a Cortex-M0+ microcontrollercompliant with Bluetooth specification v5.2. The BlueNRG-LP is suitable to implement applications compliant with Bluetooth LowEnergy SIG specifications.
Bluetooth Low Energy technology operates in the same spectrum range (2400 - 2483.5 MHz, ISM band) as classical Bluetoothtechnology, but uses a different set of channels. Bluetooth Low Energy technology has 40 channels (37 data channels + 3advertising channels) of 2 MHz band. Two modulation schemes are defined. The mandatory modulation scheme (1 Msym/s)uses a shaped, binary FM to minimize the transceiver complexity. The symbol rate is 1 Msym/s. An optional modulation scheme(2 Msym/s) is similar but uses a symbol rate of 2 Msym/s. The maximum transmit power is 10 mW (10 dBm).
Further details are given in volume 6 part A of the Bluetooth Core specification v5.2.
The BlueNRG-LP device is provided in three different packages:1. QFN482. WLCSP493. QFN32
ST provides all necessary source files (reference designs) for users that want to speed up their development.
This application note aims to accompany the reference designs of the application boards and provide detailed informationregarding the design decisions adopted within STMicroelectronics designs. In addition, it details the design guidelines todevelop a generic radio frequency application using a BlueNRG-LP device.
The RF performance and the critical maximum peak voltage, spurious and harmonic emission, receiver matching stronglydepend on the PCB layout as well as the selection of the matching network components.
For the optimal performance, STMicroelectronics recommends the use of the PCB layout design hints described in the followingsections. Furthermore, STMicroelectronics strongly suggests to use the BOM defined in the reference design, BOM thatguarantees, with a good PCB design, the correct RF performance.
For further information, visit the STMicroelectronics web site www.st.com.
PCB design guidelines for the BlueNRG-LP device
AN5526
Application note
AN5526 - Rev 2 - September 2020For further information contact your local STMicroelectronics sales office.
www.st.com
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1 Reference schematics
Different application boards have been developed to show the BlueNRG-LP device functionality. The schematicsof the different application boards are reported in the following images and refer to the three different packages.1. QFN482. WLCSP493. QFN32All the layout guidelines described in the following sections have to be applied to all these application boards.
Figure 1. BlueNRG-LP QFN48 application board schematic
C6C7
C14
L3
L1
U1
BlueNRG-LP
PB3
1
PB2
2
PB1
3
PB0
4
PA15
5
PA14
6
PA13
7
PA12
8
PA11
9
PA10
10
PA9
11
PA8
12
PA0 13PA1 14PA2 15PA3 16PA4 17PA5 18PA6 19PA7 20VDD2 21RF1 22VDDRF 23OSCOUT 24
PB448 PB547 PB646 PB745 PB844 PB943 PB1042 PB1141 VDDA40 VDD139 RSTN38 VDD337
VDD
SD36
VLXS
D35
VSS
34
NC
33
VFBS
D32
VCAP
31
PB12
/XTA
L030
PB13
/XTA
L129
PB14
28
PB15
27
VDD
426
OSC
IN25
GND49
C5
C8
C11C10
C16
C3
C9
L2
C1
C15
C2
Q2
XTAL_HS
C12
Q1
XTAL_LS
C4
C13
PB11PB10PB9PB8PB7PB6PB5PB4
PB3
PB2
PB1
PB0
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
PA7PA6PA5PA4PA3PA2PA1PA0
PB14
PB15
RSTN
1.7 V to 3.6 V Power Supply
AN5526Reference schematics
AN5526 - Rev 2 page 2/18
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Figure 2. BlueNRG-LP WLCSP49 application board schematic
C16
C8C10 C9C14
C11
C15
U1
BlueNRG-LP
PA0F6
PA1G6
PA2E5
PA3E4
VSSR
FF3
PA7G5
PA8E7
PA9D7
PA10E6
PA11D3
PA12D6
PA13D5
PA14C7
PA15C6
PB0C5
PB1C4
PB2B7
PB3B6
PB4B5
PB5B4
PB6B3
PB7B2
PB8D4
PB9C3
PB12C2
PB13D2
PB14E2
PB15F2
VDD
2G
7
VDD
3A4
VDD
SDA1
VDD
AA6
VDD
RF
G2
VSSI
OF7
VSSA
A7
VSSS
DB1
VSSI
FAD
CF4
VSSR
FTR
XG
3
VSSI
OA3
VSSS
XG
1
VLXSD A2
RST
NA5
VFBSD C1
VCAP
D1
OSCINF1
OSCOUTE1
RF1 G4
PA4E3
PA5F5
C12
L2
C6
C3
L1
C2
C13
Q1
XTAL_LS
C5
Q2
XTAL_HS
L3
C1
PB1PB0PA15PA14PA13PA12PA11PA10PA9PA8PA7PA5PA4PA3PA2PA1PA0
PB6PB5PB4PB3PB2
PB7
PB15PB14
PB9PB8
RSTN
1.7 V to 3.6 V Power Supply
Figure 3. BlueNRG-LP QFN32 application board schematic
C11
C7
C8
Q1
XTAL_LS
C5
C16
C1
C15
C10
C19
C12
C20
L4
U1
BlueNRG-LP
PB3
1
PB2
2
PB1
3
PB0
4
PA11
5
PA10
6
PA9
7
PA8
8
PA0 9PA1 10PA2 11PA3 12VDD2 13RF1 14VDDRF 15OSCOUT 16
VDD132 PB431 PB530 PB629 PB728 VCAP27 RSTN26 VDDSD25
VLXS
D24
VSS
23
VFBS
D22
PB12
/XTA
L021
PB13
/XTA
L120
PB14
19
PB15
18
OSC
IN17
GND33
C23
Q2
XTAL_HS
C14
L2 L3
PB7PB6PB5
PB3
PB2
PB1
PB0
PA11
PA10
PA9
PA8
PA3PA2PA1
PB14
PB15
RSTN
PB4PA0
1.7 V to 3.6 V Power Supply
Table 1. The BlueNRG-LP application board external component description
Component Description
C1 Decoupling capacitor
C2 32 kHz crystal loading capacitor
C3 32 kHz crystal loading capacitor
C4 Decoupling capacitor
C5 Decoupling capacitor for digital regulator
C6 DC-DC converter output capacitor
AN5526Reference schematics
AN5526 - Rev 2 page 3/18
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Component Description
C7 Decoupling capacitor
C8 Decoupling capacitor
C9 DC-DC converter output inductor
C10 Decoupling capacitor
C11 Decoupling capacitor
C12 RF matching capacitor
C13 Decoupling capacitor
C14 Decoupling capacitor
C15 RF matching capacitor
C16 RF matching capacitor
L1 DC-DC converter output inductor
L2 RF matching inductor
L3 RF matching inductor
Q1 Low speed crystal
Q2 High speed crystal
U1 BlueNRG-LP
U2 Low/band pass filter
AN5526Reference schematics
AN5526 - Rev 2 page 4/18
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2 Two or more layer application board
Different approaches can be taken when an application board is designed:1. Two layer solution2. More layer solution
2.1 Two layer solution
When it is possible to route all the tracks on two layers and a cheaper solution is requested, a two layerapplication board can be designed.
Figure 4. Two layer application board stack-up
The suggested thickness of the board is about 63 mils (800 µm).The two layer board has to be distributed as follows:1. TOP layer: used for RF signal and routing2. BOTTOM layer: used for grounding under the RF zones and for routing in the other partThe two layer solution is indicated for the QFN package.
2.2 More layer solution
When it is not possible to route all the tracks on two layers and/or a cheaper solution is not requested, a morelayer application board can be designed. This is the case, for example, for the WLCSP package where a four ormore layer solution is suggested. See Figure 5. Four layer application board stack-up.
Figure 5. Four layer application board stack-up
The suggested thickness of the board is about 63 mils (800 µm).The four/more layer board has to be distributed as follows:1. TOP layer: used mainly for RF signal and routing2. GROUND layer: used for grounding under the RF zones3. INNER and BOTTOM layers: used to route the low frequency tracks
AN5526Two or more layer application board
AN5526 - Rev 2 page 5/18
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3 QFN package layout recommendations
The application board top layer layout using the BlueNRG-LP QFN48 is shown in the Figure 6. BlueNRG-LPQFN48 application board top layer.
Figure 6. BlueNRG-LP QFN48 application board top layer
It is very important to connect very well the ground of the exposed pad of the QFN48 and QFN32 to the ground ofthe application board. Therefore a lot of vias are necessary to be sure that the parasitic inductor introduced fromeach via is negligible.
Figure 7. QFN48 vias on the exposed pad
AN5526QFN package layout recommendations
AN5526 - Rev 2 page 6/18
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The high speed crystal (Q2) is connected directly to the BlueNRG-LP without external load capacitors. Twoloading capacitors are tunable through a 6-bit word. This is mainly in order to enable fine XTAL frequency tuning.This tuning network is made by a fixed capacitor + 6 binary weighted switchable ones. The effective range ofloading capacitors are programmable through an internal register. The programmable register and the capacitorrange are reported in the BlueNRG-LP datasheet.
Figure 8. QFN48 high speed crystal zone
The low speed crystal is connected directly to the BlueNRG-LP with external load capacitors. The tracks thatconnect the low speed crystal to the BlueNRG-LP are put in a lower layer, the bottom layer, to reduce the couplingwith the RF signal.
Figure 9. QFN48 low speed crystal zone
AN5526QFN package layout recommendations
AN5526 - Rev 2 page 7/18
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The DC-DC converter area is very sensitive and it is necessary to pay attention on the layout of this part. This isbecause the DC-DC converter generates ground noise that can get coupled on surrounding ground reducing thesensitivity and high frequency components that can be coupled onto the RF part.So to ensure a correct layout it is necessary:1. To provide efficient filtering by placing capacitors as close as possible from the BlueNRG-LP2. To reduce parasitic ensuring wide and short connections to BlueNRG-LPIn Figure 10. QFN48 DC-DC converter layout zone the suggested layout is shown:
Figure 10. QFN48 DC-DC converter layout zone
Special care has to be taken in the placement of the supply voltage filtering capacitors. It is, in fact, important toensure efficient filtering placing these capacitors as close as possible from their dedicated pins on the BlueNRG-LP.The TX/RX part of the BlueNRG-LP is very sensitive. A differential to single ended device is integrated into theBlueNRG-LP so no external balun resulting in a BOM reduction. A Π matching network is foreseen on theapplication board if a 50 ohm matching activity is necessary. After the Π matching network an LPF is used to cutthe harmonics of the PA in TX mode.
AN5526QFN package layout recommendations
AN5526 - Rev 2 page 8/18
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Figure 11. QFN48 RF layout zone
AN5526QFN package layout recommendations
AN5526 - Rev 2 page 9/18
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4 CSP package layout recommendations
The layout of CSP package is more complex than that of a QFN. A technology that uses laser via is typically usedto access the internal pads of the device. Laser technology is more expensive than the one that does not useblind as well, so a solution that uses a copper capped via has been used to access the internal pads of the CSPpackage.The application board top layer layout using the BlueNRG-LP is shown in Figure 12. BlueNRG-LP CSP49application board top layer .
Figure 12. BlueNRG-LP CSP49 application board top layer
As for the QFN package, it is very important to connect very well the ground of the CSP49 to the ground of theapplication board. The ground pads are connected to ground with a via directly on the pad itself. Where possiblethe connection to the ground of the TOP layer has been made.
Figure 13. CSP49 package footprint
AN5526CSP package layout recommendations
AN5526 - Rev 2 page 10/18
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The QFN package high speed crystal (Q2) is connected directly to the BlueNRG-LP without external loadcapacitors. Two loading capacitors are tunable through a 6-bit word. This is mainly in order to enable fine XTALfrequency tuning. This tuning network is made by a fixed capacitor + 6 binary weighted switchable ones. Theeffective range of loading capacitors are programmable through an internal register. The programmable registerand the capacitor range are reported in the BlueNRG-LP datasheet.
Figure 14. CSP49 high speed crystal zone
The low speed crystal is connected directly to the BlueNRG-LP with external load capacitors. The tracks thatconnect the low speed crystal to the BlueNRG-LP are put in a lower layer, the bottom layer, to reduce the couplingwith the RF part.
AN5526CSP package layout recommendations
AN5526 - Rev 2 page 11/18
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Figure 15. CSP49 low speed crystal zone
The DC-DC converter area is very sensitive and it is necessary to pay attention to the layout of this part. This isbecause the DC-DC converter generates ground noise that can get coupled on a surrounding ground reducingthe sensitivity and high frequency components that can be coupled onto RF part.So to ensure a correct layout it is necessary:1. To provide efficient filtering by placing capacitors as close as possible to the BlueNRG-LP2. To reduce parasitic ensuring wide and short connections to the BlueNRG-LPIn Figure 16. CSP49 DC-DC converter zone the suggested layout is shown.
AN5526CSP package layout recommendations
AN5526 - Rev 2 page 12/18
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Figure 16. CSP49 DC-DC converter zone
Special care has to be taken in the placement of the supply voltage filtering capacitors. It is, in fact, important toensure efficient filtering placing these capacitors as close as possible to their dedicated pins on the BlueNRG-LP.The TX/RX part of the BlueNRG-LP is very sensitive. A differential to single-ended device is integrated into theBlueNRG-LP so no external balun resulting in a BOM reduction. A complex discrete filtering network is foreseenon the application board to filter the harmonics when the PA is on.
Figure 17. CSP49 discrete filtering network
AN5526CSP package layout recommendations
AN5526 - Rev 2 page 13/18
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5 Reference
[1] BlueNRG-LP Datasheet
AN5526Reference
AN5526 - Rev 2 page 14/18
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Revision history
Table 2. Document revision history
Date Version Changes
24-Jul-2020 1 Initial release.
15-Sep-2020 2 Updated Section Introduction.
AN5526
AN5526 - Rev 2 page 15/18
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Contents
1 Reference schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Two or more layer application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1 Two layer solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 More layer solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 QFN package layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4 CSP package layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
AN5526Contents
AN5526 - Rev 2 page 16/18
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List of figuresFigure 1. BlueNRG-LP QFN48 application board schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Figure 2. BlueNRG-LP WLCSP49 application board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Figure 3. BlueNRG-LP QFN32 application board schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Figure 4. Two layer application board stack-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Figure 5. Four layer application board stack-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Figure 6. BlueNRG-LP QFN48 application board top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 7. QFN48 vias on the exposed pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 8. QFN48 high speed crystal zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 9. QFN48 low speed crystal zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 10. QFN48 DC-DC converter layout zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 11. QFN48 RF layout zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 12. BlueNRG-LP CSP49 application board top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 13. CSP49 package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 14. CSP49 high speed crystal zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 15. CSP49 low speed crystal zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 16. CSP49 DC-DC converter zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 17. CSP49 discrete filtering network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AN5526List of figures
AN5526 - Rev 2 page 17/18
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