pc memory 2 16 by 16 bit reg. file alualu sext 16 i[5:0] i[7:0] 8 6 controller +1 rd1 rd2 wr we out1...
TRANSCRIPT
![Page 1: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/1.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1
P37X Non-Pipelined Datapath - Spring 2006
![Page 2: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/2.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1ALU1: 0000
Names: ______________________________ CSE372 Lab 3, part a
![Page 3: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/3.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1ALU2: 0001
![Page 4: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/4.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1TRAP: 0010
![Page 5: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/5.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1RTT: 0011
![Page 6: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/6.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1JUMP: 0100
![Page 7: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/7.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1JUMPR: 0101
![Page 8: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/8.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1JSR: 0110
![Page 9: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/9.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1JSRR: 0111
![Page 10: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/10.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1BR: 1000
![Page 11: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/11.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1CONST: 1001
![Page 12: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/12.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1INC: 1010
![Page 13: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/13.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1LEA: 1011
![Page 14: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/14.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1LDR: 1100
![Page 15: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/15.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1STR: 1101
![Page 16: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/16.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1LD: 1110
![Page 17: PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0]](https://reader035.vdocuments.us/reader035/viewer/2022062322/5697c0301a28abf838cdab82/html5/thumbnails/17.jpg)
PCMemory
216 by 16 bit
Reg.File
ALU
SEXT
SEXT
16 16
16
16
16
16
16
16
I[5:0]
I[7:0] 8
6
Controller
+1
Rd1
Rd2
Wr
WE
Out1
In
Out2
I
Memory216 by 16 bit
16
WE
ZEXT
16
I[11:0] 12
SEXT
16
I[8:0] 9
InData
Addr
4
16
4
16
16
I[8:6]
3’b111
Zero
16
I[11:9]
I[5:3]
I[11:9]
I[8:6]
I[15:12]
I[11:9]
3
3
3 Out
16
16 16
16
BR Logic
4’b0100
{I[12],I[2:0]} 4
3
16
16
1ST: 1111