parte2_clase03_analog view of digital signals

8/11/2019 Parte2_clase03_Analog View of Digital Signals

1/63

Analog view of digital Signals


2/63

Generalities

Interconnects degrade the quality of digital signal Capacitance: charge and discharge implies reduced

edge speed

Inductance: induced voltages implies offsets reducing

edges speed, non monotonic edges, delays and logiclevel violations

Transmission lines: finite propagation speed impliesdelays and voltage plateaus

Resistance: In short rise/falls times

In long interconnects


3/63

Digital Signal appearance


4/63

Digital Signal appearance

Overshoot/Undershoot: impedance mismatch,

crosstalk, ground and power bounce (package),

and multiple reflections .

Plateaus: usually introduced by longinterconnects adding delay depending on where

the signal is sampled.

monotonic: to prevent double clocking or meta-

stability


5/63

Modeling Frequency contents and Bandwidth

Lumped models: small compared withwavelength at the highest interest frequency

Digital waveforms split in to categories Un-terminated: (TTL, CMOS, etc) usually with

exponential decay

Terminates: (ECL, LVDS, etc) usually trapezoidal


6/63

Trapezoidal Systems with small capacitance and

terminated nets


7/63

Trapezoidal

First roll 2.78/Tw

Second roll 2.78/


8/63

Exponential Edges

Rise and fall depend on

Using the Fourier Transform

Excellent with 4/good with 1/g

Power spectrum, power spectrum envelope

Low pass filter requires BW>=1.4/


9/63

Output of a D Flip-Flop


10/63

Transmission Lines


11/63

Introduction

Any pair of wires and conductors carrying currents in oppositedirections form transmission lines.

Transmission lines are essential components in any electrical/

communication system. They include coaxial cables, two-wire lines,

microstrip lines on printed-circuit-boards (PCB). (Note that at very

high frequencies, any conductor on a PCB must be considered astransmission lines.)

The characteristics of transmission lines can be studied by the

electric and magnetic fields propagating along the line. But in most

practical applications, it is easier to study the voltages and currents

in the line instead.


12/63

Examples


13/63

Fields


14/63

Wave equation


15/63

Voltage/Current Waves


16/63

Voltage and current equations

Relation between instantaneous voltage v and current i at any pointalong the line:

For periodic signals, Fourier analysis can be applied and it is more

convenient to use phasors of voltage V and current I.


17/63


Decoupling the above equations, we get

where is called the propagation constant, and is in generalcomplex.

is the attenuation constant, is the phase constant.


18/63


The general solutions of the

second-order, linear differentialequation for V, I are :

V+, V-, I+, I- are constants (complex phasors). The terms

containing e- z represent waves travelling in +zdirection;

terms containing + z represent waves travelling inz

direction.


19/63

Lossless transmission line

Propagation constant imaginary

Equations in time domain

Phase Velocity


20/63

Some transmission lines


21/63

Some transmission lines

Careful, approximations grossly wrong for some w,h


22/63

RG58


23/63

Transmission lines impedance curves


24/63



25/63



26/63

Driving a line: equivalent circuit


27/63

Transmission point


28/63

Termination: Equivalent circuit

fl d T l h


29/63

Reflections and Telegraphers equation

G l i i li bl


30/63

General transmission line problem

P l i


31/63

Pulse propagation

F Sl d


32/63

Fast an Slow edges

TOF time of flight

For slow rise times, the transmitted wave has sufficient time to reflect off theload and return to the driver before the driver has completed its transition. Theload then modifies the impedance seen by the driver and affects its switchingcharacteristics. In other words, the driver feels the load while it switches. For

this situation to occur, the edge rate must be greater than twice the TOF .

For fast rise times with edge rates less than twice the TOF, the drivercompletes its transition before any of the transmitted wave can reflect from theload and return. During the logic transition, the driver sees only thetransmission lines characteristic impedance. In this situation, the loading doesnot affect the drivers switching behavior.

S r nd P r ll l T rmin ti n


33/63

Source and Parallel Termination

Signaling with fast edges on source

terminated and on source plusparallel terminated transmission

lines; 1ns rise and fall times with

1ns delay: (a) voltage, (b) power.

2C because of symmetry of vcc and gnd transmission lines



34/63


Signaling with slow edges on

source terminated and on source

plus parallel terminated

transmission lines; 4ns rise and fall

times with 1ns delay: (a) voltage,

(b) power.

S T i ti l


35/63

Source Termination only

Without parallel termination at the load, the +1 reflection coefficient at the loadcauses the voltage to essentially double. The large reflected wave travels back tothe driver where it is absorbed by the matched source impedance. Due to thepresence of the reflected waveform, the signal integrity along the transmission lineis not good, but it can be quite good at the load, which is where it matters for apoint to point net.

Unterminated nets are common with both TTL and CMOS to minimize powerdissipation. With good source match, the signal integrity at the load can be quitegood. However, the reflected wave is signficant and can cause difficulties on morecomplex topologies (such as multidrop nets). Also, a bidirectional bus using sourcetermination can be slower because it must wait for the signal to return andterminate in the source impedance before the bus can be turned around intoreceive mode

Nonideal Signaling


36/63

Nonideal Signaling

Switching Incidence

If the first incidence is insufficient, then the voltage must build to a sufficient level totrigger the receiver. The voltage wave reflects off of the receiver, propagates back to the

source, reflects there, and propagates back to the receiver. If the voltage is sufficient at

this second arrival, then the receiver switches, and the signaling is said to be second

incidence. If the signal is again insufficient, then switching may occur at the third

incidence, fourth incidence, and so on. Anything other than first incidence switching

involves a time penalty of two TOFs per incidence.

PC Board Test


37/63

PC Board Test

Discontinuities


38/63

Discontinuities

Capacitive Load The capacitive load introduces a delay

adder of ln 2.

Series inductance the series inductor causes noise by creating areflected pulse and adds delay to the signal due

to edge rate degradation. For the step input, the

reflected pulse voltage peak equals the amplitude

of the step, while the delay adder is ln 2.

For series inductance and shunt capacitance, the frequency-dependent impedance of these discontinuitiescauses frequency-dependent reflection coefficient

Trapezoidal ramp examples


39/63

Trapezoidal ramp examples

Impedance Step The general rule of thumb is to keep all transmission lines at the


40/63

Impedance Step The general rule of thumb is to keep all transmission lines at thesame characteristic impedance; otherwise, reflections are generated

with amplitudes given by the reflection coefficient.

impedance of transmission lines can be essentially constant over very broad bandwidths, so the reflection coefficient can be strongly frequency-independent.


41/63


42/63

Clculo del largo de pistas


43/63

Clculo del largo de pistas

velocidad de propagacin tpica del 66% de la luz: tr:tiempo de trepada de la seal [ns]

tpd:tiempo de propagacin [ns]

lmax:largo mximo de la pista [cm]

Con plano de tierra, utilizando FR-4 se tiene que lalongitud mxima aproximada esta dada por: lmax= 9 x t r

con tiempo de trepadas de 1ns la distancia mxima de una pistaes menor a 10 cm

Terminaciones de lnea:


44/63




45/63


Tipo de terminacin Partesagregadas

Retardo agregado Consumo Valores Comentario

Terminacin resistivaen serie

1 S Bajo Rs= Z0- R0Buen margen de ruido encontinua

Terminacin resistiva

en Paralelo1 Pequeo Alto R= Z

0

El consumo es un problema

Red Thevening 2 Pequeo Alto R= 2 x Z0El consumo en CMOS esun problema

Red RC 2 Pequeo MedioR= Z0C=20~600pF

Verificar ancho de banda y capacidadadicionada

Red con diodo 2 Pequeo Bajo -Limita sobre pico;Algo de rebote en los diodos

Terminacin Serie


46/63

Terminacin Serie

sta alternativa es ptima en los casosdonde slo se tiene una carga al final de la lnea, es

decir, para enlaces punto a punto. Se utiliza siempre y cuando la impedancia R0 de lafuente sea menor que Z0 .Para dimensionar Rs se considera la siguiente condicin:RsZ0- R0

Rs: Resistencia serieZ0: Impedancia caractersticaR0: Resistencia de salida de la fuente

En la actualidad se suele utilizar una resistencia de 33. La utilizacin de la terminacinserie minimiza el rebote.

Terminaciones al final de la lnea


47/63

Terminaciones al final de la lnea

Cuando existen varias cargas

conectadas a una misma lnea omltiples fuentes estn conectadas auna estructura de bus, se utilizanmtodos de terminacin al final de lalnea. La terminacin se debe colocarluego del ltimo dispositivo conectadoa la lnea. Las caractersticas de estatcnica de terminacin son las

siguientes: La seal de inters viaja hacia el final de la

lnea de transmisin sin degradacin en losniveles de tensin y corriente.

La tensin transmitida se absorbe en lacarga

El terminador remueve las reflexiones porser del mismo valor que la impedanciacaracterstica de la lnea, amortiguando

sobrepicos.

Terminacin con resistencia en paralelo


48/63

Terminacin con resistencia en paralelo

Esta terminacin agrega retardo de propagacin al aumentar la constante de

tiempo =RC por el incremento de R en la red.. Una desventajade laterminacin resistiva es el consumo de potencia en continua, dado que se

utilizan valores de entre 50 y 150. En general no se utilizan para familias

TTL o CMOS debido a la gran corriente necesaria para mantener los niveles

lgicos altos, al utilizar una resistencia a tierra o pull-down. En los casos de

lgica ECL la resistencia se conecta a Vcc

Terminacin Thevening


49/63

Te ac T eve g

Este tipo de terminacin es adecuado tanto para lgicas TTL como CMOS. La

resistencia del par RC tiene el valor de la impedancia caracterstica de la lnea al igual

que en la terminacin con resistencia en paralelo. El capacitar frena la tensin continua

por lo que la fuente no debe proveer corriente extra debido a la terminacin cada vezque se establece un nivel en la lnea

Desde el punto de vista de la adaptacin de impedancias todos los mtodos son

equivalentes siendo la alternativa RC la que menos potencia consume. La resistencia es

del valor de la impedancia caracterstica y el valor de la capacidad es muy pequeo, de

entre 20 a 600 pF. La constante de tiempo RC producida por la terminacin debe ser

dos veces mayor al retardo de propagacin de la lnea, en general se eligen valores demanera que la constante de tiempo sea tres veces el retardo de propagacin de la lnea

Terminacin con diodo


50/63

Se utilizan diodos principalmente para evitar los sobrepicos con baja disipacin depotencia. La principal desventaja es la respuesta a seales de alta frecuencia. Cuando

se utilizan diodos rpidos, la velocidad de conmutacin de los mismos debe ser de al

menos 4 veces el tiempo de trepada de la seal

Los diodos no afectan la impedancia por lo que no evitan las reflexiones, por lo que en

general si es necesario reducir o compensar la lnea debe complementarse con otra

tcnica de terminacin. De todas formas en los casos donde se desconoce la impedanciade la lnea es conveniente y sencillo utilizar terminaciones con diodos


51/63

Capacitive Crosstalk


52/63

p

A low-to-high transition on the aggressor line producespositive pulses on the victim line, while a high-to-lowtransition produces negative pulses

at the far end,

At the near far end,

Inductive Crosstalk


53/63

assuming a triangular edge on the aggressor waveform

Total Crosstalk


54/63

Topology


55/63

p gy

Maximum time rate


56/63

Eye Diagrams


57/63

Simultaneous Switching Noise


58/63

SSN


59/63

Time Margin


60/63

Clock Skew


61/63

Spider leg clock distribution network and

d di ib i


62/63

and tree distribution

Low impedance Clock distribution


63/63

parte2_clase03_analog view of digital signals

Documents