part iii the arithmetic/logic unit
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Part III The Arithmetic/Logic Unit. III The Arithmetic/Logic Unit. Overview of computer arithmetic and ALU design: Review representation methods for signed integers Discuss algorithms & hardware for arithmetic ops Consider floating-point representation & arithmetic. - PowerPoint PPT PresentationTRANSCRIPT
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 1
Part IIIThe Arithmetic/Logic Unit
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 2
III The Arithmetic/Logic Unit
Topics in This Part
Chapter 9 Number Representation
Chapter 10 Adders and Simple ALUs
Chapter 11 Multipliers and Dividers
Chapter 12 Floating-Point Arithmetic
Overview of computer arithmetic and ALU design:• Review representation methods for signed integers• Discuss algorithms & hardware for arithmetic ops• Consider floating-point representation & arithmetic
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 3
10 Adders and Simple ALUs Addition is the most important arith operation in computers:
• Even the simplest computers must have an adder• An adder, plus a little extra logic, forms a simple ALU
Topics in This Chapter
10.1 Simple Adders
10.2 Carry Propagation Networks
10.3 Counting and Incrementation
10.4 Design of Fast Adders
10.5 Logic and Shift Operations
10.6 Multifunction ALUs
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 4
10.1 Simple Adders
Figures 10.1/10.2 Binary half-adder (HA) and full-adder (FA).
x y c s 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0
Inputs Outputs
HA
x y
c
s
x y c c s 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1
Inputs Outputs
c out c in
out in x
y
s
FA
Digit-set interpretation:{0, 1} + {0, 1} = {0, 2} + {0, 1}(x + y = c + s)
Digit-set interpretation:{0, 1} + {0, 1} + {0, 1} = {0, 2} + {0, 1}(x + y + cin = cout + s)
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 5
Full-Adder Implementations
Figure10.3 Full adder implemented with two half-adders, by means of two 4-input multiplexers, and as two-level gate network.
(a) FA built of two HAs
(c) Two-level AND-OR FA (b) CMOS mux-based FA
1
0
3
2
HA
HA
1
0
3
2
0
1
x y
x y
x y
s
s s
c out
c out
c out
c in
c in
c in
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 6
Ripple-Carry Adder: Slow But Simple
Figure 10.4 Ripple-carry binary adder with 32-bit inputs and output.
x
s
y
c c
x
s
y
c
x
s
y
c
c out c in
0 0
0
c 0
1 1
1
1 2
31
31
31
31
FA FA FA 32 . . .
Critical path
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 7
10.2 Carry Propagation Networks
Figure 10.5 The main part of an adder is the carry network. The rest is just a set of gates to produce the g and p signals and the sum bits.
Carry network
. . . . . .
x i y i
g p
s
i i
i
c i c i+1
c k 1
c k
c k 2 c 1
c 0
g p 1 1 g p 0 0
g p k 2 k 2 g p i+1 i+1 g p k 1 k 1
c 0 . . . . . .
0 0 0 1 1 0 1 1
annihilated or killed propagated generated (impossible)
Carry is: g i p i
gi = xi yi pi = xi yi
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 8
Ripple-Carry Adder Revisited
Figure 10.6 The carry propagation network of a ripple-carry adder.
. . . c
k 1
c
k c
k 2
c
1
g
p
1
1
g
p
0
0
g
p
k 2
k 2
g
p
k 1
k 1
c
0 c
2
The carry recurrence: ci+1 = gi pi ci
Latency of k-bit adder is roughly 2k gate delays:
1 gate delay for production of p and g signals, plus 2(k – 1) gate delays for carry propagation, plus1 XOR gate delay for generation of the sum bits
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 9
First Carry Speed-Up Method: Carry Skip
Figures 10.7/10.8 A 4-bit section of a ripple-carry network with skip paths and the driving analogy.
c
g
p
4j+1
4j+1
g
p
4j
4j
g
p
4j+2
4j+2
g
p
4j+3
4j+3
c
4j
4j+4
c
4j+3
c
4j+2
c
4j+1
One-way street
Freeway
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10
With this recursive structure, we can do a 2n-bit add in 2(n+1)
logic levels.
Hardwareoverhead is
< 2× regularripple-carry!
Θ(log n)-time Recursive Wired-OR Carry-Skip Adder
(8 bit segment shown)
Pms Gls Pls
CinGCout
P
P
Pms Gls Pls
CinGCout
P
MS LS
LS
Pms Gls Pls
G
Pms Gls Pls
G
P
P
Pms Gls Pls
CinGCout
P
MS LS
MS
Pms Gls Pls
G
Pms Gls Pls
CinGCout
P
LS
GCoutCin
S A B
P
G Cin
S A B
P
GCoutCin
S A B
P
S A B
P
GCoutCin
S A B
P
S A B
P
GCoutCin
S A B
P
S A B
P
G CinG CinG Cin
Cin
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 11
10.3 Counting and Incrementation
Figure 10.9 Schematic diagram of an initializable synchronous counter.
D Q
C _ Q
D
c out
c in
Adder
Update
/ k
k /
a (Increment
amount)
Count register k
/
1
0
Data in
k /
k /
IncrInit
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 12
Circuit for Incrementation by 1
Figure 10.10 Carry propagation network and sum logic for an incrementer.
Substantially simpler than an adder
1
0
k 2
k 1
. . . c
k 1
c
k
c
k 2
c
1
x
x
x
x
c
2
1
0
k 2
k 1
s s s s 2 s
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 13
Carries can be computed directly without propagation
For example, by unrolling the equation for c3, we get:
c3 = g2 p2 c2 = g2 p2 g1 p2 p1 g0 p2 p1 p0 c0
We define “generate” and “propagate” signals for a block extending from bit position a to bit position b as follows:
g[a,b] = gb pb gb–1 pb pb–1 gb–2 . . . pb pb–1 … pa+1 ga
p[a,b] = pb pb–1 . . . pa+1 pa
Combining g and p signals for adjacent blocks:g[h,j] = g[i+1,j] p[i+1,j] g[h,i]
p[h,j] = p[i+1,j] p[h,i]
10.4 Design of Fast Adders
hii+1j
[h, j] = [i + 1, j] ¢ [h, i]
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 14
Second Carry Speed-Up Method: Carry Lookahead
Figure 10.11 Brent-Kung lookahead carry network for an 8-digit adder, along with details of one of the carry operator blocks.
¢ ¢ ¢ ¢
¢ ¢
¢ ¢
¢ ¢ ¢
[7, 7 ] [6, 6 ] [5, 5 ] [4, 4 ] [3, 3 ] [2, 2 ] [1, 1 ] [0, 0 ]
[0, 7 ] [0, 6 ] [0, 5 ] [0, 4 ] [0, 3 ] [0, 2 ] [0, 1 ] [0, 0 ]
[2, 3 ] [4, 5 ]
[6, 7 ]
[4, 7 ] [0, 3 ]
[0, 1 ]
g [0, 0]
g [0, 1]
g [1, 1]
p [0, 0]
p [0, 1]
p [1, 1]
[a,b]=For bitsfrom positionsa through b
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 15
Recursive Structure of Brent-Kung Carry Network
Figure 10.12 Brent-Kung lookahead carry network for an 8-digit adder, with only its top and bottom rows of carry-operators shown.
¢ ¢ ¢ ¢
¢ ¢ ¢
[7, 7] [6, 6] [5, 5] [4, 4] [3, 3] [2, 2] [1, 1] [0, 0]
[0, 7] [0, 6] [0, 5] [0, 4] [0, 3] [0, 2] [0, 1] [0, 0]
4-input Brent-Kung carry network
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 16
Carry-Lookahead Logic with 4-Bit Block
Figure 10.13 Blocks needed in the design of carry-lookahead adders with four-way grouping of bits.
Blo
ck s
ign
al g
en
era
tion
p [i, i+3]
c i
Inte
rme
idte
ca
rrie
s
c i+1 c i+2 c i+3 g [i, i+3]
p i+3 g i+3 p i+2 g i+2 p i+1 g i+1 p i g i
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 17
Third Carry Speed-Up Method: Carry Select
Figure 10.14 Carry-select addition principle.
c out c in Adder
Version 1 of sum bits 1
0
x [a, b ]
c out c in Adder
Version 0 of sum bits
y [a, b]
s [a, b]
c a
0 1
Allows doubling of adder width with a single-mux additional delay
(Carry in to position a)
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 18
10.5 Logic and Shift Operations
Conceptually, shifts can be implemented by multiplexing
Figure 10.15 Multiplexer-based logical shifting unit.
Multiplexer
0 1 2 31 32 33 62 63
5
6
Right’Left Shift amount 0, x[31, 1]
x[31, 0]
00, x[30, 2]
00...0, x[31]
x[31, 0]
x[30, 0], 0
x[1, 0], 00...0
x[0], 00...0
. . . . . .
32
32 32 32 32 32 32 32 32
6-bit code specifying shift direction & amount
Right-shifted values
Left-shifted values
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 19
Arithmetic Shifts
Figure 10.16 The two arithmetic shift instructions of MiniMIPS.
Purpose: Multiplication and division by powers of 2
sra $t0,$s1,2 # $t0 ($s1) right-shifted by 2 srav $t0,$s1,$s0 # $t0 ($s1) right-shifted by ($s0)
1 1
1 1
0 0 0
fn
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0
31 25 20 15 0
ALU instruction
Unused Source register
op rs rt
R rd sh
10 5
Destination register
Shift amount
sra = 3
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
31 25 20 15 0
ALU instruction
Amount register
Source register
op rs rt
R rd sh
10 5 fn
Destination register
Unused srav = 7
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 20
Practical Shifting in Multiple Stages
Figure 10.17 Multistage shifting in a barrel shifter.
2
0, x[31, 1]
x[31, 0]
x[30, 0], 0
32
0 1 2 3
32 32 32 32
0 0 No shift 0 1 Logical left 1 0 Logical right 1 1 Arith right
x[31], x[31, 1]
Multiplexer
2
0 1 2 3 (0 or 4)-bit shift
2
0 1 2 3 (0 or 2)-bit shift
2
0 1 2 3 (0 or 1)-bit shift
(a) Single-bit shifter (b) Shifting by up to 7 bits
y[31, 0]
z[31, 0]
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 21
Figure 10.18 A 4 8 block of a black-and-white image represented as a 32-bit word.
Bit Manipulation via Shifts and Logical Operations
AND with mask to isolate a field: 0000 0000 0000 0000 1111 1100 0000 0000
Right-shift by 10 positions to move field to the right end of word
The result word ranges from 0 to 63, depending on the field pattern
32-pixel (4 8) block of black-and-white image:
1010 0000 0101 1000 0000 0110 0001 0111 Representation as 32-bit word:
Hex equivalent: 0xa0a80617
Row 0 Row 1 Row 2 Row 3
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 22
10.6 Multifunction ALUs
General structure of a simple arithmetic/logic unit.
Logicunit
Arithunit
0
1
Operand 1
Operand 2
Result
Logic fn (AND, OR, . . .)
Arith fn (add, sub, . . .)
Select fn type (logic or arith)
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July 2005 Computer Architecture, The Arithmetic/Logic Unit Slide 23
An ALU for MiniMIPS
Figure 10.19 A multifunction ALU with 8 control signals (2 for function class, 1 arithmetic, 3 shift, 2 logic) specifying the operation.
AddSub
x y
y
x
Adder
c 32
c 0
k /
Shifter
Logic unit
s
Logic function
Amount
5
2
Constant amount
Variable amount
5
5
ConstVar
0
1
0
1
2
3
Function class
2
Shift function
5 LSBs Shifted y
32
32
32
2
c 31
32-input NOR
Ovfl Zero
32
32
MSB
ALU
y
x
s
Shorthand symbol for ALU
Ovfl Zero
Func
Control
0 or 1
AND 00 OR 01
XOR 10 NOR 11
00 Shift 01 Set less 10 Arithmetic 11 Logic
00 No shift 01 Logical left 10 Logical right 11 Arith right