parametric yield
TRANSCRIPT
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1Lecture 2: Parametric Yield
SpanosEE290H F05
Fall 2005 EE290H Tentative Weekly Schedule1. Functional Yield of ICs and DFM. 2. Parametric Yield of ICs.3. Yield Learning and Equipment Utilization.
4. Statistical Estimation and Hypothesis Testing.5. Analysis of Variance.6. Two-level factorials and Fractional factorial Experiments.
7. System Identification. 8. Parameter Estimation.9. Statistical Process Control. Distribution of projects. (week 9)
10. Run-to-run control.11. Real-time control. Quiz on Yield, Modeling and Control (week 12)
12. Off-line metrology - CD-SEM, Ellipsometry, Scatterometry13. In-situ metrology - temperature, reflectometry, spectroscopy
14. The Computer-Integrated Manufacturing Infrastructure
15. Presentations of project results.
ProcessModeling
ProcessControl
IC Yield & Performance
Metrology
ManufacturingEnterprise
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2Lecture 2: Parametric Yield
SpanosEE290H F05
IC Yield and Performance (cont.)• Defect Limited Yield
• Definition and Importance
• Metrology
• Modeling and Simulation
• Design Rules and Redundancy
• Parametric Yield• Parametric Variance and Profit• Metrology and Test Patterns• Modeling and Simulation• Worst Case Files and DFM
• Equipment Utilization• Definition and NTRS Goals
• Measurement and Modeling
• Industrial Data
• General Yield Issues• Yield Learning
• Short loop methods and the promise of in-situ metrology
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3Lecture 2: Parametric Yield
SpanosEE290H F05
IC Structures can be highly Variable
Transistor
Interconnect
Variability will impact performance
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4Lecture 2: Parametric Yield
SpanosEE290H F05
What is Parametric Yield?
• When devices (transistors) do not have the exact size they were designed for,
• when interconnect (wiring) does not have the exact values (Ohms/μm, Farads/μm2, etc.) that the designer expected,
• when various structures (diffused layers, contact holes and vias, etc.) are not exactly right,
• the circuit may work, but• performance (speed, power consumption, gain,
common mode rejection, etc.) will be subject to statistical behavior...
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5Lecture 2: Parametric Yield
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What are the Parametric Yield Issues?
• Binning and Impact on Profitability• The Process and Performance Domains
– Characterizing the Process Domain– Identifying Critical Variables– Modeling Process Variability – Associated (Statistical) Metrology
• Process Variability and the Circuit Designer• Design for Manufacturability Methods• A Global (re)view of Yield
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6Lecture 2: Parametric Yield
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What is the Critical Dimension?
CD
Gate is typically made out of Polysilicon
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7Lecture 2: Parametric Yield
SpanosEE290H F05
Basic CD Economics
(D. Gerold et al, Sematech AEC/APC, Sept 97, Lake Tahoe, NV)
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8Lecture 2: Parametric Yield
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Application of Run-to-Run Control at Motorola
Dosen = Dosen-1 - β (CDn-1 - CDtarget)(D. Gerold et al, Sematech AEC/APC, Sept 97, Lake Tahoe, NV)
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9Lecture 2: Parametric Yield
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CD Improvement at Motorola
σLeff reduced by 60%(D. Gerold et al, Sematech AEC/APC, Sept 97, Lake Tahoe, NV)
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10Lecture 2: Parametric Yield
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Why was this Improvement Important?
600k APC investment, recovered in two days...
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11Lecture 2: Parametric Yield
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Process and Performance Domains• CD is not the only process variable of interest…• Speed is not the only performance of interest…• In general we have a mapping between two multi-
dimensional spaces:
CDResistivitiesConductance of contacts and ViasDielectric capacitance per unit area...
SpeedPower...
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12Lecture 2: Parametric Yield
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So, what to do?
Process
Electrical
Circuit
PerformanceWhat performance is important?What Process/Layout parameters can we change to satisfy critical performance specs?
How to simulate performance variation?How to design a circuit that is immune tovariation?
What electrical parameters matter?How can we set reasonable specs on those?
What process parameters to measure?How to reduce Process Variability?
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13Lecture 2: Parametric Yield
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Translating Specifications between Domains
• Performance Specs, imposed by the market, translate to an “acceptability region” in the process domain.
• This “acceptability region” is also known as the Yield Body (YB).
• The Yield Body can be mapped into either domain.
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14Lecture 2: Parametric Yield
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So what is Parametric Yield?• One is interested in mapping and in maximizing the
overlap between YB and PS.
• This can be accomplished in various ways.• first, we should be able to measure (characterize) the Process
Spread (PS).
• then, one has to figure the mapping from Process to Performance!
• Finally, one needs design tools to manipulate the above.
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15Lecture 2: Parametric Yield
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Parametric Test Patterns
Typically on scribe lanes orin “drop-in” test ICs.E-test measurements:- transistor parameters- CDs- Rs- Rc- small digital and analog
blocks- ring oscillators
SpecialTestIC
IC
IC
IC IC
IC
IC
IC
IC
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16Lecture 2: Parametric Yield
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Parametric Transistor Measurements
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17Lecture 2: Parametric Yield
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There is no agreement about Interconnect Parameters...
An Extraction Method to Determine Interconnect Parasitic Parameters, C-J Chao, S-C Wong, M-J Chen, B-K Liew, IEEE TSM, Vol 11, No 4. Nov 1998.
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18Lecture 2: Parametric Yield
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Interconnect Characterization Structures
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19Lecture 2: Parametric Yield
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Ring Oscillator for Interconnect Characterization
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20Lecture 2: Parametric Yield
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Interconnect Structures are very Complex...
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21Lecture 2: Parametric Yield
SpanosEE290H F05
Statistical Metrology for CDs
Spatial
Random/Deterministic
Within Die
Among Die
Among Wafers
Causal
Equipment Recipe
?Other
Response from Equipment A
Random/Deterministic
Where does variability come from? What are its spatial components?
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22Lecture 2: Parametric Yield
SpanosEE290H F05
Data Collection
• Electrical Measurements facilitate data collection.
• Raw data contains confounded variability components from the entire “short loop”process sequence.
wafer
CD
You can “see” the boundariesof the stepper fields!
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23Lecture 2: Parametric Yield
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Nested Variance – A Simple Model
CDijkl = μ + fi + wj + lk + Ll + σTrue mean
Across-field
Across-wafer
Across-lot
Lot-to-lot
Random
CD variation can be thought of as nested systematic variations about a true mean: Spatial components
Field
Wafer
Lot
Jason Cain, SPIE 2003
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24Lecture 2: Parametric Yield
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Experimental Design
• Use a mask with densely grouped test features to explore spatial variability.
• Electrical linewidth metrology (ELM) chosen as primary metrology due to its high speed.
• A fabrication process based on a standard 248 nm lithography process was used to print test wafers.
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25Lecture 2: Parametric Yield
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Test Mask Design
• Mask design consists of a 22x14 array of test modules
• Module has CD structures (ELM, CD-SEM, OCD) in varying pitch, orientation, and OPC use.
• Density of structures allows detailed variance maps using an “exhaustive” sampling plan.
• Three feature types measured for each module for every field on the wafer (all no-OPC).
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26Lecture 2: Parametric Yield
SpanosEE290H F05
Test Mask Design (cont)
SEMLines
ID: XXNGratingHorz Iso
W/S= 180/1000
GratingVert Iso
W/S= 180/1000
GratingHorz Iso
W/S= 180/360
GratingVert Iso
W/S= 180/360
GratingHorz
MediumW/S = 180/
240
GratingVert MediumW/S = 180/
240
GratingHorz DenseW/S = 180/
180
GratingVert DenseW/S = 180/
180
DUT1Vert
DUT2Vert
DUT3Horz
DUT4Horz VDP
DUT5Horz
DUT6Horz
DUT7Vert
DUT8Vert
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
32
SEMLines
ID: XXO
DUT1Vert
DUT2Vert
DUT3Horz
DUT4Horz VDP
DUT5Horz
DUT6Horz
DUT7Vert
DUT8Vert
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
32
SEMLines
CF_LENS coma/flare
CD_LIN linearity
MEFH
MEF
Probe padsELM CD Patterns
OCD Patterns
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27Lecture 2: Parametric Yield
SpanosEE290H F05
Across-Field Systematic Variation –Mask Errors
Average FieldScaled Mask Errors Non-mask related across-
field systematic variation
Calculate average field to see across-field systematic variation
Use mask measurements to decouple scaled mask errors from non-mask related systematic variation
- =
σ2 = (2.57 nm)2 σ2 = (1.78 nm)2 σ2 = (1.85 nm)2
Scan
Slit
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28Lecture 2: Parametric Yield
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Optimizing Mask Error Scaling Factor for ELM
Mask error scaling factor optimized to minimize residuals when mask errors are removed from average field.
Mask Errors
→ Aerial Image
→ Resist Pattern
→ Trim Etch
→ Poly Etch
→ Electrical Measurement
Electrical MEFMask Error Scaling Factor Optical MEF expected to
be ~1.2
0.7
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29Lecture 2: Parametric Yield
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Across-Field Systematic Variation
Average field with mask errors
removed
Polynomial model of across-field
systematic variation
Residuals
=-
Polynomial model used to capture across-field systematic variation (inferred from examination of data):
CD(Xf,Yf) = aXf2 + bYf
2 + cXf + dYf
σ2 = (1.85 nm)2 σ2 = (1.23 nm)2 σ2 = (1.38 nm)2
Scan
Slit
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30Lecture 2: Parametric Yield
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Across-Wafer Systematic Variation
- -
=
Average Wafer Scaled Mask Errors Across-Field Systematic Variation
Across-Wafer Systematic Variation
Separation of Across-Field and Across-Wafer Systematic Variation:σ2 = (3.28 nm)2 σ2 = (1.77 nm)2 σ2 = (1.23 nm)2
σ2 = (2.46 nm)2
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31Lecture 2: Parametric Yield
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Across-Wafer Systematic Variation
• There is a distinct local drop in CD value in the wafer center, most likely linked to the way the develop fluid is dispensed.
• A bi-variate Gaussian function was fitted to the data to remove this effect.
- =Across-Wafer
Systematic VariationBivariate Gaussian
ModelRemaining Across-Wafer
Systematic Variation
σ2 = (2.46 nm)2 σ2 = (0.52 nm)2 σ2 = (2.39 nm)2
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32Lecture 2: Parametric Yield
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Across-Wafer Systematic Variation
The remaining across-wafer systematic variation was removed using a polynomial model:
CD(Xw,Yw) = aXw2 + bYw
2 + cXw + dYw + eXwYw
- =
Across-Wafer Systematic Variation with bivariate
Gaussian removed
Polynomial Model Remaining Across-Wafer Systematic Variation
σ2 = (2.39 nm)2 σ2 = (1.39 nm)2 σ2 = (1.95 nm)2
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33Lecture 2: Parametric Yield
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Systematic Variation Model Summary• Across-field systematic variation:
– Mask errors (magnified scaling factor) removed– Polynomial terms in X and Y across the field
• Across-wafer systematic variation:– Across-field systematic variation removed– Bivariate Gaussian for spot effect (likely linked to develop effect)– Polynomial terms in X and Y across the wafer
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34Lecture 2: Parametric Yield
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Reduced Sampling Plan Candidates
Plan 1: 920 measurements Plan 2: 900 measurements
Plan 3: 927 measurements Plan 4: 785 measurements
Each plan requires roughly one hour of measurement time (Exhaustive plan had 21,252 measurements, requiring 25 hours)
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35Lecture 2: Parametric Yield
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Comparison of Reduced Sampling Plans
Plan 1 offers the best estimate of across-wafer variation without compromising the quality of the across-field estimate.
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36Lecture 2: Parametric Yield
SpanosEE290H F05
Statistical Metrology for Dielectrics
Rapid Characterization and Modeling of Pattern-Dependent Variation in Chemical-Mechanical PolishingBrian E. Stine, Dennis O. Ouma, Member, IEEE, Rajesh R. Divecha, Member, IEEE, Duane S. Boning, Member, IEEE,James E. Chung, Member, IEEE, Dale L. Hetherington, Member, IEEE, C. Randy Harwood,O. Samuel Nakagawa, and Soo-Young Oh, Member, IEEE, IEEE TSM, VOL. 11, NO. 1, FEBRUARY 1998
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37Lecture 2: Parametric Yield
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Dielectric Thickness vs Position in Field
Studies like this can be used to complement “random”variability with the deterministic, pattern dependent variability.
The combination of the two leads to simulation tools that can predict very well the “spread” of circuit performances.
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38Lecture 2: Parametric Yield
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Impact of Process Variability to Circuit Performance
• Obviously, not everything in the process impacts the Circuit Performance.
• Studies have tried to focus on the most important process parameters.
• CD is clearly one of them.
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39Lecture 2: Parametric Yield
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Impact of Pattern-Dependent Poly-CD Variation
Simulating the Impact of Pattern-Dependent Poly-CD Variation on Circuit Performance, Stine, et al, IEEE TSM, Vol 11, No 4, November 1998
Use basic Optical Model to determine “actual” pattern...
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40Lecture 2: Parametric Yield
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Simulated Performance Variability in 64x8 SRAM Macrocell
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41Lecture 2: Parametric Yield
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Circuit Sensitivity to Interconnect Variation
Circuit Sensitivity to Interconnect Variation, Lin, Spanos and Milor, IEEE TSM, Vol 11, No 4, November 1998
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42Lecture 2: Parametric Yield
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Sample Sensitivities to Interconnect
ILD Thickness
Metal Thickness!
0.8 - 1.2μm
0.2-
0.3n
s0.
2-0.
3ns
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43Lecture 2: Parametric Yield
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Modeling Spatial Matching
• Component Matching is an aspect of process variability that affects the yield of Analog Circuits:– D-A converters: capacitor matching.– Diff amplifiers, current sources: transistor matching.
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44Lecture 2: Parametric Yield
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Circuit Element “Matching” Models• In order to describe matching one needs a “spatial”
distribution.• In this case location, as well as distance are factors that
will affect process (and performance) variability.• Several models have been created, either empirically, or
by taking into account detailed device parameters.
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45Lecture 2: Parametric Yield
SpanosEE290H F05
Pelgrom’s Model
1 2
1A 2A
2B 1B
LW
L
W
L
W
Dx
Dx
Dy
σ2(ΔP) = A2p/WL + S2
pD2x
σ2(ΔP) = A2p/2WL + S2
pD2xD2
y/wafer diameter
Variance inversely proportional to area, proportional to distance2.
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46Lecture 2: Parametric Yield
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Example - Resistance Variance vs. Pattern
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47Lecture 2: Parametric Yield
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Example on Variance in Element Array
1
2
34
5
678910
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48Lecture 2: Parametric Yield
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Example of Variance vs. size, distance
σ2 ΔR/R vs 1/L
σ2 ΔR/R vs D2
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49Lecture 2: Parametric Yield
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Simulating Parametric Yield
• The process domain can be mapped to the performance domain through random exploration.
• The Yield can then be estimated as Y= Np/N.• Though this estimate converges rather slowly, it does have some
nice properties.
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50Lecture 2: Parametric Yield
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Monte Carlo - the speed of Convergence
• Since Y is an estimate of a random variable, bounds for the actual value of Y are given by the general Tchebycheffinequality:
P{|Yest-Y| > kσ} < 1/k2
• Since each random experiment can be seen as a Bernoulli trial with Y probability of success, then if N is large and Y(1-Y)N>6 (or so), we can employ the approximation:
μY = Y
σ2Y=Y(1-Y)/N
• The estimation accuracy is independent of the dimensionality of the process domain.
definitions: Y: actual yield, N: number of Monte Carlo trials, μY, σ2Y are the mean
and variance of the estimated yield Yest.
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51Lecture 2: Parametric Yield
SpanosEE290H F05
An Example - EPROM Sense Amp
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52Lecture 2: Parametric Yield
SpanosEE290H F05
The two Domains for the Sense Amp
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53Lecture 2: Parametric Yield
SpanosEE290H F05
Yield Simulation Example
N = 100, Np = 59Y = 0.59, σ2
y=Y(1-Y)/N = 0.052
Y = 0.59 +/-0.15 => 0.44 < Y < 0.74
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54Lecture 2: Parametric Yield
SpanosEE290H F05
Next Time on Parametric Yield
• Current and Advanced DFM techniques– The role of process simulation (TCAD)– Complete Process Characterization– Worst Case Files– Statistical Design
• The economics of DFM