paralleling of gallium nitride transistors for 48v high
TRANSCRIPT
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Nikola Boskovic, MSc
Prof. ir. Korneel Wijnands
Dr. ir. Maurice Roes
Prof. dr. Elena Lomonova June 14th 2018
Paralleling of Gallium Nitride transistors for
48V high current automotive applications
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Outline
• Introduction
• Motivation
• Approach
• Measurement results
• Conclusion
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Application – Mild hybrid system2
• Specificationso 48 V
o 500 Apeak
• Key performanceso Cost [€/kW]
o Efficiency [%]
battery pack48 V
dc-ac converter
electrical motor
combustion engine
Source: Federalmogul.com
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Power converter topology
• Standard 3-phase 2-level inverter
• No transistors available for high currents (500 A)
• Type of low voltage transistors? Si MOSFET or GaN.
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– solution: PARALLELING
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Gallium Nitride transistors
• Lower losses compared to silicon devices
• Extremely fast switching
• Paralleling GaN transistors?
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Source: EPC white paper
10 V/div
2 ns/div
80 V/ns
GaN transistor(100V, 90A)6,05 mm x 2,3 mm
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• Static current sharing (DC)
• Dynamic current sharing(Transient)
Current sharing5
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Static current sharing
• Steady state
• Resistance RDS(ON)
• Negative feedback
• Self-balancing
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• Transients
• Transistor parameters
• Threshold voltage VGS(th)
• Positive feedback
• Avalanche effect
Dynamic current sharing7
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Dynamic current sharing
• Asymmetric layout – unavoidable when paralleling more then two transistors
o Circuit parameters – mainly parasitic inductances
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Power loopGate loop
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Approach of modelling
• Extraction of the parameters values
• Simulation
• Measurements
• Verifying
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• Wide frequency range
Model of passive components10
Si MOSFET
GaN
Relevant for:
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• Models for needed frequency (GHz) range don’t exist!
11Models
40 Hz 110 MHz55 MHz 110 MHz
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• Five slightly different circuits
• Most important two are:
Boost Converter
Transistor is in BGA package, 0.9 mm x 0.9 mm
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Boost Converter13
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Prototype14
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Measurements15
~1 ns (1 GHz)
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16Conclusions
• Gallium Nitride transistors are beneficial in terms of lower losses.
• Measurement uncertainty – 1 GHz oscillation!
• Impossible to verify parameters.
• Prediction of current for very high number of paralleled transistors.
• Too many uncertainties for the generalized conclusions.
• Different route should be taken.
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Alternative approach
• Paralleling of half bridges by inductances
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Thank you for your attention!
Nikola Boskovic
Electromechanics & Power Electronics (EPE) group