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Session F3: PARALLEL PROCESSING: Array Processors I

Chairman: Fausto Distante Politecnico di Milano Milano (Italy)

Massive computation is required by an increasing number of applications, such as digital signal and image processing, matr ix operations, da ta searching, pat tern recognition, string processing and data base manage- ment. To achieve a considerable throughput, special- purpose architectures with parallel computation capa- bility are often required: array processors and hard- ware accelerators are two examples of present trends in research and development activities.

On the other hand, these recent innovative struc- tures become more and more attractive and cost-effec- tive since suited VLSI and WSI integration technolo- gies are now available at reasonable costs.

Examples of special-purpose architectures present- ing high-computing performances are discussed in this session.

In A veetorized superminieomputer: VAX 11/780 with vector processing, J. Shi-Yao, Z. Shuan and Y. Shi-Sheng discuss an experimental implementation of a new floating-point accelerator with vector processing capabilities for the classic architecture of VAX 11/780. Modification in hardware, firmware, instruction set and software are presented.

The other papers are concerned with array proces- sors. Their basic structure consists in a regular mesh of simple processors connected by an interconnection net- work: functionalities, features and performances of the array depend on the characteristics of the processing elements and interconnection grid. Architectural sup- ports and applications are presented and evaluated.

A. Krikelis and R. Lea have designed and imple- mented a modular, programmable, flexible array pro- cessor, called ASP. In their paper An associative string processor architecture for parallel processing applica- tions, the overall structure of the processing elements and the interconnection are given: implementation de- tails and performances are presented.

M. Maresca proposes in A VLSI implementation of palymorphie-torus architecture a new interconnec- tion network based upon Circuit Switched Connection

Autonomy. This approach allows for realizing dynam- ically different topologies (e.g. bidimensional, pirami- dal, tree-like, or ring structures) but preserving locality of programmable connections. An experimental VLSI implementation is also evaluated.

E.L. Zapata, R. Daollo, F. Rivera and M. Ismail consider the use of array processors in pat tern recogni- tion. In A VLSI systolic architecture for fuzzT cluster- ing, they propose a systolic array for executing a sys- tolic version of the algorithm of fuzzy clustering. The pat tern recognition problem and fuzzy clustering algo- r i thm based upon fuzzy sets are presented: the design of the overall architecture is given and discussed.

S.F. Reddaway and R. Page propose a new array processor (called DAP) for parallel da ta searching in a data base. In High speed data searching with processor array, they present the problem of fast data retrieval in large data bases: the design of their flexible array is treated and its performances are carefully considered.

In many applications the system must be able to survive to faults, even if with degraded performances. This requirement is particularly urgent for mission- critical applications or when repairing and maintenan- ce are too expensive or impossible (e.g. in artificial aerospace satellites). The last two paper of this ses- sion afford the problem of introducing fault-tolerance capabilities in array architectures.

In Fault-tolerant hezayonal arithmetic array pro- cessorn, V. Pinri studies the use of residue arithmetic and A*N+B data coding for achieving error detection and fault localization in a class of array for a wide range of applications involving arithmetic computations.

L. Breveglieri proposes and evaluates the imple- mentation of a VLSI serial multiplier in Design and implementation of a VLSI serial multiplier for fized paint numbers with sell-checking capability. Error de- tection is achieved by means of AN data coding: in particular, 3N code has been considered for its high error detectabili ty with respect to its costs in terms of computational delay and silicon area.