parallel eeprom

8/10/2019 Parallel EEPROM

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Parallel EEPROM Data Protection

Advantages of EEPROMsEEPROMs provide the memory solutionwherever reprogrammable, nonvolatilememory is required. They are easy touse, requiring little or no support hard-ware such as refresh clocks or batteries.Each memory location can be selectivelychanged without impact on any otherlocation; blanket erasure and rewriting of

the entire device or a large section of it isnot required.EEPROMs ma d e a t A t me l we r edesigned to provide the best featuresavailable. Atmel EEPROMs provide highspeed read access times so that manyapplications can use them without insert-ing costly wait states. The page modewrite operation of Atmel EEPROMsallows for the fastest effective write timeavailable in EEPROM memories. Sinceal l of Atmel’s devices are made inCMOS, they offer the benefits of low

operating and standby power.

In order to take advantage of all of thebenefits of Atmel EEPROMs, care mustbe taken to maintain the integrity of thedata. While an EEPROM will retain itsdata for many years with or withoutpower applied, improper operation of thedevice could result in data being inad-vertently rewritten.

When is DataSusceptible to CorruptionIn the use of any memory device, it isexpected that the data stored in it isavailable as it is written. This is espe-cially true of EEPROMs since their codeoften controls the operation of the sys-tem in which they are contained. Unlikemost other memory types that are rewrit-ten in systems, EEPROMs are oftenexpected to retain their data for a periodof many years, with or without powerapplied and during power transitions. Forthese reasons, added attention is givento avoid corrupting data in EEPROMs.

Figure 1. Hardware Data Protection - Power Level Sense Detector and Power OnDelay Timer

ParallelEEPROMs

ApplicationNote

Rev. 0543C–10/98



EEPROMs

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The software data protection feature protects data againstvarious causes of inadvertent writes. Since it is active dur-ing power transitions it protects data when powering on oroff the device. Noise spikes that occur on the control lineswill be ignored since they will not show the correct addressand data needed to start a write cycle. Even for systemmalfunctions, such as when write pulses of adequatelength are given to the device, the software feature canprevent the corruption of the data in the EEPROM. Theaddress locations used for the software code are not sacri-ficed from the usable memory array. The device recognizesthe software code and does not alter the data stored at theaddress locations of the code. Byte locations of code arestill usable, and don’t have to be rewritten.

System Design ConsiderationsDesigning systems with data integrity in mind can greatlyreduce the chance of lost data. The amount of attentionneeded depends upon the nature of the design. Followingare a few areas that might need special attention in certaindesigns.

External Power On ProtectionMany systems will have a PON (power on) signal to controlthe operation of the system. Such a signal can be gatedwith the logic creating the OE signal to the EEPROM, hold-ing OE low when the PON signal is false. Similarly, a PON-type signal could be gated with the WE or CE logic, forcingWE or CE high when writes should not be allowed.If the system does not include a PON-type signal, one canbe created from various programmable voltage referencedevices. With such a device, the user can select the volt-age supply level below which the device cannot be written.It should be noted that in many systems, using Atmel’s

EEPROMS with their internal power level detection andpower delay timer, no additional power on circuitry isrequired for the device.

Multiple Power SuppliesIn systems that utilize more than one power supply, extracare must be taken during power transitions to both theEEPROM and the devices controlling the inputs to theEEPROM. Power on rates of the different supplies arelikely to vary. U sing programmable voltage referencedevices to detect the power level of both supplies and forc-ing the OE pin low when either line is below the desiredlevel may be used in such situations to avoid inadvertentwrites.

Memory CardsSince memory cards are often pushed into and pulled outof systems that are already powered on, they have addi-

tional chances of inadvertent writes. If the edge connectoris arranged such that power and control lines are notasserted in a prescribed manner, false writes to the devicemay occasionally occur depending upon how the card isinserted. To provide proper power on sequencing, a cardcould be designed with its control pins recessed from theedge of the card. Resistors would be placed on the card toconnect CE and WE to V CC and OE to ground. Thisarrangement insures that power is first applied to thedevice and that the control pins are not in the write stateuntil each pin is being controlled by the host system. Varia-tions of this technique may be used effectively in differentsystems; the basic idea is to guarantee systematic applica-

tion of the power and control pins such that a write state isnot entered upon insertion or removal of the card from thehost.

Figure 3. Software Data Protection - Enable



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Figure 4. Software Data Protection - Disable



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© At mel Corp orat io n 19 98 .Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s website. The Company assumes no responsibility forany errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time withoutnotice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atm el’s products arenot authorized for use as critical components in life support devices or systems.

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Terms and product names in this document may be trademarks of others.

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