Parallel Data Acquisition Systems for a Compton Camera

By:

Kıvanç Nurdan, T. Çonka-Nurdan CAESAR / Uni-Siegen

H.J. Besch, B. Freisleben, N.A. Pavel, A.H. Walenta

Uni-Siegen

INTRODUCTION

• Physical Facts- System Considerations- Coincidence timing- Proposed System Parameters

• Proposed DAQ System- Architecture- Implementation

Channel Processor Subsystem Backplane Event Builder Subsystem

• Current Status• Extendibility of the System• Discussion

Compton Camera Principle

Monolithic array of 19 hexagonal SDD’s of 5mm² of each arranged in a honeycomb configuration designed and produced by MPI Semiconductor Laboratory.Integrated on-chip JFET => low noise, excellent energy resolution

Reference: C. Fiorini et al., IEEE NSS 2001 and to be published at Nucl. and Medical Imaging Science, June 2002

Anger Camera:• NaI(Tl) crystal of 10” diameter and of 3/8” thickness

• Read out via 37 x 3” hexagonal PMTs

• Integrated analog readout electronics

System Considerations• Time coincidence

- Any valid Compton event should be detected in both detectors, within 1 ns time difference.

- It can be assumed that they appear at the same time quanta

• Expected Timing Properties- Trigger signal occurs 10-15 ns after an event in

Gamma Camera

- Trigger signal occurs after 0-150 ns in Silicon Drift Detector

PROPOSED SYSTEM PARAMETERS66 Ms/sec 12bit resolution per channel

19 channels from SDD 4 channels from Gamma Detector.

19 triggers from SDD , 1 Trigger from Gamma Detector. ( self triggering)

12 bit data and 5 bit address bus for interfacing channels to coincidence unit

Architecture:

1. Each channel tracks its input continuously and creates trigger with digitally programmable threshold for any reasonable ripple in the signal, finds the peak and integral of the signal in the given time window.

2. Coincidence logic waits for a trigger from Gamma detector then for a trigger from SDD for at most total drift time of the SDD.

3. If and only if one SDD channel creates trigger within this time, this is taken as a true coincidence

Event Reconstruction Mechanism

CHANNEL PROCESSOR SUBSYSTEM

• Conceptional design- Internal digital delay

- Internal trigger generation and external trigger

- Pre trigger delay

- Peak detection

- Integration

- Time stamping

- Raw data for direct inspection

- event output buffer

- System bus interface

ADCAnalogStage Trigger

Unit32 sample Prog.

Pre_trg delay

Peak Event SizeController

256 sample Prog. D. Delay

Integral

Time

MasterController

256 sample output buffer

Buffer1

Semaphore 1Ch 1 Master Cnt.

Bus interface

Buffer N

Semaphore NCh N Master Cnt.

Backplane

Implemented PCBSelected Hardware:

• 65 Msamples/s 12bit ADCs from Analog Devices. AD9235

• Xilinx FPGAs : SpartanIIE• Differential line receivers from Analog Devices.

AD8138• Voltage regulators from National Instruments• Configuration eeprom: ATMEL 17002

Channel 1

Line receiver

ADC 1

FPGA

Conf.Memory

Results:Event 1 Event 2 Event 3 Event 4

1722 1721 1735 16791720 1718 1731 17071719 1717 1730 17401719 1717 1739 17201719 1716 1743 17133431 2911 3445 26672346 3442 2916 34421735 1748 1748 17431724 1729 1744 17321698 1708 1712 17151698 1694 1715 16981714 1708 1731 17041725 1721 1741 17131720 1724 1737 17171699 1710 1720 17091690 1693 1708 16953431 3431 3442 3445 3442

7 29779 7 30377 7 30595 71107 29779 1705 30377 1923 30595 12861831 1831 1831 1831516 540 1056 541 1597 540 2137

8.181 8.19615 8.181

RAWDATA

PEAK

INTEGRAL

TIME STAMP

0

500

1000

1500

2000

2500

3000

3500

4000

45001 32 63 94 125

156

187

218

249

280

311

342

373

404

435

466

497

2MHz Sine Wave

BUS (backplane)

• Clock Distribution- Central-synchronous system clock

• Supports- 44 ( +2) parallel I/O- 3 Serial I/O- 2 Clock lines ( may configured for

differential clocking)

Title

Size Document Number Rev

Date: Sheet of

1.0 1.9

bus data transmission

A3

1 1Friday, April 26, 2002

908.0mV

Vt1.5V

Vcc3.3V

0V

X1

IOpin

INPUT

OUTPUT

Vcc

Vee

Enable

0V

V3

TD = 5ns

TF = .01nsPW = 10nsPER = 20ns

V1 = .6

TR = .01ns

V2 = 3V

Connector Model

904.7mV

CR50.02

Vcc

905.0mV

CC5

2pF

CL56nH

1

2

Vcc Vt

905.0mV

905.0mV

904.0mV

905.0mV

RX8

23

X9

IOpin

INPUT

OUTPUT

Vcc

Vee

Enable

out7

906.0mV

out1

3.300V

RX9

23

LO

SS

Y Tx9

out9

906.0mV

LO

SS

Y Tx8

Vcc

LOSSY

T7_8

905.0mV

0V

LOSSY

T8_9

0V

out8

906.0mV

Vcc

X8

IOpin

INPUT

OUTPUT

Vcc

Vee

Enable

Rt1

50

905.0mV

905.0mV

RX1

23

LO

SS

Y Tx1

CR90.02

Connector Model

Vt

905.0mV

905.0mV

CC9

2pF

CL96nH

1

2

909.2mV

Vt

1.500V

CR70.02

LOSSY

Tt1

30

CC7

2pF

CL76nH

1

2

Connector Model

CR60.02

CC6

2pF

CL66nH

1

2

Connector Model

CR40.02

LOSSY

T1_2

20

CC4

2pF

CL46nH

1

2

600.0mV

Connector Model

LO

SS

Y Tx2

907.3mV

X2

IOpin

INPUT

OUTPUT

Vcc

Vee

Enable

RX2

27

CR30.02

Vcc

0V

CC3

2pF

CL36nH

1

2

Connector Model

CR10.02

CC1

2pF

CL16nH

1

2

Connector Model

908.0mV

908.0mV

908.0mV

out2

908.4mV906.5mV

RX3

23Vcc

0V

LO

SS

Y Tx3

X3

IOpin

INPUT

OUTPUT

Vcc

Vee

Enable3.300V

out3

907.5mV

LOSSY

T2_3

600.0mV

905.7mV

RX4

23Vcc

0V

LO

SS

Y

Tx4906.5mV

X4

IOpin

INPUT

OUTPUT

Vcc

Vee

Enable

out4

906.7mV

To simulate INPUT for xilinx i/o pininput : tied to VccEnable : tied to GND or Veeoutput : connected as signal input

LOSSY

T3_4

RX5

25

0V

Vcc

LO

SS

Y Tx5

906.5mV

X5

IOpin

INPUT

OUTPUT

Vcc

Vee

Enable

out5

LOSSY

T4_5

906.5mV

3.300V

905.0mV

RX6

23Vcc

0V

LO

SS

Y Tx6

X6

IOpin

INPUT

OUTPUT

Vcc

Vee

Enable

out6

906.0mV

LOSSY

T5_6

RX7

23

905.7mV

0V

Vcc

905.7mV

LO

SS

Y Tx7

905.7mV

X7

IOpin

INPUT

OUTPUT

Vcc

Vee

Enable

LOSSY

T6_7

To simulate OUTPUT for xilinx i/o pininput : tied to pulse generator Enable : tied to Vccoutput : connected as signal output

905.0mV

905.0mV

905.0mV

CL26nH

1

2

CR20.02

Connector Model907.3mV

CC2

2pF

907.3mV

907.3mV

CR80.02

905.0mV

CL86nH

1

2

905.0mV

CC8

2pF

Connector Model

905.0mV

905.0mV

Rt2

50

LOSSY

Tt2

Event Builder• Conceptional Design

- An event consists of; X Y E1 E2 SDD pixel

- Each element has a time stamp, an integral and a peak value.

- ~8M detector events per second bus data transfer throughput.

- .7M Compton events ( depending on integration time) may be reconstructed.

- 10K compton events are expected for the prototype system

Gamma Detector

Silicon Detector

Coincidence Algorithm1. Wait for a trigger from Gamma Detector

2. Trigger received from Gamma Detector,

a) If one and only one channel from Silicon detector triggers within a max drift time, this coincidence is considered as an event candidate. GOTO 3

b) Else GOTO 1.

3. If within total integration and accumulation time;

a) no other triggers received, accept this coincidence as an event, and push its data to output buffers

b) Else purge data

4. GOTO 1

Slave controllers

DATA

BUSBUS

MASTERABS_REG

SCAT_REGS

ProgrammableSystem

ControllerPC

Interface

SRAMController

SRAM

CoincidenceLogic

TimeStamps

Parallel portinterface

FPGA

18x1 Mbit133MHzSSRAM

PC interface

• Simple parallel port interface (implemented)8 Mbits/sec

• Ethernet interface ?100 Mbits/sec

• IEEE 1394 interface ?400 Mbits/sec

• USB 2.0 interface ?480 Mbits/sec

Support DAQ Software

Current StatusA concept has been developed for the whole Data Acquisition System of the Compton Camera.

Analog Interface and digital electronics developed and tested for the Channel Processor module.

Electrical characteristics for bus architecture has been finalized and Backplane Module has been fabricated .

Event builder module has been electrically characterized. Bus implementation in VHDL code is ongoing.

Initial PC interface over parallel port for a single Channel Processor module has been built and DAQ software has been written to transfer data to PC.

A Possible Parallel DAQ System for a Future Compton Camera

COMPTON CAMERA TRIGGERING DAQ SYSTEM

Trigger FlowScatter detector module Absorption Detector Module

Detector

Time Coincidence

L0 Trigger

L0 Trigger Manager

L0 Trigger

L1 Trigger

Fast

Slow

Buffer Manager

L1 Buffer L1 Buffer

BufferManager

Fast

Fast

Detector

Event Builder

Data Bus Data Bus

L0 Buffer

Derandomized Event Buffer

ReadoutUnit

L0 DepthManager

Command Bus Command Bus

L0 Buffer

Further Discussion

• Deadtime of such a system ?• How fast we can go ?• Extensible ? How far ?• Support Software ? Balance between programmable firmware and computer software ?

References & Acknowledgements

Dipl. Ing. M. Adamek (SiemensVDO A.G) (general design) Dipl. Ing. Alan Rudge (CERN) (low noise electronics)

An Innovative Distributed Termination Scheme for GTL Backplane Bus Designs, High-Performance System Design Conference 1998

Application Report SCEA022 Texas Instruments- April 2001

Application Report SLLA067 Texas Instruments- March 2000

EIA/JESD8-8, Stub Series Terminated Logic for 3.3 V (SSTL_3)

EIA/JESD8-9, Stub Series Terminated Logic for 2.5 V (SSTL_2)

High-Speed Digital Design, H. W. Johnson, M. Graham, 1993