paper 5 : sensorless optimization of dead times in dc-dc converters with synchronous rectifiers

994 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 4, JULY 2006

Sensorless Optimization of Dead Times in DC–DCConverters With Synchronous RectifiersVahid Yousefzadeh, Student Member, IEEE, and Dragan Maksimovic, Member, IEEE

Abstract—This paper introduces an approach to achieve op-timum dead times in dc–dc converters with synchronous rectifierswithout sensing any of the power-stage signals other than theoutput voltage. The dead times are adjusted adaptively to mini-mize the duty-cycle command, which results in maximization ofthe converter efficiency. The method is particularly well suited fordigital controller implementation, requiring no additional analogcomponents or modifications of standard gate-drive circuitry.Experimental results for a digitally controlled 5 V-to-1 V, 5-A syn-chronous buck converter demonstrate practical implementationof the sensorless dead-time optimization algorithm.

Index Terms—DC–DC converter, dead time, synchronous recti-fier, sensorless.

I. INTRODUCTION

BECAUSE of significantly lower conduction losses,synchronous rectifiers are now used in essentially all

low-voltage dc power supplies including converters forbattery-operated electronics, point-of-load converters, micro-processor power supplies, etc. As an example, Fig. 1 shows asynchronous buck dc–dc converter, and Fig. 2 shows typicalexperimental waveforms. It is well known that optimum utiliza-tion of a synchronous rectifier depends on the ability to adjustthe commutation dead-times and . Too long dead times(as shown in Fig. 2) result in additional losses due to the bodydiode conduction and the body-diode reverse recovery.

Too short (or negative) dead-times may result in simultaneousconduction of the main switch and the synchronous recti-fier , with even more adverse penalties in the converter effi-ciency. Various gate-drive schemes have been proposed to ad-dress the synchronous rectifier commutation. In the presenceof parameter tolerances, temperature variations and operatingpoint changes, the simplest approach of fixed dead times oftenyields severely degraded efficiency, especially in converters op-erating at relatively high switching frequencies (in the hundredsof kHz to MHz range) [1].

Previously proposed schemes for improved synchronous rec-tifier commutation have been based on the idea that the syn-chronous rectifier should switch as an ideal rectifier: it shouldbe turned on exactly at the time when the voltage across it dropsto zero, and it should be turned off exactly at the time whenthe current through it drops to zero [2]. Direct implementation

Manuscript received January 14, 2005; revised September 15, 2005. Thiswork was supported by Toshiba through the Colorado Power Electronics Center.Recommended by Associate Editor B. Lehman.

V. Yousefzadeh is with the Colorado Power Electronics Center, Electricaland Computer Engineering Department, University of Colorado, Boulder, CO80309 USA (e-mail: [email protected]; [email protected]).

Digital Object Identifier 10.1109/TPEL.2006.876850

Fig. 1. Synchronous buck converter proof-of-concept prototype: V = 5 V,V = 1 V, 0< I <5 A, L = 4.3 �H, C = 705 �F, f = 200 kHz,MOSFETs: Si4888DY.

Fig. 2. Experimental waveforms for I = 2.5 A; the dead times are too long.

of this idea requires sensing the zero-crossing of the voltageacross the synchronous rectifier, and sensing the threshold-

crossing of the gate-drive voltage, which is indicative of theswitch turn-on (or the switch turn-off) instant. In “adaptive”gate-drive schemes, fast comparators attempt to match the zero-crossing and the threshold-crossing instants in each switchingcycle, which in practice results in suboptimal performance be-cause of the comparator delays and sensitivity to parameter andtemperature variations.

Better results have been reported with schemes based on the“predictive” gate drive technique [1], or with delay-locked loops[3]–[5]. These techniques can reduce the dependence on very

0885-8993/$20.00 © 2006 IEEE

YOUSEFZADEH AND MAKSIMOVIC: SENSORLESS OPTIMIZATION OF DEAD TIMES IN DC–DC CONVERTERS 995

fast comparators and the sensitivity to parameter or tempera-ture variations. They are still dependent on sensing the noisyswitch voltage , and on the ability to accurately detect turn-onand turn-off instants, which can be difficult, especially if thegate drivers and the power MOSFETs are not integrated on thesame die. Furthermore, such dead-time optimization schemesare available only with more complex, specialized gate drivers.

In this paper, we introduce an entirely different approach tooptimum synchronous rectifier commutation, which does notrely on sensing the switch node voltage or any other signal inthe power stage other than the output voltage (which is per-formed for the purpose of output voltage regulation anyway).The proposed method, which is based on the idea of optimizingthe efficiency by minimizing the steady-state duty-cycle com-mand, is equally well suited for converters with discrete powerMOSFETs and conventional (separate) gate drivers, and for con-verters based on power MOSFETs with integrated gate drivers.The method is particularly well suited for digital controller im-plementation, requiring relatively small additional digital logicresources; no additional analog components or modifications ofthe standard gate-drive circuitry are needed.

Section II introduces the concept of sensorless dead-time op-timization. Section III presents an experimental digitally con-trolled 5 V-to-1 V, 5-A synchronous buck converter, which isused to demonstrate practical realization of the proposed sensor-less dead-time optimization method. A dead-time optimizationalgorithm and its implementation in the experimental prototypeare described in Section IV. Dynamic operation of the optimiza-tion algorithm is addressed in Section V.

II. SENSORLESS OPTIMIZATION OF DEAD TIMES

Let us consider the objective of maximizing the converter ef-ficiency as a function of the dead times and ,subject to the precise output dc voltage regulation requirement,

(1)

Direct on-line maximization of , although possiblein principle [6]–[8], would require sensing or computation ofthe input power or the losses, which is more difficult to accom-plish in practice. Our approach is instead based on the observa-tion that, for a given load and subject to the precise output dcvoltage regulation, the optimum dead-times that result in effi-ciency optimization (1) simultaneously result in the minimumswitch duty-cycle command

(2)

Since the duty cycle command value is already available inthe controller without any additional sensing, finding the op-timum dead times from (2) leads to a sensorless approach tooptimization of the converter efficiency.

The concept is further explained through the switch and gate-drive waveforms shown in Fig. 3. Suppose, for example, that the

Fig. 3. Switch node voltage v (t) and gate-drive waveforms for (a) optimumdead time, (b) too long dead times, and (c) too short dead times; duty cycle Dmust be increased (“+” areas) to compensate for the loss (“�” areas) in theaverage voltage hv i due to non-optimum commutation, in order to maintainthe average switch voltage constant.

dead-time is too long [as shown in Fig. 3(b)]. As a result,the body diode conducts, which adds a subinterval of negativevoltage to the waveform. This tends to reduce the averageswitch voltage . However, since the output voltage is pre-cisely regulated, , this means that (for a given loadcurrent) the duty cycle command must be increased to com-pensate for the loss of the average switch voltage. In the case oftoo long dead-time in Fig. 3(b), the loss in the average value ofthe switch node voltage, is

(3)

where is the switching period, and is the body diodevoltage drop. Similarly, for a too short dead-time, a part of thepositive portion of the switch node voltage is lost dueto the overlap between the two gate drive signals. Therefore,

is decreased and the duty cycle command is increased.In Fig. 3(c), the loss in the average value of the switch nodevoltage, in the case of too short dead-time is

(4)

which is usually even larger than the loss (3) due to the bodydiode conduction. and are the on-resistances of thetwo switches, and . It should be noted that the result (4)


Fig. 4. Measured efficiency � and duty-cycle command D as functions of thedead-time t in the experimental prototype.

can be significantly affected by parasitic inductances in the cir-cuit. A more detailed analysis is given in Section IV-B.

In any case of non-optimum commutation, the duty cyclecommand must be increased to compensate for the loss in theaverage switch voltage The optimum commutation, i.e., theoptimum values of the dead-times, are therefore indeed obtainedwhen the switch duty-cycle command attains the minimumpossible value. It is important to observe that this concept worksunder the assumption of precise dc output voltage regulation:the sensing needed to distinguish optimum versus non-optimumswitch commutation is in fact performed by the output voltagesensing followed by the large dc gain of the compensator, bothof which are already implemented in a closed-loop dc voltageregulator.

As an example, Fig. 4 shows the measured converter effi-ciency and the duty cycle command as functions of thedead time . In this measurement the dead-time is fixedto the value of 150 ns. It can be observed that the max-imum of coincides with the minimum of . In the digitallycontrolled proof-of-concept prototype, the zero-error bin of theA/D converter is 20 mV (2% of the nominal output voltage), andthe digital controller is implemented on an FPGA, which limitsthe switching frequency to 200 KHz. The practical limitationscontribute to the relatively shallow maximum of the efficiency

and minimum of the duty cycle in the experimental resultsshown in Fig. 4. At higher switching frequencies, the efficiencyexhibits proportionally stronger dependence on the dead times,and optimum commutation is increasingly important [1]. Wenote that a more precise output voltage regulation (e.g., 1% orbetter) directly results in improved sensitivity and performanceof the proposed method, i.e., in the ability to approach the actualoptimum efficiency by minimizing the switch duty cycle com-mand. This point is discussed in more detail in Section IV.

III. EXPERIMENTAL PROTOTYPE

The experimental circuit used to test the digital dead-time op-timization algorithm is shown in Fig. 5. The converter has theinput voltage of 5 V, and the output voltage of 1 V.The filter elements are 4.3 H, 705 F, the switchingfrequency is 200 kHz and the load current is

Fig. 5. Experimental prototype.

0–5 A. The digital controller is implemented on an FPGA con-trol board, which includes a Xilinx Virtex II (XC2V1000) chip.

The output voltage is sensed through a windowed A/D con-verter and is regulated at 1 V. The A/D converter is basedon the two comparator (three-error bin) architecture [9], [10],with the zero-error bin width of 20 mV. The error signal atthe output of the A/D is processed by a PID compensator, whichprovides the necessary duty-cycle command for the outputvoltage regulation. Following the approach presented in [9], aPID compensator is designed so that the loop gain of the systemhas a crossover frequency of 10 kHz and the phase marginof more than 75 at the load of 2.5 A. The duty-cycle command

at the output of the PID compensator is then low-pass filtered[by the filter ] to compute the average, steady-state value

of the duty-cycle command, as required in the dead-time op-timization method introduced in Section II. The algorithm fordead-time optimization, which takes the values of and asthe inputs, is described in detail in Section IV.

Realizations of the low pass filter and the digital pulse-width modulator (DPWM) are discussed next.

A. Low-Pass Filter LP

The purpose of the low-pass filter is to compute the averagevalue of the duty-cycle command . In the experimental proto-type, a moving-average filter performs this function

(5)

The -transform of (5) gives the filter transfer function

(6)

For small value of the pole at 1 is close to one, whichcorresponds to a low-frequency pole. By rearranging (5), thevalue of can be found from

(7)

Choosing to be 1/2 , where is a positive integer value, themultiplication in (7) can be performed simply by a shift opera-


Fig. 6. Load transient simulation. Inductor current i , duty cycle command d,average value of the duty cycle command D, output voltage v .

tion. In our experiment, the value of is chosen to be 7. Itis interesting to note that this type of moving-average filteringto compute the steady-state duty cycle can find applicationinside the control loop in the digital current-mode controller ar-chitecture described in [11].

The converter, the PID compensator, and the moving-averagefilter were modeled in the Matlab/Simulink environment. Sim-ulation waveforms for a step load change from 4.5 to 2.3 A areshown in Fig. 6. It can be observed that the averaging filter elim-inates the abrupt changes in the duty-cycle and provides asmooth transition of the average duty-cycle command . Therelatively high value of the overshoot (120 mV or 10%) at theoutput voltage is a result of the low number of error bins (threeerror bins) for the A/D converter. When the output voltage goesoutside of the zero error bin, the “gain” of the A/D converterdecreases significantly, and the compensator operates as a rel-atively slow integral compensator. In this paper, only the zero-error bin for precision dc voltage regulation was important. Alarger number of error bins in the A/D converter would yield abetter load transient performance.

B. DPWM Operation

The digital pulsewidth modulator (DPWM) in the controllerof Fig. 5 has three inputs: the duty cycle command , the deadtime command and the dead time command , and two out-puts: the control signals and for the main switch and thesynchronous rectifier , respectively. A simple counter-basedapproach has been applied to construct the DPWM in the FPGArealization. A 9-b counter clocked at 100 MHz gives the outputpulses with 9-b (10 ns) resolution at the switching frequencyof 200 KHz. The operation of the DPWM is illustrated by thewaveforms shown in Fig. 7. At the beginning of each switchingcycle, corresponding to the zero-crossing of the 9-b counter, the

Fig. 7. Operation of the digital pulse width modulator (DPWM) block.

Fig. 8. Dead-time optimization algorithm.

gate signal is set. At the time that the value of the 9-b counterequals to the value of the duty cycle command , the signalis reset. Therefore the signal applied to the main (high-side)switch is unaffected by the dead-time commands. The dead-time commands and are applied to the gate signalthat controls the synchronous rectifier . As shown in Fig. 7,the signal is set when the value of the 9-b counter equalsto , and is reset when it equals to 1 . It should benoted that the DPWM block in the FPGA is constructed in sucha way that the dead-time commands can be positive or negativevalues. The values of the dead-time commands and arefound in the optimization algorithm, which is described in thenext section.

IV. OPTIMIZATION ALGORITHM

Based on the concept introduced in Section II, on-line effi-ciency optimization can be performed simply by searching forthe dead times that minimize the steady-state duty cycle com-mand , as shown in (2). The algorithm, performed in ourFPGA-based digital controller, is illustrated by the flowchart ofFig. 8. We assume that the load and the input voltage are con-stant during the execution of the dead-time search. Dynamic op-eration of the algorithm is addressed in Section V.

The algorithm starts by a trigger signal. Starting from a safe,sufficiently long maximum dead time , the dead time isdecreased in small steps of . After each change of the dead-time, the algorithm waits for a certain number of switchingcycles, and then compares the current steady state value of the


duty cycle with the previous one. The wait block ensures that thesystem has reached a new steady state in each step of the search.Decreasing the dead-time continues until an increase in theduty cycle command is detected. Then, the dead-time searchstops and provides the final optimum dead-time commands tothe DPWM. In our prototype, the same dead-time search algo-rithm is performed for first, and then for .

There are two issues that should be discussed in more detail:the precision of the dead time algorithm with respect to the trueoptimum efficiency, and the selection of the final value of theoptimum dead-time.

A. Precision of Efficiency Optimization

The compensator takes the action for correcting the duty cyclewhen the output voltage goes out of regulation and producesan error signal in the input of the controller. In a digitally con-trolled converter, no error will be generated as long as the outputvoltage stays inside the zero-error bin of the A/D converter, andthe duty cycle command stays the same. One small step changeof the dead-time may not be sufficient to bring the output voltageoutside of the zero-error bin. Consider the case when the deadtime is larger than the optimum value so that the body diode ofthe synchronous rectifier conducts during the switch commu-tation. To observe a change in the output voltage, a minimumchange in the dead time of approximately

(8)

is necessary, where is the width of the zero-error bin of theA/D converter that senses the output voltage, is the voltagedrop across the synchronous rectifier body diode, and is theswitching frequency. As the dead-time optimization algorithmdecreases the dead-time in small steps , the outputvoltage increases gradually, until the output voltage goes outsideof the zero-error bin, which produces an error signal at the inputof the compensator and the compensator decreases the duty-cycle command. As shown in the flowchart of Fig. 8, decreasingthe dead-time continues as long as the current steady-state dutycycle is less than or equal to the previous value. Given thequantization of the dead-time command, and the quantizationof the output voltage, it is of interest to find how precise theoptimization algorithm is, i.e., to find the efficiency tolerance

with respect to the true optimum efficiency. From

(9)

we have

(10)

where is the load current. By substituting (8) into (10) we find

(11)

Fig. 9. Experimental waveforms showing the case of slight overlap in conduc-tion of the switchesQ andQ when t is too short. The waveform v (channel1) is 20-MHz band-width limited, to show the dc portion of the ringing.

which shows that the optimum efficiency is found with atolerance that depends on the precision of the output voltageregulation.

B. Optimum Dead Time Selection

The dead-time command value, for which a decrease in theaverage duty cycle command is observed, is stored as the es-timate of the optimum dead time . When an increase in theaverage duty cycle command is observed, the algorithm stopsand assigns the last stored as the optimum dead-time com-mand. The reasoning behind this selection of the final optimumdead time is related to practical operation of the converter witha slight overlap in conduction between the switches and .When the dead-time is too short, the switch node voltage differsfrom the idealized waveforms shown in Fig. 3 because of para-sitic inductances in the loop with the switches and . Sup-pose that there is a slight overlap in conduction of the switches.A “shoot-through” current goes through the two switches anda small parasitic inductance in series with the switches. Oncea switch is turned off, the energy stored in the parasitic induc-tance is released in a ringing waveform across the switch nodeparasitic capacitance. This release of energy from the parasiticinductance appears as an increase in the average value of theswitch node voltage, as illustrated by the experimental wave-forms in Fig. 9. This additional voltage component due to therelease of the energy stored in the parasitic inductance in serieswith the switches tends to compensate for the reduction in theaverage switch node voltage caused by the slight overlap in con-duction. In fact, if the additional voltage component were largerthan the loss in the average voltage during the overlap, the algo-rithm would fail, stopping at a lower-efficiency point that corre-sponds to an overlap in conduction. In the analysis that follows,we show that even when parasitic inductances have significantvalues, an overlap in conduction necessarily results in a net lossof the average switch voltage. As a result, the algorithm shownin Fig. 8 stops at a point where the efficiency is close to the op-timum value, safely away from the switch cross-conduction.

Consider the case of a too short , i.e., the case of an overlapin conduction of the switches and . Let the length of theoverlap be equal to . Fig. 10 shows a simplified model of


Fig. 10. Circuit model of the synchronous Buck converter (a) during theoverlap time t and (b) the switch Q is turned off.

Fig. 11. Switch node voltage v (t), waveform and the gate drive signals vand v .

the converter circuit during (a) the overlap time and (b)immediately after the switch turns off.

In Fig. 10, and are the parasitic series inductances,and are the on-resistances of the two switches and

is the parasitic output capacitance of the switch . Forsimplicity, the output filter inductor is replaced by a constantcurrent source . The circuit analysis is simplified by assumingthat , which represents theworst case of relatively large parasitic inductances.

During the cross-conduction overlap the current buildsup through the series connection of the switch on resistancesand the parasitic inductances. The switch-node voltageis significantly reduced compared the ideal , asshown in Fig. 11 waveform. By solving the circuit in Fig. 10(a),and integrating the voltage during , we obtain an

upper bound for the net contribution to the average switch-nodevoltage during the overlap

(12)

and initial values of the inductor currents at the time when theswitch is turned off. In the circuit of Fig. 10(b), the energystored in the parasitic inductors is dissipated in the resonant cir-cuit formed by and . An upper bound for thenet increase in the average switch-node voltage compared tothe case of zero overlap is obtained by solving the circuit inFig. 10(b), and integrating over the time long enough forthe ringing to subside

(13)

From (12) and (13), the cross-conduction overlap resultsin the total voltage added to the averageswitch-node voltage

(14)

The result, (14), shows that the overlap, even in the worst caseof relatively large parasitic inductances, results in a net negativecontribution to the average switch-node voltage . However,as a result of , (14) also shows that larger parasitic in-ductances result in a slower decrease in the averageswitch-node voltage. As a result, the duty cycle command asa function of the dead time has a shallower minimum comparedto the efficiency, which exhibits a sharp drop when the overlap inconduction occurs. To mitigate this problem, the converter cir-cuit should be designed with the parasitic inductances as smallas possible, which is a very common practice for a number ofother reasons.

The optimization algorithm (as shown in Fig. 8) approachesthe optimum dead time starting from a safe value , andstops at the last point where a decrease in the duty cycleis observed. As a result, even if the parasitic inductances haverelatively large values, the algorithm results in the dead timesaway from the overlap conduction of the switches, and achievesefficiency close to the true optimum.

Fig. 12 shows experimental digital data collected from theFPGA digital controller during the operation of the optimizationalgorithm of Fig. 8. The figure shows the optimization search forthe dead-time commands and and the resulting changesin the average duty cycle command . The algorithm starts fromthe safe dead-time values typical for constant dead-time realiza-tions: 200 ns and 220 ns. The efficiency ofthe converter at this operating point is 88%.

The system is triggered before time 0. At the point “a,” thedead-time search algorithm for starts decreasing the valueof with a step change of 10 ns. At the points wherethe steady state duty cycle is decreased, the value of isstored in the register. At the point “c” the dead-time istoo short, which results in a decrease of the average value ofthe switch node voltage. As a result, the compensator increases


Fig. 12. Experimental digital data collected from the FPGA digital controllerfor the values of t ; t commands, and the average duty cycle command D.The data were collected by the Xilinx “Chipscope,” which functions as a logicanalyzer module embedded on the FPGA.

the value of the duty cycle command. This increase is shown inthe point “c” of Fig. 12. At this time, the search algorithm for

stops, and sets the last stored value of as the optimumdead-time command for . After that, the search algorithm for

is triggered automatically, and the optimization searchproceeds as shown in Fig. 12. The total time for the dead-timesearch (starting from a long initial value of ) is 43 ms.The dead-time values found by the optimization algorithm are

70 ns and 130 ns. The converter efficiency atthe end of the dead-time search is 92%.

Fig. 13 shows the experimental converter waveforms (a) be-fore the optimization and (b) after the optimization. In the ex-perimental prototype shown in Fig. 5, 10 ns, which isa limitation of the FPGA. With digital PWM controllers ICs,operation in the MHz range with subnanosecond resolution forthe duty cycle and for the dead times and can be readilyachieved [12].

V. DYNAMIC OPERATION

In this section, we discuss several options for triggering theoptimization algorithm of Section IV. In principle, the completeoptimization that starts from sufficiently long, safe dead timesshould be performed upon power up or reset of the converter.In normal operation, there are several options of triggering theoptimization. For example, the optimization can be performedperiodically, starting from the previously determined optimumvalues for the dead-time commands. Another option is to uti-lize the flexibility of the digital controller implementation andtrigger the optimization algorithm only when a change in theoperating condition is detected. An implementation of this op-tion is described in this section.

A transient in the duty cycle command can be used as anindication of a change in the operating conditions. A differencebetween the duty cycle command and its average valueindicates that a transient occurs. The corresponding logic signaltrans is generated as follows:

(15)

Fig. 13. Experimental waveforms (a) before optimization, efficiency is 87.3%and (b) after optimization, efficiency is 92.4%.

TABLE ISUMMARY OF OPTIMIZATION ALGORITHM AND

TRANSIENT DETECTION PARAMETERS

To avoid triggering the dead-time optimization algorithmupon relatively small changes in operating conditions, activa-tion of the signal trans according to (15) can be delayed by ashort interval from the time a difference between andoccurs. Once the trans signal is activated, the dead-timesand are increased to the safe values, and ,respectively. After the converter reaches a new steady-stateoperating point , the signal trans is deactivated, whichtriggers the optimization algorithm.

Table I summarizes the definitions of the optimizationalgorithm and transient detection parameters. Thevalues are chosen as in constant dead-time realizations: toensure non-overlapping switch commutation under worst-casecombination of gate-drive delays and operating conditions.In the experimental prototype switching at 200 KHz,


Fig. 14. Experimental waveforms during a step load transient. The signal transindicates the interval when the duty cycle command d differs from the averageduty cycle command D.

we have 200 ns and 220 ns. Thediscrete-time moving-average low-pass filter LP in (6)computes the average duty cycle command , and filters outshort-term variations in due to load or input voltage dis-turbances. In the experimental prototype, the filter pole is at1 1 1/2 7, which means that after a change in ittakes at least 2 2 128 switching cycles until the averagecommand becomes equal to the instantaneous duty-cyclecommand . The wait block in the search algorithm ensuresthat the system has reached a new steady state in each step of thesearch and the transient introduced by dead-time change doesnot trigger the dead-time search algorithm. In the optimizationalgorithm of Fig. 8, the number of wait cycles , should begreater than 2 2 128 to ensure that the converter returnsto steady state after the small transient caused by the changein the dead time. If a large load or input voltage transient doesoccur during the wait cycles, the trans signal is generatedaccording to (15), and the optimization algorithm is triggeredagain after the next falling edge of the trans signal. Duringnormal operation, transients longer than the parameteractivate the trans signal, and trigger the optimization algorithmon the falling edge of trans. In practice, can be selectedso that relatively small or short disturbances or changes inoperating conditions do not restart the dead-time optimizationsearch. In the experimental prototype, 20 100 s.

Experimental load transient response waveforms in Fig. 14illustrate the operation of the transient detection. At the point“a” in Fig. 14, a step load change from the full load of 5 Ato the half load of 2.5 A occurs. The compensator generatestime-varying duty-cycle commands to bring the output voltageback to regulation. At the rising edge of the signal trans, which isshown as the point “b” in Fig. 14, the dead-times and areincreased to the safe values, and , respectively.At the falling edge of trans, which is shown as the point “c” inFig. 14, the system is in a new steady state . At thistime, the dead-time optimization algorithm is triggered, and thesearch proceeds as described in Section IV and illustrated inFig. 12.

Fig. 15. Experimental waveforms of the dead time optimization initiated by a100%-to-50% step load transient. Channel 4 shows a signal that indicates thedead-time optimization is in process.

Fig. 15 shows experimental waveforms during the entirelength of the optimization initiated dynamically by the loadtransient shown in Fig. 14.

The time interval “a” in Fig. 15 corresponds to the dead-timeoptimization time for . The time interval “c” corresponds tothe optimization search for . The range of in Fig. 15 is thezero-error bin of the A/D converter sensing the output voltage.The upper edge of the zero-error bin is denoted as and thelower edge as . The dead-time optimization algorithm ofis initiated at the falling edge of the signal trans. As shown inFig. 12, the dead-time starts decreasing from . As aresult, the output voltage starts increasing. As long as the outputvoltage is inside the zero-error bin of the A/D, the compen-sator detects no error, and the duty cycle command remains thesame. As the dead time is decreased further, crosses theupper edge of the zero-error bin, introducing an error signalat the input of the voltage-loop compensator. As a result, thedigital controller decreases the value of the duty cycle and theoutput voltage returns back inside the zero-error bin of the A/Dconverter. This behavior is clearly visible in Fig. 15, showingsmall perturbations in the output voltage as the dead-time op-timization search proceeds. At the point “b” in Fig. 15, thedead-time is too short, the output voltage decreasesand hits the lower edge of the zero-error bin. The compen-sator increases the value of the duty cycle to bring the outputvoltage back to regulation by increasing the duty cycle com-mand. This is detected by the dead-time optimization algorithmfor , which sets the dead time command to the optimum value

, and triggers the optimization search. Following thesame steps as for , the dead-time optimization for startsat the point “b” and ends at the point “d.” Fig. 15 shows thatthe total time for the optimization is about 43 ms, whichagrees well with the experimental digital data shown in Fig. 12.It should be noted that this time corresponds to the optimizationthat starts from the safe dead-time values . In apractical implementation of the dynamic operation described inthis section, the optimization, when triggered, could start fromthe previously determined optimum, which would result in a sig-nificantly shorter time to complete the search. Furthermore, the


optimum values could be stored in a look-up table addressedby the average duty-cycle command (or by other availablesignals), thus eliminating the need to retrigger the dead-timesearch. Current research efforts are directed towards evaluatingthese and other options in the presence of repeated or unpre-dictable load or input voltage transients.

VI. CONCLUSION

This paper introduces an approach to achieve optimum deadtimes in dc–dc converters with synchronous rectifiers withoutsensing any of the power-stage signals other than the outputvoltage (which is sensed for the purpose of closed-loop dcvoltage regulation anyway). The dead-times are adjusted tominimize the average duty-cycle command, which coincideswith maximization of the converter efficiency in steady stateoperation. The performance is unaffected by parameter ortemperature variations, operating conditions, zero-voltage orhard-switching operation, size or type of the power devices, orany gate-drive or circuit implementation details. The methodis particularly well suited for digital controller implementa-tion, requiring only relatively small additional digital logicresources. No additional analog components or modificationsof standard gate-drive circuitry are needed. A proof-of-conceptdigitally controlled 5 V-to-1 V, 5-A, 200-KHz synchronousbuck converter has been constructed to demonstrate prac-tical implementation of the sensorless dead-time optimizationalgorithm.

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[9] V. Yousefzadeh, N. Wang, D. Maksimovic, and Z. Popovic, “Digitallycontrolled DC–DC converter for RF power amplifier,” in Proc. IEEEAPEC, 2004, pp. 81–87.

[10] A. Syed, E. Ahmed, and D. Maksimovic, “Digital PWM controllerwith feed-forward compensation,” in Proc. IEEE APEC’04, 2004, pp.60–66.

[11] H. Peng and D. Maksimovic, “Digital current mode controller forDC–DC converters,” in Proc. 20th Annu. IEEE APEC, Mar. 2005, pp.899–905.

[12] B. J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, “High-fre-quency digital PWM controller IC for DC–DC converters,” IEEETrans. Power Electron., vol. 18, no. 1, pp. 438–446, Jan. 2003.

Vahid Yousefzadeh (S’03) received the B.S. degreein electrical engineering from Amirkabir Universityof Technology, Tehran, Iran, in 1994 and the M.S. de-gree from the University of Colorado at Boulder in2004 where he is currently pursuing the Ph.D. degree.

From 1994 to 2002, he was a Design and ResearchEngineer with Namvaran, and Bina-Afzar Engi-neering, Tehran, where he was involved with powersystem and power electronics design engineering.His research interests include modeling, simulation,and digital control techniques in power electronics.

Dragan Maksimovic (M’89) received the B.S. andM.S. degrees in electrical engineering from the Uni-versity of Belgrade, Belgrade, Yugoslavia, in 1984and 1986, respectively, and the Ph.D. degree fromthe California Institute of Technology, Pasadena, in1989.

From 1989 to 1992, he was with the University ofBelgrade. Since 1992, he has been with the Depart-ment of Electrical and Computer Engineering, Uni-versity of Colorado at Boulder, where he is currentlyan Associate Professor and Co-Director of the Col-

orado Power Electronics Center (CoPEC). His current research interests includepower electronics for low-power, portable systems, digital control techniques,and mixed-signal integrated circuit design for power electronics.

Dr. Maksimovic received the NSF CAREER Award in 1997 and the PowerElectronics Society Transactions Prize Paper Award.

paper 5 : sensorless optimization of dead times in dc-dc converters with synchronous rectifiers

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