pal16r4

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TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R

HIGH-PERFORMANCEIMPACT PAL CIRCUITS

SRPS019A FEBRUARY 1984 REVISED APRIL 2000

1POST OFFICE BOX 655303 DALLAS, TEXAS 75265

High-Performance Operation:Propagation Delay

C Suffix . . . 15 ns MaxM Suffix . . . 20 ns Max

Functionally Equivalent, but Faster ThanPAL16L8A, PAL16R4A, PAL16R6A, andPAL16R8A

Power-Up Clear on Registered Devices (AllRegister Outputs Are Set High, but VoltageLevels at the Output Pins Go Low)

Package Options Include Both Plastic andCeramic Chip Carriers in Addition toPlastic and Ceramic DIPs

Dependable Texas Instruments Quality andReliability

DEVICEI

INPUTS

3-STATEO

OUTPUTS

REGISTEREDQ

OUTPUTS

I/OPORTS

PAL16L8 10 2 0 6

PAL16R4 8 04 (3-statebuffers) 4



description

These programmable array logic devices featurehigh speed and functional equivalency when

compared with currently available devices. TheseIMPACT circuits combine the latest AdvancedLow-Power Schottky technology with proventitanium-tungsten fuses to provide reliable,high-performance substitutes for conventionalTTL logic. Their easy programmability allows forquick design of custom functions and typicallyresults in a more compact circuit board. Inaddition, chip carriers are available for furtherreduction in board space.

The TIBPAL16 C series is characterized from 0 Cto 75 C. The TIBPAL16 M series is characterized

for operation over the full military temperaturerange of 55 C to 125 C.

These devices are covered by U.S. Patent 4,410,987.IMPACT is a trademark of Texas Instruments.PAL is a registered trademark of Advanced Micro Devices Inc.

Copyright 2000, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

12345678910

20191817161514131211

IIIIIIIII

GND

VCCOI/OI/OI/OI/OI/OI/OOI

TIBPAL16L8C SUFFIX . . . J OR N PACKAGEM SUFFIX . . . J OR W PACKAGE

(TOP VIEW)

45678

1817161514

I/OI/OI/OI/OI/O

IIIII

TIBPAL16L8C SUFFIX . . . FN PACKAGEM SUFFIX . . . FK PACKAGE

(TOP VIEW)

I I I

O I / O

O

I

G N D I

V C C

3 2 1 20 19

9 10 11 12 13

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TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15CTIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20MHIGH-PERFORMANCEIMPACT PAL CIRCUITS


2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

12345678910

20191817161514131211

CLKIIIIIIII

GND

VCCI/O

I/OQQQQI/OI/OOE

TIBPAL16R4C SUFFIX . . . J OR N PACKAGEM SUFFIX . . . J OR W PACKAGE

(TOP VIEW)

CLKIIIIIIII

GND

VCCI/OQQQQQQI/OOE


(TOP VIEW)

CLKIIIII

III

GND

VCCQQQQQ

QQQOE


(TOP VIEW)

I I C L K

I / O

I / O

I / O

I

G N D

V C C

O E

I/OQQQQ

IIIII

TIBPAL16R4C SUFFIX . . . FN PACKAGEM SUFFIX . . . FK PACKAGE

(TOP VIEW)

I I C L K

I / O Q

I / O

I

G N D

V C C

QQQQQ

IIIII

O E


(TOP VIEW)

I I C L K

Q Q

Q

I

G N D

V C C

O E

QQQQ

Q

IIII

I


(TOP VIEW)

12345678910

20191817161514131211

123456

78910

201918171615

14131211

45678

1817161514

3 2 1 20 19

9 10 11 12 13

45678

1817161514

3 2 1 20 19

9 10 11 12 13

4567

8

18171615

14

3 2 1 20 19

9 10 11 12 13

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TIBPAL 16L8-15C, TIBPAL 16R4-15TIBPAL 16L8-20M, TIBPAL 16R4-20




functional block diagrams (positive logic)

denotes fused inputs

TIBPAL16L8

TIBPAL16R4

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I

EN 1&32 64

10 16

166

7

7

7

7

7

7

7

7

6

Q

I/O

I/O

I/O

I/O

I

EN

8 16

164

7

7

7

8

8

8

7

4

1

1

8

Q

Q

Q

4

1D

I = 1 2

CLK C1EN 2OE

4

16

16

&32 64

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TIBPAL 16R6-15C, TIBPAL 16R8-15CTIBPAL 16R6-20M, TIBPAL 16R8-20MHIGH-PERFORMANCEIMPACT PAL CIRCUITS



functional block diagrams (positive logic)

denotes fused inputs

TIBPAL16R6

TIBPAL16R8

Q

I/O

I/O

I

EN

8 16

162

7

8

8

8

7

2

1

1

8

Q

Q

Q

6

1DI = 1 2

CLK C1EN 2OE

6

8 Q

8 Q

Q

I8 16

168

8

8

8

8

8

Q

Q

Q

1D

I = 1 2

CLK C1EN 2

8 Q

8 Q

1

OE

8 Q

8 Q

16

16

&32 64

&32 64

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TIBPAL 16L8-15CTIBPAL 16L8-20M




logic diagram (positive logic)

0 4 8 12 16 20 24 28 31

I2

I3

4

I5

I6

I7

I8

I9

O19

I/O18

I/O17

I/O16

I/O15

I/O14

I/O13

O12

I11

IncrementI 1

Fuse number = First fuse number + Increment

0326496

128160192224

256288320352384416448480

512544576

608640672704736

768800832864896928960992

10241056108811201152118412161248

12801312134413761408144014721504

15361568160016321664169617281760

17921824185618881920195219842016

FirstFuse

Numbers

I

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TIBPAL 16R4-15CTIBPAL 16R4-20MHIGH-PERFORMANCEIMPACT PAL CIRCUITS




2016

0 4 8 12 16 20 24 28 31

I2

I3

I4

I5

I6

I7

I8

I9

I/O19

I/O18

Q17

Q16

Q15

Q14

I/O13

I/O12

11

IncrementCLK 1


0326496

128160192224

256288320352384416448480

512544576

608640672704736

768800832864896928960992

10241056108811201152118412161248

12801312134413761408144014721504

15361568160016321664169617281760

1792182418561888192019521984

FirstFuse

Numbers

C1

1DI = 1

C1

1DI = 1

C1

1DI = 1

C1

1DI = 1

OE

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TIBPAL 16R6-15CTIBPAL 16R6-20M






0 4 8 12 16 20 24 28 31

I2

I3

I4

I5

I6

I7

I 8

I9

I/O19

Q17

Q16

Q15

Q14

I/O12

11

IncrementCLK 1

0326496

128160192224

256288320352384416448480

512544576608640672704736

768800832864896928960992

10241056108811201152

118412161248

12801312134413761408144014721504

15361568160016321664169617281760

17921824185618881920195219842016

FirstFuse

Numbers

C1

1DI = 1

C1

1DI = 1

C1

1DI = 1

C1

1DI = 1

OE

Q18

C1

1DI = 1

Q13

C1

1DI = 1

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TIBPAL 16R8-15CTIBPAL 16R8-20MHIGH-PERFORMANCEIMPACT PAL CIRCUITS




0 4 8 12 16 20 24 28 31

I2

I3

I4

I5

I6

I7

I8

I9

Q17

Q16

Q15

Q14

IncrementCLK 1


0326496

128160192224

256288320352384416448480

512544576

608640672704736

768800832864896928960992

10241056108811201152118412161248

12801312134413761408144014721504

15361568160016321664169617281760

17921824185618881920195219842016

FirstFuse

Numbers

C1

1DI = 1

C1

1DI = 1

C1

1DI = 1

C1

1DI = 1

OE

Q18

C1

1DI = 1

Q13

C1

1DI = 1

Q19

C1

1DI = 1

Q12

C1

1DI = 1

11

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TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8HIGH-PERFORMANCEIMPACT PAL CIRCUITS



absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V CC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Operating free-air temperature range 0 C to 75 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T stg 65 C to 150 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .NOTE 1: These ratings apply, except for programming pins, during a programming cycle.

recommended operating conditionsMIN NOM MAX UNIT

VCC Supply voltage 4.75 5 5.25 V

VIH High-level input voltage 2 5.5 V

VIL Low-level input voltage 0.8 V

IOH High-level output current 3.2 mA

IOL Low-level output current 24 mA

fclock Clock frequency 0 50 MHz

High 8w u u , Low 9

tsu Setup time, input or feedback before clock 15 ns

th Hold time, input or feedback after clock 0 ns

TA Operating free-air temperature 0 25 75 C

NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, f clock . The minimum pulse durations specified are forclock high or low only, but not for both simultaneously.

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TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15CHIGH-PERFORMANCEIMPACT PAL CIRCUITS SRPS019A FEBRUARY 1984 REVISED APRIL 2000


electrical characteristics over recommended operating free-air temperature rangePARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIK VCC = 4.75 V, I I = 18 mA 1.5 V

VOH VCC = 4.75 V, I OH = 3.2 mA 2.4 3.3 V

VOL VCC = 4.75 V, I OL = 24 mA 0.35 0.5 V

Outputs 20OZH I/O ports CC

= . , O = . 100

Outputs 20OZL I/O ports CC

= . , O = . 250

II VCC = 5.25 V, V I = 5.5 V 0.1 mA

IIH VCC = 5.25 V, V I = 2.7 V 20 A

IIL VCC = 5.25 V, V I = 0.4 V 0.2 mA

IO VCC = 5.25 V, V O = 2.25 V 30 125 mA

ICC VCC = 5.25 V, V I = 0, Outputs open 140 180 mA

All typical values are at V CC = 5 V, T A = 25 C. The output conditions have been chosen to produce a current that closely approximates one-half of the short-circuit output current, I OS .

switching characteristics over recommended ranges of supply voltage and operating free-airtemperature (unless otherwise noted)

PARAMETERFROM

(INPUT)TO

(OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT

fmax 50 MHz

tpd I, I/O O, I/O 10 15 ns

tpd CLK Q R1 = 500 , 8 12 ns

ten OE Q ,

R2 = 500 , 8 12 ns

tdis OE QSee Figure 3 7 10 ns

ten I, I/O O, I/O 10 15 ns

tdis I, I/O O, I/O 10 15 ns

All typical values are at V CC = 5 V, T A = 25 C.

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TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16RHIGH-PERFORMANCEIMPACT PAL CIRCUITS



absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V CC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Operating free-air temperature range 55 C to 125 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T stg 65 C to 150 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .NOTE 1: These ratings apply, except for programming pins, during a programming cycle.

recommended operating conditionsMIN NOM MAX UNIT

VCC Supply voltage 4.5 5 5.5 V

VIH High-level input voltage 2 5.5 V

VIL Low-level input voltage 0.8 V

IOH High-level output current 2 mA

IOL Low-level output current 12 mA

fclock Clock frequency 0 41.6 MHz

High 10w u u , Low 11

tsu Setup time, input or feedback before clock 20 ns

th Hold time, input or feedback after clock 0 ns

TA Operating free-air temperature 55 25 125 C

NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, f clock . The minimum pulse durations specified are forclock high or low only, but not for both simultaneously.

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TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20MHIGH-PERFORMANCEIMPACT PAL CIRCUITS SRPS019A FEBRUARY 1984 REVISED APRIL 2000


electrical characteristics over recommended operating free-air temperature rangePARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIK VCC = 4.5 V, I I = 18 mA 1.5 V

VOH VCC = 4.5 V, I OH = 2 mA 2.4 3.2 V

VOL VCC = 4.5 V, I OL = 12 mA 0.25 0.4 V

Outputs 20OZH I/O ports CC

= . , O = . 100

Outputs 20OZL I/O ports CC

= . , O = . 250

Pin 1, 11 0.2I All others CC

= . , I = . 0.1

Pin 1, 11 50

IIH I/O ports V CC = 5.5 V, V I = 2.7 V 100 A

All others 20

I/O ports 0.25IL All others CC

= . , I = . 0.2

IOS

VCC = 5.5 V, V O = 0.5 V 30 250 mAICC VCC = 5.5 V, V I = 0, Outputs open 140 190 mA

All typical values are at V CC = 5 V, T A = 25 C. Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set V O at 0.5 V to avoid

test-equipment degradation.

switching characteristics over recommended ranges of supply voltage and operating free-airtemperature (unless otherwise noted)

PARAMETERFROM

(INPUT)TO

(OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT

fmax 41.6 MHz

tpd I, I/O O, I/O 10 20 ns

tpd

CLK QR1 = 390 ,

8 15 ns

ten OE Q R2 = 750 , 8 15 ns

tdis OE QSee Figure 4 7 15 ns

ten I, I/O O, I/O 10 20 ns

tdis I, I/O O, I/O 10 20 ns

All typical values are at V CC = 5 V, T A = 25 C.

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TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R




programming information

Texas Instruments programmable logic devices can be programmed using widely available software andinexpensive device programmers.

Complete programming specifications, algorithms, and the latest information on hardware, software, andfirmware are available upon request. Information on programmers capable of programming Texas Instrumentsprogrammable logic also is available, upon request, from the nearest TI field sales office or local authorized TIdistributor, by calling Texas Instruments at +1 (972) 6445580, or by visiting the TI Semiconductor Home Pageat www.ti.com/sc.

preload procedure for registered outputs (see Figure 1 and Note 3)

The output registers can be preloaded to any desired state during device testing. This permits any state to betested without having to step through the entire state-machine sequence. Each register is preloaded individuallyby following the steps given below.

Step 1. With V CC at 5 V and Pin 1 at V IL, raise Pin 11 to V IHH.Step 2. Apply either V IL or V IH to the output corresponding to the register to be preloaded.Step 3. Pulse Pin 1, clocking in preload data.

Step 4. Remove output voltage, then lower Pin 11 to V IL. Preload can be verified by observing thevoltage level at the output pin.

tdtsu

twtd

VIHH

VIL

VIL

VOL

VOH

VIH

Pin 11

Pin 1

Registered I/O Input OutputVIH

VIL

NOTE 3: t d = t su = t h = 100 ns to 1000 ns V IHH = 10.25 V to 10.75 V

Figure 1. Preload Waveforms

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TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15CTIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20MHIGH-PERFORMANCEIMPACT PAL CIRCUITS



power-up reset (see Figure 2)

Following power up, all registers are set high. This feature provides extra flexibility to the system designer andis especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is importantthat the rise of V CC be monotonic. Following power-up reset, a low-to-high clock transition must not occur untilall applicable input and feedback setup times are met.

1.5 V

tsu

tpd

tw

VIL

VIH

5 VVCC

Active-LowRegistered Output

CLK

4 V

VOH

VOL

1.5 V

(600 ns TYP, 1000 ns MAX)

1.5 V

This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data. This is the setup time for input or feedback.

Figure 2. Power-Up Reset Waveforms

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TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8HIGH-PERFORMANCEIMPACT PAL CIRCUITS



PARAMETER MEASUREMENT INFORMATION

tdis

tdis

tsu

S1

From OutputUnder Test

TestPoint

R2CL

(see Note A)

LOAD CIRCUIT FOR 3-STATE OUTPUTS

th

TimingInput

DataInput

Input

In-PhaseOutput

Out-of-PhaseOutput

(see Note D)

tpd

tpd

tpd

tpd

VOLTAGE WAVEFORMSSETUP AND HOLD TIMES

VOLTAGE WAVEFORMSPROPAGATION DELAY TIMES

VOH

VOH

VOL

VOL

tw

High-LevelPulse

Low-LevelPulse

OutputControl

(low-levelenabling)

Waveform 1S1 Closed

(see Note B)

Waveform 2S1 Open

(see Note B)

3.5 V

0.3 V

3.5 V

VOL

VOH

VOH 0.3 V0 V

ten

ten

VOLTAGE WAVEFORMSENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOLTAGE WAVEFORMSPULSE DURATIONS

R1

3.5 V

0.3 V

VOL + 0.3 V

7 V

NOTES: A. C L includes probe and jig capacitance and is 50 pF for t pd and t en , 5 pF for t dis .B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform

2 is for an output with internal conditions such that the output is high except when disabled by the output control.C. All input pulses have the following characteristics: PRR 1 MHz, t r = t f 2 ns, duty cycle = 50%D. When measuring propagation delay times of 3-state outputs from low to high, switch S1 is closed.

When measuring propagation delay times of 3-state outputs f rom high to low, switch S1 is open.E. Equivalent loads may be used for testing.

1.3 V

1.3 V 1.3 V

3.5 V

0.3 V

3.5 V

0.3 V

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

3.5 V

0.3 V

3.5 V

0.3 V

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V

1.3 V

Figure 3. Load Circuit and Voltage Waveforms

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TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20MHIGH-PERFORMANCEIMPACT PAL CIRCUITS SRPS019A FEBRUARY 1984 REVISED APRIL 2000


PARAMETER MEASUREMENT INFORMATION

tdis

tdis

tsu

S1

From OutputUnder Test

TestPoint

R2CL

(see Note A)

LOAD CIRCUIT FOR 3-STATE OUTPUTS

th

TimingInput

DataInput

Input

In-PhaseOutput

Out-of-PhaseOutput

(see Note D)

tpd

tpd

tpd

tpd

VOLTAGE WAVEFORMSSETUP AND HOLD TIMES

VOLTAGE WAVEFORMSPROPAGATION DELAY TIMES

VOH

VOH

VOL

VOL

tw

High-LevelPulse

Low-LevelPulse

OutputControl

(low-levelenabling)

Waveform 1S1 Closed

(see Note B)

Waveform 2S1 Open

(see Note B)

3 V

0

3.3 V

VOL

VOH

VOH 0.5 V0 V

ten

ten

VOLTAGE WAVEFORMSENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOLTAGE WAVEFORMSPULSE DURATIONS

R1

3 V

0

VOL + 0.5 V

5 V

NOTES: A. C L includes probe and jig capacitance and is 50 pF for t pd and t en , 5 pF for t dis .B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform

2 is for an output with internal conditions such that the output is high except when disabled by the output control.C. All input pulses have the following characteristics: PRR 10 MHz, t r = t f 2 ns, duty cycle = 50%D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.E. Equivalent loads may be used for testing.

1.5 V

1.5 V 1.5 V

3 V

0

3 V

0

1.5 V 1.5 V

1.5 V 1.5 V

3 V

0

3 V

0

1.5 V 1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V 1.5 V

1.5 V

1.5 V

Figure 4. Load Circuit and Voltage Waveforms

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IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being relied on is current and complete. All products are soldsubject to the terms and conditions of sale supplied at the time of order acknowledgment, including thosepertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale inaccordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extentTI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarilyperformed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customers applications, adequate design and operatingsafeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or representthat any license, either express or implied, is granted under any patent right, copyright, mask work right, or otherintellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TIs publication of information regarding any thirdpartys products or services does not constitute TIs approval, warranty or endorsement thereof.

Copyright 2000, Texas Instruments Incorporated

pal16r4

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