Paging and Virtual Memory

Memory management: Review

Fixed partitioning, dynamic partitioning

ProblemsInternal/external fragmentationA process can be loaded only if a contiguous memory chunk is available to accommodate the processProcess size is limited by the main memory size

Advantage: simplicity

Paging Process memory is divided into fixed

size chunks of the same size, called pages

Pages are mapped onto frames in the main memory

Process pages can be scattered all over the main memory

Paging example01

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Free Frame List

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Paging support Page table maintains mapping of

process pages onto frames Hardware support is needed to

support translation of relative addresses within a program (logical addresses) into the memory addresses

Address translation Page (frame) size is

a power of 2with page size = 2r, a logical address of l+r bits is interpreted as a tuple (l,r)l = page number, r = offset within the page

Page number is used as an index into the page table

Hardware support

Program Paging Main Memory

Logical address

Register

Page Table

PageFrame

Offset

P#

Frame #

Page Table Ptr

Page # Offset Frame # Offset

+

Virtual Memory Paging makes virtual memory

possibleLogical to physical address mapping is dynamic

=> It is not necessary that all of the process pages be in main memory during execution

Benefits More processes may be maintained

in the main memoryBetter system utilization and throughput

The process size is not restricted by the physical memory size: the process memory is virtual

But what is the limit anyway?

Less disk I/O to swap/load programs

How does this work? CPU can execute a process as long as

some portion of its address space is mapped onto the physical memory

E.g., next instruction and data addresses are mapped

Once a reference to an unmapped page is generated (page fault):

Page fault interrupt transfers control to the OS handler

Page Fault Handler Put the process into blocking state Program disk controller to read the

page from disk into the memory Later on: I/O interrupt signals

completion Resume the process

Why is this practical? Observation: Program branching and

data access patterns are not random Principle of locality: program and

data references tend to cluster=> Only a fraction of the process

virtual address space need to be resident to allow the process to execute for sufficiently long

Virtual memory implementation

Efficient run-time address translationHardware support, control data structures

Fetch policyDemand paging: page is brought into the memory only when page-fault occursPre-paging: pages are brought in advance

Page replacement policyWhich page to evict when a page fault occurs?

Thrashing A condition when the system is

engaged in moving pages back and forth between memory and disk most of the time

Bad page replacement policy may result in thrashing

Programs with non-local behavior

Address translation Virtual address is divided into page

number and offset

Mapping of virtual pages onto physical frames are facilitated by page table(s)

Forward-mapped page tables (FMPT)Inverted page tables (IPT)

Virtual Address

Page Number Offset

Forward-mapped page tables (FMPT)

Page table entry (PTE) structure

Page table is an array of the above

Index is the virtual page number

P M Frame NumberOther Control Bits

Page Table

Frame #

Page #

P: present (valid) bitM: modified bit

Address Translation using FMPT

Program Paging Main Memory

Virtual address

Register

Page Table

PageFrame

Offset

P#

Frame #

Page Table Ptr

Page # Offset Frame # Offset

+

Handling large address spaces One level FMPT is not suitable for

large virtual address spaces32 bit addresses, 4K (212) page size, 232 / 212 = 220 entries ~4 bytes each =>

4Mbytes resident page table per process!What about 64 bit architectures??

Solutions: multi-level FMPTInverted page tables (IPT)

Multilevel FMPT Use bits of the virtual address to

index a hierarchy of page tables The leaf is a regular PTE Only the root is required to stay

resident in main memoryOther portions of the hierarchy are subject to paging as regular process pages

Two-level FMPTpage number page offset

pi p2 d

10 10 12

Two-level FMPT

Inverted page table (IPT) A single table with one entry per

physical page Each entry contains the virtual

address currently mapped to a physical page (plus control bits)

Different processes may reference the same virtual address values

Address space identifier (ASID) uniquely identifies the process address space

Address translation with IPT Virtual address is first indexed into

the hash anchor table (HAT) The HAT provides a pointer to a

linked list of potential page table entries

The list is searched sequentially for the virtual address (and ASID) match

If no match is found -> page fault

Address translation with IPT

Virtual addresspage number offset

hash

+

HAT baseregister

ASID

register

page numberASID

Frame#

IPT

+

IPT baseregister

frame number

HAT

Translation Lookaside Buffer (TLB)

With VM accessing a memory location involves at least two intermediate memory accesses

Page table access + memory access

TLB caches recent virtual to physical address mappings

ASID or TLB flash is used to enforce protection

TLB internals TLB is associative, high speed memory

Each entry is a pair (tag,value)When presented with an item it is compared to all keys simultaneouslyIf found, the value is returned; otherwise, it is a TLB missExpensive: number of typical TLB entries: 64-1024Do not confuse with memory cache!

Address translation with TLB

Bits in the PTE: Present (valid) Present (valid) bit

Indicates whether the page is assigned to frame or notA reference to an invalid page generates page fault which is handled by the operating system

Bits in PTE: modified, used Modified (dirty) bit

Indicates whether the page has been modifiedUnmodified pages need not be written back to the disk when evicted

Used bitIndicates whether the page has been accessed recentlyUsed by the page replacement algorithm

Bits in PTE Access permissions bit

indicates whether the page is read-only or read-write

UNIX copy-on-write bitSet whether more than one process shares a pageIf one of the processes writes into the page, a separate copy must first be made for all other processes sharing the pageUseful for optimizing fork()

Protection with VM Preventing processes from

accessing other process pages Simple with FMPT

Load the process page table base address into a register upon context switch

ASID with IPT

Page size considerations Small page size

better approximates localitylarge page tablesinefficient disk transfer

Large page sizeinternal fragmentation

Most modern architectures support a number of different page sizes

a configurable system parameter

Next: Page replacement