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Configurable Command and Control Structure With Soft-Core Processor

The Romanian Review Precision Mechanics, Optics & Mechatronics, 2012, No. 41 13

CONFIGURABLE COMMAND AND CONTROL STRUCTURE

WITH SOFT-CORE PROCESSOR

Dan Rotar

"Vasile Alecsandri" Bacau University,

Calea Marasesti 157, Bacau, Romania, 600115, [email protected]

Abstract: The mechatronic systems in use today have some command and control systems,generally represented by microsystems, which are made with the microprocessors or themicrocontrollers. Depending on the complexity of the mechatronic system and the controlsolution adopted, the CPUs used may have an 8, 16 or 32 bits data bus. Such an approach has theadvantage of a specified hardware and the task of the designer is to connect the existing physicalstructures and to develop the command and the control software.The development of such physical structures represented by programmable logic arrays allows a

new approach to such systems. Such a structure provided with a soft-core processor and theconfiguration ability as needed can bring certain advantages of the control system performanceand optimization. The judicious choice of program components and the necessary physicalstructure increases the working speed and lowers the overall consumption.The article presents a solution to achieve the command and control system drives of the robotthrough its implementation with Xilinx programmable logic array fitted with a soft-coreprocessor. The article explains how to program the physical structures necessary to commandand control the robot motors and how to use the soft-core processor.The main advantage of this approach is the simple ability to change the physical structuredepending on the engine used (stepper or DC motor) and using the strictly necessary physicalcomponents. At the same time, the designer can choose the required rapport between thesoftware and the hardware components so as to ensure both the necessary operating speed andthe simplicity to achieve the command and control program.

Keywords: soft-core processor, programmable logic arrays, command and control system, driverobots, microprocessor, microcontroller.

1. Introduction

The FPGA (Field Programmable Gate Array) allowthe HDL (Hardware Description Language)programming of the digital physical structures.Programming the logical structures brings a fewimportant advantages, such as: the possibility of theoptimization of the physical structure according ofthe application, the computing speed is higher due tothe parallel processing, the intake is low, etc. Thefact that programming the physical structures withthe help of the HDL languages must be also takeninto consideration because it is generally harder thanthe programming of the software structures withhigh level programming languages. Sometimes, acertain physical structure that is not modified isneeded, but the change of the correspondingcommands is necessary. Because of this reason, insome cases, the use of soft-care processors in thestructure built through the FPGA programming.A soft-core processor is the main component of a

computing system built in a single FPGA circuit.Such a component is a hardware structureprogrammed on a FPGA circuit and which canexecute a program from a ROM memory (ReadOnly Memory) also done through HDLprogramming on the FPGA circuit. The user can addas they desire hardware modules such as ports,

timers, communication modules, and other,depending on the obtained application so as toachieve an optimization of the hardware structure.Such a system built on a FPGA is programmed usingtwo methods. First of all, a HDL is used to programthe physical structure and then an assembly languagefor programming the central unit of the soft-coreprocessor. This way, the biggest advantage is thatalong with the change of the program for the centralunit, the physical structure associated can also bechanged through a single operation. For anembedded system used for the command and controlof a structure such as a mechatronic structure,

improvements and changes always appear. Due to


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The Romanian Review Precision Mechanics, Optics & Mechatronics, 2012, No. 4114

this, such a completely programmable system leadsto a series of supplementary facilities inprogramming and in exploitation [10]. If we countthe continuous developing of the FPGA, theimprovements made and the supplementary facilities

added, we can say that such a solution is extremelyattractive for the system designers.

2. The Soft-core used

For the experiments presented in this paper,intellectual property (IP), open-source cores or freecores were used. Open-source cores are IPcomponents that are freely available in the open-source community [6] [7]. The free version used isthe PicoBlaze 8 bit processor offered by Xilinx, andthe open-source was the AVR core, which iscompatible with the 103 ATMEL ATmega 8 bit

microcontroller offered by the OpenCorescommunity [1]. Each of these solutions wasimplemented on a Xilinx Spartan-3 platform due tothe fact that the chosen soft-core processors areoptimized for this platform.In figure 1, the general structure of the AVRmicroprocessor is presented. Such a structure in theminimal configuration contains a soft-core with aprogram memory and a data memory.

Figure 1. The AVR system

There are two ways to add the user modules. One ofthem is to associate an address from the addressingspace of the data memory, which is not used, to thenewly made module. This way, the data transferbetween the microcontroller and the new createdmodule is done through operations ofwriting/reading of the memory making sure that anincreased speed for the data transfer is available. Themain inconvenient of this method consists of the factthat the high impedance state of the interface cannotbe maintained through the program.The second possibility to add new modules to the

microcontroller is through an input/output portcreated by the user. This way, the transfer of theinformation with the created module is done throughthe input/output instructions of the microcontroller.It is obvious that the transfer speed of the data is

lower, but in this situation, we do benefit from allthe advantages of using an input/ output port: thehigh impedance state, interruptions, etc.Due to the fact that the AVR ATmegamicrocontroller [2] is well known and used in otherapplications, we benefit from lots of already createdtools for its programming. These tools can be usedwith some modifications in the systems embeddedon the FPGA [3]. For example, C or C++applications can be developed with the help of thetools for the developing of the WinAVRTM [4]software based on the GNU GCC compilator anduploaded into the ROM memory of the

microcontroller through the FPGA programmingfolder.The second soft-core used is the one offered by theXilinx firm named PicoBlaze. In figure 2 theminimal structure of a Soc (System on Chip) donewith this 8 bit microcontroller.

Figure 2. The PicoBlaze system

The programming of the microcontroller is done inthe assembly language, a special programmingenvironment for this being available. The writing ofthe ROM memory is done through the FPGAconfiguration folder. In order to connect thesupplementary modules, the input/output ports of themicrocontroller are used. In this situation, theadditional modules being added by the user andbenefiting from all the advantages of theinput/output operations with which the

microcontroller is equipped.


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3. Command and control solution for the drives

The command and control solutions of the drives areessentially depend on the type of engine used [5][11]. The drives used for robots were studied

without making an exhaustive study about them. Themain purpose of the tests was to determine which theadvantages of the method are and to analyze theobtained results. To this purpose, this paper willpresents the contributions of the author to theexecution of the PWM generator and the functiongenerator of a SoC done on a Xilinx Spartan 3E

platform.

4. The PWM generator

Figure 3 presents the main block of the hardware

structure of the PWM generator.The PWM generators working is based oncomparing the content of the U5 and U6 registers.Depending on the type of the wave form desired,symmetric or asymmetric, one or two comparators(the U7 and U8 circuits) are used.

Figure 3. The main block of the PWM generator

In figure 4, the wave forms of the PWMgenerator are presented, when an asymmetric wave

form is generated,which explains the way it works.

For the PWM circuits with which themicrocontrollers are equipped, the designer has thepossibility to establish the tact frequency of thePWM period counter and the Duty Cycle value. Dueto this, the PWM generator resolution is limited bythe size of the counters (usually 10 or 12 bits) and bythe command frequency.For the presented solution, the designer establishesthrough the soft-core program the frequency of the

clock signal the value of the Duty Cycle duration,and through the hardware structure, the size of the

counters used. These parameters can be easilymodifies through the change of some constants ofthe programs for the software and hardwarestructures. This new proposed solution allows theintroduction of some new facilities for the PWMgenerator. This way, the value obtained by the U6register (for establishing the Duty Cycle) can bedynamically changed according to a certain profile.In figure 5, such a situation is presented; the signal

generated being used for the command of a LED(Light Emitting Diode) illuminating device.

Figure 4. The wave forms of the PWM generator.

end PWM

cycle

start

cycle

end duty

cycle


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The Romanian Review Precision Mechanics, Optics & Mechatronics, 2012, No. 4116

Figure 5. The Duty Cycle modulation

The command of the physical structure of the PWMby the soft-core is done through 3 ports or memorylocations. Due to the fact that the size of the U5 andU6 counters is variable and it is chosen by the user,in order to allow the use of some common,configurable codes for the software, a multiplexorfor the successive command of the structure is used.There are two 8 bit data ports (U1 and U2) so that 16bit data can be written and an 8 bit command port(U4). The command port allows the configuration of

the hardware structure and of the output signal.5. The function generator

A particular situation is represented by the case inwhich the synthesis of an output signal that canreproduce an analogue function is required. Usually,the generated system is a sinusoidal system used atthe command of the invertors and then the technique

used is called the PWM sinusoidal technique. Thecircuit used for the generation of the sinusoidalcircuit is presented in figure 3. At present, themodulation of the output signal through thealteration of the duration of the impulse is donebased on some tables places in a memory which areread sequentially. These tables contain the values ofthe duration of the impulse (of the Duty Cycleduration). In the case of the symmetrical signals,such as the sinusoidal signal, a great quantity of

memory can be saved by using the symmetry of thesignal.For example, for the sinusoidal signal is enough tomemorize the values form the 0-/2 interval. Thesynthesis of the system is done, as it is shown infigure 6 with the help of some bidirectional counters,operated depending on the number of read values tocover four times in a period, the saved values beingascending and descending.

Figure 6. The signals of the function generator

In Figure 6, the signal "clock" is the clock commandwith which the frequency of the generated signal ischanged, "state" is a direction control signal for thecounters generating the address for the memory tablecontaining waveform signal, "table_index" is thegenerated address, the "wave_out" signal is thedigital output signal converted to analog signal foreasy visualization and the "positive_cycle" signal isthe signal order to reverse the signal for thesynthesis of alternating positive and negative.

The main disadvantage of the method shown is thatthe values needed to generate the function once

stored in the memory cannot be modified.The solution proposed in this paper generated thenecessary values for the command of the duration ofthe impulse with the help of a program of the soft-core processor created in the programmable logicalarray. This allows the increase of the flexibility ofthe generator through the change of thecharacteristics of the function generated taking intoconsideration the process parameters. At the sametime, the system even allows the change of the type

of function generated while working.The output signal generation can be done in two


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ways: on one bit or more bits. Generating the outputsignal on a single bit is done by modulating thewidth of the signal (as shown in Figure 5). In thiscase, the output is likely to be required to install afilter for the correction of the output signal. In the

second case, where through the output more bits aresent, it is no longer the case of the pulse widthmodulation but of the sending of the codes directlyto a digital-analog converter. The designerdetermines the number of bits for synthesisaccording to the desired resolution. And in this caseit may be necessary to mount the output of aninterpolation circuit.The solution currently used for the realization ofsuch a circuit involves the use of fixed hardwarestructures possibly supplemented by a programmingstructure to increase system flexibility. The newsolution presented in this paper allows maximum

flexibility by using programmable structures. Thechoice of the solutions presented is facilitated by thepossibility of modifying the structure of bothsoftware and hardware simultaneously. Also, thedrive control is achieved by modifying theparameters of the generator; the control possibilitiesare broader than those for the classical solutions dueto flexibility of the proposed system.In case of the complex functions generation, the soft-core module must perform complex calculations. At thesame time the chosen control algorithms requiresome calculations from a certain complexity.Depending on when the data is needed: the table

function values are created before the start of thecommand or a function values table is created duringthe command, the computing time can becomecritical. To meet these demands a mixed solution wasadopted. Thus, the complex calculations are done usinghardware, also connected through a port or a memorylocation. This custom hardware, also depending on theapplication implemented, can be treated as amathematical processor. But in this situation thedesigner can choose a different solution. For example,a soft-core with the corresponding number of bit databus, 16 or 32 bits can be adopted, for thecorresponding increase in computing speed. In this

situation the mathematical process can be waivedand the problem can be solved exclusively by thesoftware methods. As noted, the programming in ahigh-level programming language raises fewerproblems than writing a program in HDL. Theflexibility of the solution presented in this paperallows choosing the best solution to solve the problem.

6. Conclusions

This paper presents a new method of establishing thePWM interface for the command for the robot drives. The

presented solution represents a SoC done on a FPGA

Xilinx Spartan 3E platform. Due to this approach,many advantages can be stated. These advantages are:

othe designer can choose the balance between thesoftware and the hardware components used in theproject, mainly taking into consideration theperformances which are wanted;ochanging the structure and the characteristics ofthe PWM interface presented in this article can bemade in a simple way through the change of someparameters from the HDL description or from thesoft-core program;othe insurance of an increased flexibility,optimizations being easily made according to theactual conditions imposed;oincreasing the drive control flexibility because thesystem introduced the possibility of programmingthe hardware structure and software component.Through the experiments made on a Digilent Basys2platform, the fact that SoC is used for the robotdrives allows the acquiring of superior performances

in comparison to the classic systems.

7. References

[1] http://opencores.org/project,avr_core[2] http://www.atmel.com/Images/doc0945.pdf[3] https://github.com/[4] http://winavr.sourceforge.net/[5] Fredrik Roos, Hans Johansson, Jan Wikander,Optimal selection of motor and gearhead in mechatronicapplications, ELSEVIER, Mechatronics 16, pp. 6372,2006[6] Franjo Plavec, Soft-Core Processor Design,Thesis for the Degree of Master of Applied Science,Graduate Department of Electrical and ComputerEngineering University of Toronto, 2004[7] Jason G. Tong, Ian D. L. Anderson and MohammedA. S. Khalid, Soft-Core Processors for EmbeddedSystem, The 18th International Conference onMicroelectronics (ICM), pp. 170-173, 2006[8] Xiao Wanang, Fang Zhi, Shi Yin, The Design andImplementation of the IEEE 802.11 Mac Based On Soft-Core Processor and Rtos, Journal of Electronics(CHINA), Vol.24 No.2, pp. 232-237, March 2007[9] M. Finc, A. Zemva, Profiling soft-core processorapplications for hardware/software partitioning, Journal

of Systems Architecture 51, pp. 315329, 2005[10]Alexander Biedermann, Marc Stttinger, LijingChen and Sorin A. Huss, Secure Virtualizationwithin a Multi-processor Soft-Core System-on-ChipArchitecture, Lecture Notes in Computer Science,2011, Volume 6578, Reconfigurable Computing:Architectures, Tools and Applications, pp. 385-396, 2011[11]Markus Flckiger, Sensorless Position Controlof Piezoelectric Ultrasonic Motors: a MechatronicDesign Approach, Thse no 4752 (2010) colepolytechnique fdrale de Lausanne prsente le 27aot 2010 la Facult Sciences et Techniques del'ingnieur laboratoire d'actionneurs intgrs

programme doctoral en systmes de production etrobotique, pp. 68-113, 2010
http://opencores.org/project,avr_corehttp://opencores.org/project,avr_corehttp://www.atmel.com/Images/doc0945.pdfhttp://www.atmel.com/Images/doc0945.pdfhttps://github.com/https://github.com/http://winavr.sourceforge.net/http://winavr.sourceforge.net/http://winavr.sourceforge.net/https://github.com/http://www.atmel.com/Images/doc0945.pdfhttp://opencores.org/project,avr_core

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