p3c18v8z40/p3c18v8zia 3 volt zero standby power universal

P3C18V8Z40/P3C18V8ZIA3 Volt zero standby power universal PAL devices

Product specification 1996 Oct 09

INTEGRATED CIRCUITS

IC13 Data Handbook

Philips Semiconductors Product specification

P3C18V8Z40/P3C18V8ZIA3 volt zero standby poweruniversal PAL devices

21996 Oct 09 853–1847 17376

DESCRIPTIONThe P3C18V8Z is a universal PAL-type device designed to operatespecifically in a low voltage environment (3.3V). The PAL device isavailable in the commercial temperature range, P3C18V8Z40, andthe industrial temperature range, P3C18V8ZIA.

These devices offer virtually zero standby power (15µA typical) aswell as very low power consumption during operation. TheP3C18V8Z automatically powers down when the inputs or the clockare idle for greater than one full clock cycle. The device willautomatically power up from a standby mode once any input or theclock is activated. This input transition detection circuitry makesthese devices ideal for power sensitive applications –– especiallythose which are battery operated or backed up.

All the P3C18V8Z devices are available in plastic DIP, PLCC, PlasticSmall Outline (SOL), Plastic Shrink Small Outline (SSOP), andPlastic Thin Shrink Small Outline (TSSOP) packages. A ceramicDIP with a window for erasure is available for prototyping.

The P3C18V8Z is a two level logic element comprised of 10 inputs,74 AND gates (logic and control product terms) and 8 Output MacroCells (OMCs). Each OMC can be configured as a dedicated input, acombinatorial I/O or a registered output with internal feedback.Each OMC has individual direction control (from the AND array) andprogrammable output polarity. The dedicated clock and OE pins canbe configured as inputs for strictly combinatorial applications. Twoproduct terms control the asynchronous Reset and the synchronousPreset functions.

Power up Reset and Register Preload functions have also beenincorporated into the P3C18V8Z to facilitate state machine designand testing.

The Output Macro Cell feature of the P3C18V8Z devices providesthe flexibility to emulate all 20 pin common PAL and GAL functions,thus providing reduced documentation, inventory and manufacturingcosts. The P3C18V8Z is also pin and fuse map compatible with allthe Philips 5 Volt PLC18V8Z devices.

FEATURES• 20-pin Universal Programmable Array Logic (PAL), operational

over low voltage range and industrial temperature range

• Virtually zero-standby-power and very low dynamic power

– 15µA standby (typ.)

– 0.9 mA/MHz (worst case)

• Functional replacement for Series 16 PALs and GALs

– Highly flexible Output Macro Cell

• Available in DIP, PLCC, SOL (Small Outline), SSOP (Shrink SmallOutline), and TSSOP (Thin Shrink Small Outline) packages

• High performance EPROM CMOS cell technology

– 100% testable prior to programming

– Low cost OTP plastic packages

– Erasable/reconfigurable (ceramic package)

• Design support provided by most popular third partyprogrammable Logic CAD tools

APPLICATIONS• Laptop, notebook and palm top computers

• Portable communications equipment

• Battery powered instruments

• Industrial automation/control

PIN CONFIGURATIONS

1

2

3

4

5

6

7

8

9

10 11

12

13

14

15

16

17

18

19

20

D, DB, DH, N, and FA Packages

I0/CLK

I1

I2

I3

I4

I5

I6

I7

I8 F0

GND

F1

F2

F3

F4

F5

F6

F7

VCC

I9/OE

D = Plasitc Small Outline Large Package (300mil-wide)DB = Plastic Shrink Small Outline Package (5.3mm wide)DH = Plastic Thin Shrink Small Outline Package (4.4mm wide)N = Plastic Dual In-Line Package (DIP) (300mil-wide)FA = Ceramic DIP with Quartz Window (300mil-wide)

123

4

5

6

7

8

9 10 11 12 13

14

15

16

17

18

1920

A Package

A = Plastic Leaded Chip Carrier

F0 F1

F2

F3

F4

F5

F6

F7VCC

I9/OE

I0/CLKI1I2

I3

I4

I5

I6

I7

I8 GND

SP00026A

PIN DESCRIPTIONS

I Dedicated Input

F Output/Input Macrocell

CLK Clock Input

OE Output Enable

VCC Supply Voltage

GND Ground



1996 Oct 09 3

ORDERING INFORMATION

DESCRIPTION TEMPERATURERANGE ORDER CODE DRAWING

NUMBER

20-Pin (300mil-wide) Plastic Dual In-Line Package

Commercial

P3C18V8Z40N SOT146-1

20-Pin (300mil-wide) Ceramic Dual In-Line Package with Quartz Window

Commercial

P3C18V8Z40FA 0584B

20-Pin (350mil square) Plastic Leaded Chip Carrier PackageCommercial

P3C18V8Z40A SOT380-1

20-Pin (300mil-wide) Plastic Small Outline Large PackageCommercial

P3C18V8Z40D SOT163-1

20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package P3C18V8Z40DB SOT339-1

20-Pin (4.4mm-wide) Plastic Thin Shrink Small Outline Package P3C18V8Z40DH SOT360-1

20-Pin (300mil-wide) Plastic Dual In-Line Package

Industrial

P3C18V8ZIAN SOT146-1

20-Pin (300mil-wide) Ceramic Dual In-Line Package with quartz window

Industrial

P3C18V8ZIAFA 0584B

20-Pin (350mil square) Plastic Leaded Chip Carrier PackageIndustrial

P3C18V8ZIAA SOT380-1

20-Pin (300mil-wide) Plastic Small Outline Large PackageIndustrial

P3C18V8ZIAD SOT163-1

20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package P3C18V8ZIADB SOT339-1

20-Pin (4.4mm-wide) Plastic Thin Shrink Small Outline Package P3C18V8ZIADH SOT360-1



1996 Oct 09 4

PAL DEVICE TO P3C18V8Z OUTPUT PIN CONFIGURATION CROSS REFERENCE

PINNO.

P3C18V8Z

16L816H816P816P8

16R416RP4

16R616RP6

16R816RP8

16L216H216P2

14L414H414P4

12L612H612P6

10L810H810P8

1 I0/CLK I CLK CLK CLK I I I I

19 F7 B B B D I I I O

18 F6 B B D D I I O O

17 F5 B D D D I O O O

16 F4 B D D D O O O O

15 F3 B D D D O O O O

14 F2 B D D D I O O O

13 F1 B B D D I I O O

12 F0 B B B D I I I O

11 I9/OE I OE OE OE I I I I

The Philips Semiconductors’ state-of-the-art Floating-Gate CMOSEPROM process yields bipolar equivalent performance at less thanone-quarter the power consumption. The erasable nature of theEPROM process enables Philips Semiconductors to functionally testthe devices prior to shipment to the customer. Additionally, thisallows Philips Semiconductors to extensively stress test, as well asensure the threshold voltage of each individual EPROM cell. 100%programming yield is subsequently guaranteed.

FUNCTIONAL DIAGRAM

CONFIG.CELL

CONFIG.CELL

I0/CLK

I1

I2

I7

I8

PR

OG

RA

MM

AB

LE A

ND

AR

RA

Y36

RO

WS

X 7

2 C

OLU

MN

S

F6

F1

F0

I9/OE

I9

F7

I0

CLK

9

9

9

9

OMC

OE

OMC

OMC

OMC

SP

AR

SP00013



1996 Oct 09 5

LOGIC DIAGRAM

Pins 1 and 11 are configured as Inputs 0 and 9, respectively, via the configuration cell. The clock and OEfunctions are disabled.All output macro cells (OMC) are configured as bidirectional I/O, with the outputs disabled via the direc-tion term. Denotes a programmable cell location.

1

2

3

4

5

6

7

8

9

NOTES:In the unprogrammed or virgin state:

All cells are in a conductive state.All AND gate locations are pulled to a logic “0” (Low).Output polarity is inverting.

0 4 8 12 16 20 24 28 32 35

SP

AR

CLK OE

AC1AC2

DIR

CLK

F719

11

SP

AR

CLK OE

AC1AC2

DIR

F618

SP

ARCLK OE

AC1AC2

DIR

F517

SP

AR

CLK OE

AC1AC2

DIR

F416

SP

ARCLK OE

AC1AC2

DIR

F315

SP

ARCLK OE

AC1AC2

DIR

F214

SP

AR

CLK OE

AC1AC2

DIR

F113

SP

ARCLK OE

AC1AC2

DIR

F012

SPAR

I9/OE

I0/CLK

I1

I2

I3

I4

I5

I6

I7

I8

I I I I0 0 9 9I I F F

8 8 0 0I I F F

7 7 1 1I I F F

6 6 2 2I I F F

5 5 3 3I I F F

4 4 4 4I I F F

3 3 5 5I I F F

2 2 6 6I I F F

1 1 7 7 CONFIG.CELL

SP00012



1996 Oct 09 6

OUTPUT MACRO CELL (OMC)

OEMUX

1

11

CLKQ

OE

D F

00111001

OUTMUX

10

00

01

11

FMUX

0010

1101

VCC

OUTPUTPOLARITYCONTROL

FROMAND

ARRAYS

X(n)

DIRECTION CONTROL TERM

TO ALL OMCs

TO ALL OMCs

AC1n

AC2n

NOTE:Denotes a programmable cell location.

FROM ANDARRAY

SP

AR

.

SP00014

THE OUTPUT MACRO CELL (OMC)The P3C18V8Z series devices have 8 individually programmableOutput Macro Cells. The 72 AND inputs (or product terms) from theprogrammable AND array are connected to the 8 OMCs in groups of9. Eight of the AND terms are dedicated to logic functions; the ninthis for asynchronous direction control, which enables/disables therespective bidirectional I/O pin. Two product terms are dedicated forthe Synchronous Preset and Asynchronous Reset functions.

Each OMC can be independently programmed via 16 architecturecontrol bits, AC1n and AC2n (one pair per macro cell). Similarly,each OMC has a programmable output polarity control bit (Xn). Byconfiguring the pair of architecture control bits according to theconfiguration cell table, 4 different configurations may beimplemented. Note that the configuration cell is automaticallyprogrammed based on the OMC configuration.

DESIGN SECURITYThe P3C18V8Z series devices have a programmable security fusethat controls the access to the data programmed in the device. Byusing this programmable feature, proprietary designs implementedin the device cannot be copied or retrieved.



1996 Oct 09 7

CONFIGURATION CELLA single configuration cell controls the functions of Pins 1 and 11.Refer to Functional Diagram. When the configuration cell isprogrammed, Pin 1 is a dedicated clock and Pin 11 is dedicated foroutput enable. When the configuration cell is unprogrammed, Pins 1and 11 are both dedicated inputs. Note that the output enable for allregistered OMCs is common—from Pin 11 only. Output enablecontrol of the bidirectional I/O OMCs is provided from the AND arrayvia the direction product term.

If any one OMC is configured as registered, the configuration cellwill be automatically configured (via the design software) to ensurethat the clock and output enable functions are enabled on Pins 1and 11, respectively. If none of the OMCs are registered, theconfiguration cell will be programmed such that Pins 1 and 11 arededicated inputs. The programming codes are as follows:

Pin 1 = CLK, Pin 11 = OE L

Pin 1 and Pin 11 = Input H

CONTROL CELL CONFIGURATIONS

FUNCTION AC11 AC2N CONFIG. CELL COMMENTS

Registered mode Programmed Programmed Programmed Dedicated clock from Pin 1. OE Controlfor all registerd OMCs from Pin 11 only.

Bidirectional I/O mode Unprogrammed Unprogrammed Unprogrammed Pins 1 and 11 are dedicated inputs.3-State control from AND array only.

Fixed input mode Unprogrammed Programmed Unprogrammed Pins 1 and 11 are dedicated inputs.

Fixed output mode Programmed Unprogrammed Unprogrammed Pins 1 and 11 are dedicated inputs. Thefeedback path (via FMUX) is disabled.

NOTE:1. This is the virgin state as shipped from the factory.

ARCHITECTURE CONTROL—AC1 and AC2

I

CODE

D

OMC CONFIGURATION

REGISTERED (D–TYPE)

1

11

S

CLK

F(D), F (D)Q

OE

SF(B), F (B)

DIR

CODE

B

OMC CONFIGURATION CODE

O

OMC CONFIGURATION

FIXED OUTPUT

CODECONFIGURATION CELLCODE

L

CONFIGURATION CELLCODEOMC CONFIGURATION

FIXED INPUT

BIDIRECTIONAL I/O1

(COMBINATORIAL)

PIN 1 = CLKPIN 11 = OE H6PIN 1 = INPUT

PIN 11 = INPUT

SF(O), F (O)

F (I)

F(D), F (D)

11

1

CLK Q

OE

11

1

CLK Q

OE

NC

NC

SP

AR

SP

AR

SP

AR

SP00015

NOTES:A factory shipped unprogrammed device is configured such that:1. This configuration cannot be used if any OMCs are configured as registered (Code = D). The configuration cell will be automatically

configured to ensure that the clock and output enable functions are enabled on Pins 1 and 11, respectively, if any one OMC is programmedas registered.* All AND gates are pulled to a logic ”0” (Low).* Output polarity is inverting. * Pins 1 and 11 are configured as inputs 0 and 9. The clock and OE functions are disabled. * All Output Macro Cells (OMCs) are configured as bidirectional I/O, with the outputs disabled via the direction term.



1996 Oct 09 8

ABSOLUTE MAXIMUM RATINGS 1

SYMBOL PARAMETER RATINGS UNIT

VCC Supply voltage –0.5 to +6 VDC

VCC Operating supply voltage 3.0 to 3.6 VDC

VIN Input voltage –0.5 to VCC +0.5 VDC

VOUT Output voltage –0.5 to VCC +0.5 VDC

∆t/∆V Input/clock transition rise or fall2 200 ns/V maximum

IIN Input currents –10 to +10 mA

IOUT Output currents +24 mA

Tamb Operating temperature range–40 to +85 (Industrial) 0 to +75 (Commercial)

°C

Tstg Storage temperature range –65 to +150 °C

NOTES:1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at

these or any other condition above those indicated in the operational and programming specification of the device is not implied.2. All digital circuits can oscillate or trigger prematurely when input rise and fall times are very long. When the input signal to a device is at or

near the switching threshold, noise on the line will be amplified and can cause oscillation which, if the frequency is low enough, can causesubsequent stages to switch and give erroneous results. For this reason, external Schmitt-triggers are recommended if rise/fall times arelikely to exceed 200ns at VCC = 3.6V.

THERMAL RATINGS

TEMPERATURE

Maximum junction 150°C

Maximum ambient 75°C

Allowable thermal rise ambient to junction 75°C

AC TEST CONDITIONS

+3.3V

CL

R1

R2

S1

GNDBZ

BY

INPUTS

I0

I9BW

BXOUTPUTS

C2C1

DUT

NOTES:C1 and C2 are to bypass VCC to GND.R1 = 200Ω R2 = 390Ω

VCC

SP00353

VOLTAGE WAVEFORMS

90%

10%

5ns5ns

5ns 5ns

90%

10%

+3.0V

+3.0V

0V

0V

tR tF

MEASUREMENTS:All circuit delays are measured at the +1.5V level of inputs and outputs,unless otherwise specified.

Input Pulses SP00017

SWITCHING WAVEFORM

Input to Output Disable/Enable

tER tEA

VOH – 0.3V

VOL + 0.3V

INPUT

OUTPUT

VT

VT

SP00354



1996 Oct 09 9

DC ELECTRICAL CHARACTERISTICS3.0V ≤ VCC ≤ 3.6 rangesCommercial = 0°C ≤ Tamb ≤ +75°CIndustrial = –40°C ≤ Tamb ≤ +85°C

LIMITS

SYMBOL PARAMETER TEST CONDITION MIN TYP1 MAX UNIT

Input voltage

VIL Low VCC = MIN –0.3 0.8 V

VIH High VCC = MAX 2.0 VCC + 0.3 V

Output voltage 2

VOL LowVCC = MIN, IOL = 20µA 0.100 V

VOL LowVCC = MIN, IOL = 24mA 0.500 V

VOH HighVCC = 3.0, IOH = –3.2mA VCC – 0.6

VOH High VCC = 3.0, IOH = –20µA VCC – 0.3 VOHVCC = 3.0, IOH = –1.6µA VCC – 0.3 V

Input current

IIL Low5 VIN = GND –5 µA

IIH High VIN = VCC 5 µA

Output current

IO(OFF) Hi–Z stateVOUT = VCC 10 µA

IO(OFF) Hi–Z stateVOUT = GND –10 µA

IOS Short-circuit3 VOUT = GND –130 mA

ICC VCC supply current (Standby) VCC = MAX, VIN = 0 or VCC6 15 40 µA

ICC/f VCC supply current (Active)4 VCC = MAX .75 0.9 mA/MHz

Capacitance

CI Input VCC = 5V, VIN = 2.0V 12 pF

CB I/O VB = 2.0V 15 pF

NOTES:1. All typical values are at VCC = 3.3V, Tamb = +25°C.2. All voltage values are with respect to network ground terminal.3. Duration of short–circuit should not exceed one second. Test one at a time.4. Measured with all outputs switching.5. IIL for Pin 1 (I0/CLK) is ± 10µA with VIN = 0.4V.6. VIN includes CLK and OE if applicable.



1996 Oct 09 10

AC ELECTRICAL CHARACTERISTICS3.0V ≤ VCC ≤ 3.6V range; R2 = 390ΩCommercial = 0°C ≤ Tamb ≤ +75°CIndustrial = –40°C ≤ Tamb ≤ +85°C

TEST CONDITION1 P3C18V8Z40(Commercial)

P3C18V8ZIA(Industrial)

SYMBOL PARAMETER FROM TO CL (pF) MIN MAX MIN MAX UNIT

Pulse width

tCKP Clock period (Minimum tIS + tCKO) CLK + CLK + 50 47 57 ns

tCKH Clock width High CLK + CLK – 50 20 25 ns

tCKL Clock width Low CLK – CLK + 50 20 25 ns

tARW Async reset pulse width I ±, F± I +, F + 35 40 ns

Hold time

tIH Input or feedback data hold time CLK + Input ± 50 0 0 ns

Setup time

tIS Input or feedback data setup time I ±, F± CLK + 50 30 35 ns

Propagation delay

tPD Delay from input to active output I ±, F± F± 50 40 45 ns

tCKOClock High to output valid accessTime CLK + F± 50 15 20 ns

tOE1 Product term enable to outputs off I ±, F± F± 50 40 45 ns

tOD1 Product term disable to outputs off I ±, F± F± 5 40 45 ns

tOD2Pin 11 output disable High to outputsoff OE – F± 5 25 30 ns

tOE2 Pin 11 output enable to active output OE + F± 50 30 35 ns

tARD Async reset delay I ±, F± F + 40 45 ns

tARR Async reset recovery time I ±, F± CLK + 30 35 ns

tSPR Sync preset recovery time I ±, F± CLK + 30 35 ns

tPPR Power-up reset VCC + F + 35 40 ns

Frequency of operation

fMAX Maximum frequency I/(tIS + tCKO) 50 22 18 MHz

NOTES:1. Refer also to AC Test Conditions. (Test Load Circuit)



1996 Oct 09 11

POWER-UP RESETIn order to facilitate state machine design and testing, a power-upreset function has been incorporated in the P3C18V8Z. All internalregisters will reset to Active-Low (logical “0”) after a specified periodof time (tPPR). Therefore, any OMC that has been configured as aregistered output will always produce an Active-High on theassociated output pin because of the inverted output buffer. Theinternal feedback (Q) of a registered OMC will also be set Low. Theprogrammed polarity of OMC will not affect the Active-High outputcondition during a system power-up condition.

TIMING DIAGRAMS

ÉÉÉÉ

ÉÉÉÉ

ÉÉÉÉ

ÉÉÉÉ

ÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ




ÉÉÉ

ÉÉÉ

ÉÉÉ

ÉÉÉ

ÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉ

Switching Waveforms

VALID INPUTVALID INPUT

3–STATE

3-STATE

INPUTSI/O, REG.

FEEDBACK

CLK

PIN 11 OE

REGISTEREDOUTPUTS

ANY INPUTPROGRAMMED FOR

DIRECTION CONTROL

COMBINATORIALOUTPUTS

tIS tIH tCKH tCKL

tCKP

tCKO

tOD1

tOD2 tOE2

tPD tOE1

Power-Up Reset

NOTE:Diagram presupposes that the outputs (F) are enabled. The reset occurs regardless of the output condition (enabled or disabled).

tCKP

tCKH tCKLtIS

1.5V 1.5V 1.5V

tCKL tIH tIS

1.5V1.5V

tCKO

1.5V1.5V

tPPR

2.6V

+3.3V

0V

VOH

VOL

+3V

0V

+3V

0V

VCC

F(OUTPUTS)

I, B(INPUTS)

CLK

SP00356



1996 Oct 09 12

TIMING DIAGRAMS (Continued)

tSPR

tARW

ASYNCHRONOUSRESET INPUT

REGISTEREDOUTPUT

CLOCK

tARD

tARR

SYNCHRONOUSPRESET INPUT

CLOCK

REGISTEREDOUTPUT

Asynchronous Reset

Synchronous Preset

tIS tIH

tCKO

SP00021



1996 Oct 09 13

REGISTER PRELOAD FUNCTION(DIAGNOSTIC MODE ONLY)In order to facilitate the testing of state machine/controller designs, adiagnostic mode register preload feature has been incorporated intothe P3C18V8Z series device. This feature enables the user to loadthe registers with predetermined states while a super voltage isapplied to Pins 11 and 6 (I9/OE and I5). (See diagram for timing andsequence.)

To read the data out, Pins 11 and 6 must be returned to normal TTLlevels. The outputs, F0 – 7, must be enabled in order to read dataout. The Q outputs of the registers will reflect data in as input viaF0 – 7 during preload. Subsequently, the register Q output via thefeedback path will reflect the data in as input via F0 – 7.

Refer to the voltage waveform for timing and voltage references.tPL = 10µsec.

REGISTER PRELOAD (DIAGNOSTIC MODE)

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ




I9/OE(PIN 11)

I5(PIN 6)

I0/CLK(PIN 1)

F0–7

I1–4, 6–8

PRELOAD DATA IN PRELOAD DATA OUT DATA OUT

OE(VOL)

I0/CLK

F0–7

I1–4, 6–8

tPL tPL tPL tPL tPL tPL

tOE tCKL tCKO

tIS tIH

5.0V5.0V

12.0V 12.0V

12.0V

5.0V

SP00022



1996 Oct 09 14

LOGIC PROGRAMMINGThe P3C18V8Z series is fully supported by industry standard(JEDEC compatible) PLD CAD tools, including PhilipsSemiconductors’ SNAP design software package. ABEL andCUPL 90 design software packages also support the P3C18V8Zarchitecture.

All packages allow Boolean and state equation entry formats. SNAP,ABEL and CUPL also accept, as input, schematic capture format.

P3C18V8Z logic designs can also be generated using the programtable entry format, which is detailed on the following pages. Thisprogram table entry format is supported by SNAP only.

With Logic programming, the AND/OR/EX-OR gate inputconnections necessary to implement the desired logic function arecoded directly from logic equations using the Program Table.Similarly, various OMC configurations are implemented byprogramming the Architecture Control bits AC1 and AC2. Note thatthe configuration cell is automatically programmed based on theOMC configuration.

In this table, the logic state of variables I, P and B associated witheach Sum Term S is assigned a symbol which results in the properfusing pattern of corresponding link pairs, defined as follows:

ERASURE CHARACTERISTICS(For Quartz Window Packages Only)The erasure characteristics of the P3C18V8Z Series devices aresuch that erasure begins to occur upon exposure to light withwavelengths shorter than approximately 4000 Angstroms (Å). Itshould be noted that sunlight and certain types of fluorescentlighting could erase a typical P3C18V8Z in approximately threeyears, while it would take approximately one week to cause erasurewhen exposed to direct sunlight. If the P3C18V8Z is to be exposedto these types of lighting conditions for extended periods of time,opaque labels should be placed over the window to preventunintentional erasure.

The recommended erasure procedure for the P3C18V8Z isexposure to shortwave ultraviolet light which has a wavelength of2537 Angstroms (Å). The integrated dose (i.e., UV intensity ×exposure time) for erasure should be a minimum of 15Wsec/cm2.The erasure time with this dosage is approximately 30 to 35 minutesusing an ultraviolet lamp with a 12,000µW/cm2 power rating. Thedevice should be placed within one inch of the lamp tubes duringerasure. The maximum integrated dose a CMOS EPLD can beexposed to without damage is 7258Wsec/cm2). Exposure of theseCMOS EPLDs to high intensity UV light for longer periods maycause permanent damage.

The maximum number of guaranteed erase/write cycles is 50. Dataretention exceeds 20 years.

OUTPUT POLARITY – (O, B)

O, BS

X

ACTIVE LEVEL CODE

LINVERTING1

O, BS

X

ACTIVE LEVEL CODE

HNON-INVERTINGSP00023

“AND” ARRAY – (I, B)

CODE

–

STATE

DON’T CARE

CODESTATE CODESTATE CODESTATE

INACTIVE1 O I, B H I, B L

P P P P

I, B

I, BI, B

I, B

I, BI, B

I, B

I, BI, B

I, B

I, BI, B

SP00024

NOTE:1. A factory shipped unprogrammed device is configured such that all cells are in a conductive state.

ABEL is a trademark of Data I/O Corp.CUPL is a trademark of Logical Devices, Inc.



1996 Oct 09 15

* THE CONFIGURATION CELL IS AUTOMATICALL Y PROGRAMMED BASED ON THE OMC ARCHITECTURE.** FOR SP, AR: “ –” IS NOT ALLOWED.

TERM 7 6 5 4 3 2 1 07 6 5 4 3 2 1 07 6 5 4 3 2 1 089

76543210

89

1011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071SPAR

PIN

DAAAAAAAA

DAAAAAAAA

DAAAAAAAA

DAAAAAAAA

DAAAAAAAA

DAAAAAAAA

DAAAAAAAA

DAAAAAAAA

11 9 8 7 6 5 4 3 2 1 1213141516171819 1213141516171819

VA

RIA

BLE

NA

ME

AND OR (FIXED)

CONFIGURATION CELL (CLK/OE CONTROL)

I F (I) F (B, O, D)

ARCH. CONTROL BITSOUTPUT POLARITY

CU

ST

OM

ER

NA

ME

PU

RC

HA

SE

OR

DE

R #

PH

ILIP

S D

EV

ICE

#C

F(X

XX

X)

CU

ST

OM

ER

SY

MB

OLI

ZE

D P

AR

T #

TO

TAL

NU

MB

ER

OF

PA

RT

S

PR

OG

RA

M T

AB

LE #

RE

V.D

AT

E

NO

TE

S:

In th

e un

prog

ram

med

or

virg

in s

tate

:A

ll A

ND

gat

e lo

catio

ns a

re p

ulle

d to

a lo

gic

“0”

(Low

).O

utpu

t pol

arity

is in

vert

ing.

Pin

s 1

and

11 a

re c

onfig

ured

as

inpu

ts 0

and

9, r

espe

ctiv

ely,

via

the

conf

igur

atio

n ce

ll. T

he c

lock

and

OE

func

tions

are

dis

able

d.A

ll ou

tput

mac

ro c

ells

(O

MC

) ar

e co

nfig

ured

as

com

bina

toria

l I/O

,w

ith th

e ou

tput

s di

sabl

ed v

ia th

e di

rect

ion

cont

rol t

erm

.

INACTIVE

I, F (I, B)

I, F (I, B)**DON’T CARE

O

H

L

–

AND ARRAY CONTROL OR ARRAY (FIXED)

• • • •

REGISTERED(D-TYPE)FIXED INPUT

FIXED OUTPUTBIDIRECTIONAL I/O

D

I

OB

OMC ARCH. OUTPUT POLARITY

NON-INVERTING

INVERTING

H

L

CONFIG. CELL*

PIN 1 = CLK; PIN 11 = OE

PIN 1, PIN 11 = INPUT

L

H

DATA CANNOT BE ENTEREDINTO THE OR ARRAY FIELDDUE TO THE FIXED NATUREOF THE DEVICE ARCHITEC-TURE.

DIRECTION CONTROL

ACTIVE OUTPUT

D

A

NOT USED

PROGRAM TABLE

SP00029



1996 Oct 09 16

SNAP RESOURCE SUMMARY DESIGNATIONS

CONFIG.CELL

CONFIG.CELL

I0/CLK

I1

I2

I7

I8

PR

OG

RA

MM

AB

LE A

ND

AR

RA

Y36

RO

WS

X 7

2 C

OLU

MN

SF6

F1

F0

I9/OE

I9

F7

I0

CLK

9

9

9

9

OMC

OE

OMC

OMC

OMC

SP

AR

CKEV8

NOUTV8

NOUTV8

NOUTV8

NOUTV8

AND

DINV8

NINV8

OEMUX

1

11

CLKQ

OE

D

F

10

00

01

11

FMUX

00

10

1101

VCC

OUTPUTPOLARITYCONTROL

FROMAND

ARRAYS

X(n)

DIRECTION CONTROL TERM

TO ALL OMCs

TO ALL OMCs

AC1n

AC2n

NOTE:Denotes a programmable cell location.

FROM ANDARRAY

SP

AR

XORINV

XORDIR

XORREG

NOUTV8DFFV8

OR

OE11V8

FDMUX

SP00025



1996 Oct 09 17

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1



1996 Oct 09 18

0584B 20-PIN (300 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE)

NO

TE

S:

1.C

ontr

ollin

g di

men

sion

: Inc

hes.

Mill

imet

ers

are

2.D

imen

sion

and

tole

ranc

ing

per A

NS

I Y14

. 5M

-198

2.3.

“T”,

“D

”, a

nd “

E”

are

refe

renc

e da

tum

s on

the

body

4.T

hese

dim

ensi

ons

mea

sure

d w

ith th

e le

ads

5.P

in n

umbe

rs s

tart

with

Pin

#1

and

cont

inue

6.D

enot

es w

indo

w lo

catio

n fo

r E

PR

OM

pro

duct

s.

and

incl

ude

allo

wan

ce fo

r gl

ass

over

run

and

men

iscu

son

the

seal

line

, and

lid

to b

ase

mis

mat

ch.

cons

trai

ned

to b

e pe

rpen

dicu

lar

to p

lane

T.

coun

terc

lock

wis

e to

Pin

#20

whe

n vi

ewed

show

n in

par

enth

eses

.

from

the

top.

0.20

0 (5

.08)

0.01

0 (0

.254

)T

ED

0.02

3 (0

.58)

0.01

5 (0

.38)

0.16

5 (4

.19)

0.12

5 (3

.18)

0.05

8 (1

.47)

0.03

0 (0

.76)

0.16

5 (4

.19)

0.17

5 (4

.45)

0.14

5 (3

.68)

0.32

0 (8

.13)

0.29

0 (7

.37)

(NO

TE

4)

BS

C0.

300

(7.6

2)

0.39

5 (1

0.03

)

0.30

0 (7

.62)

(NO

TE

4)

0.01

5 (0

.38)

0.01

0 (0

.25)

0.03

5 (0

.89)

0.02

0 (0

.51)

SE

E N

OT

E 6

– D

–

PIN

# 1

– E

–0.

306

(7.7

7)

0.28

5 (7

.24)

0.10

0 (2

.54)

BS

C 0.97

5 (2

4.73

)

0.94

0 (2

3.88

)

0.07

8 (1

.98)

0.01

2 (0

.30)

0.07

8 (1

.98)

0.01

2 (0

.30)

– T

–

SE

AT

ING

PLA

NE

0.07

0 (1

.78)

0.05

0 (1

.27)

853–0584B 06688



1996 Oct 09 19

PLCC20: plastic leaded chip carrier; 20 leads SOT380-1



1996 Oct 09 20

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1



1996 Oct 09 21

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1



1996 Oct 09 22

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1



1996 Oct 09 23

NOTES


P3C18V8Z40/P3C18V8ZIA3 Volt zero standby poweruniversal PAL devices

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. PhilipsSemiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or maskwork right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposesonly. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testingor modification.

LIFE SUPPORT APPLICATIONSPhilips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expectedto result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling PhilipsSemiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fullyindemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

This data sheet contains preliminary data, and supplementary data will be published at a later date. PhilipsSemiconductors reserves the right to make changes at any time without notice in order to improve designand supply the best possible product.

Philips Semiconductors811 East Arques AvenueP.O. Box 3409Sunnyvale, California 94088–3409Telephone 800-234-7381

DEFINITIONS

Data Sheet Identification Product Status Definition

Objective Specification

Preliminary Specification

Product Specification

Formative or in Design

Preproduction Product

Full Production

This data sheet contains the design target or goal specifications for product development. Specificationsmay change in any manner without notice.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changesat any time without notice, in order to improve design and supply the best possible product.

Philips Semiconductors and Philips Electronics North America Corporationregister eligible circuits under the Semiconductor Chip Protection Act.

Copyright Philips Electronics North America Corporation 1996All rights reserved. Printed in U.S.A.

p3c18v8z40/p3c18v8zia 3 volt zero standby power universal

Documents