p-tile ip for pci express* ip core release notes

P-Tile IP for PCI Express* IP CoreRelease Notes

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Contents

1. P-Tile IP for PCI Express IP Core Release Notes............................................................. 31.1. P-Tile IP for PCI Express IP Cores v8.0.0...................................................................31.2. P-Tile IP for PCI Express IP Cores v7.0.0...................................................................41.3. P-Tile IP for PCI Express IP Cores v6.0.0...................................................................61.4. P-Tile IP for PCI Express IP Cores v5.0.0...................................................................81.5. P-Tile IP for PCI Express IP Cores v4.0.0.................................................................101.6. P-Tile IP for PCI Express IP Cores v4.0.0.................................................................141.7. P-Tile IP for PCI Express IP Cores v3.1.0.................................................................161.8. P-Tile IP for PCI Express IP Cores v3.0.0.................................................................191.9. P-Tile IP for PCI Express IP Cores v2.0.0.................................................................221.10. P-Tile IP for PCI Express IP Cores v1.1.0............................................................... 251.11. P-Tile IP for PCI Express IP Cores v19.3................................................................ 261.12. P-Tile IP for PCI Express IP Cores v19.2................................................................ 271.13. P-Tile IPs for PCI Express User Guide Archives....................................................... 27

Contents

P-Tile IP for PCI Express* IP Core Release Notes Send Feedback

2


1. P-Tile IP for PCI Express IP Core Release Notes

1.1. P-Tile IP for PCI Express IP Cores v8.0.0

IP versions are the same as the Intel Quartus Prime Design Suite software versions upto v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IPshave a new IP versioning scheme.

The IP version (X.Y.Z) number may change from one Intel® Quartus® Prime softwareversion to another. A change in:

• X indicates a major revision of the IP. If you update your Intel Quartus Primesoftware, you must regenerate the IP.

• Y indicates the IP includes new features. Regenerate your IP to include these newfeatures.

• Z indicates the IP includes minor changes. Regenerate your IP to include thesechanges.

Table 1. v8.0.0 2022.03.28

Intel Quartus Prime Version Description Impact

22.1 Hardware testing support was added for thePerformance design example.

All design examples (PIO, SR-IOV,Performance) now have SCTH support.

Debug Toolkit support was added for theRoot Port mode.

Both Endpoint and Root Port modescan now support the Debug Toolkit.

Support for the Riviera* simulator wasadded.

The P-tile IP for PCIe can now supportthe Riviera* simulator along with theQuesta* and VCS* simulators.

Table 2. P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for IntelStratix® 10 DX DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T =timing, H = hardware, N/A = configuration not supported

ConfigurationPCIe IP Support Design Example Support Timing Support

EP RP BP EP RP BP -1 -2 -3

Gen4 x16512-bit S C T H S C T H S C T H S C T H N/A N/A 400 MHz 400 MHz N/A

Gen4 x8/x8256-bit S C T H N/A S C T H S C T H N/A N/A 450 MHz 450 MHz 350 MHz

Gen4x4/x4/x4/x4

128-bitN/A S C T H S C T H N/A N/A N/A 450 MHz 450 MHz 350 MHz

continued...

683508 | 2022.03.28

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ISO9001:2015Registered


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Gen3 x16512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz


Gen3x4/x4/x4/x4


Table 3. P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for IntelAgilex™ DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T =timing, H = hardware, N/A = configuration not supported

Configuration

PCIe IP Support Design Example Support Timing Support

EP RP BP EP RP BP -1 -2 -3 -4

Gen4 x16512-bit S C T H S C T H S C T H S C T H N/A N/A 500

MHz500MHz

450MHz N/A

Gen4 x8/x8256-bit S C T H N/A S C T H S C T H N/A N/A 500

MHz500MHz

450MHz

350MHz

Gen4x4/x4/x4/x4

128-bitN/A S C T H S C T H N/A N/A N/A 500

MHz500MHz

450MHz

350MHz


MHz250MHz

250MHz

250MHz


MHz250MHz

250MHz

250MHz

Gen3x4/x4/x4/x4


MHz250MHz

250MHz

250MHz



The IP version (X.Y.Z) number may change from one Intel Quartus Prime softwareversion to another. A change in:





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Table 4. v7.0.0 2021.12.13


21.4 Added P-Tile Performance design example(SCT Support).

This design example can be used todemonstrate P-tile functionality withmultiple TLPs per segment. Foradditional details, refer to the P-TileIntel FPGA IP for PCIe Design ExampleUser Guide.

Added a parameter to the IP ParameterEditor to strip the ECRC field from a TLPpayload.

You can choose to remove the ECRCfield from the TLP payload when the P-Tile FPGA IP for PCIe is configured inTLP Bypass mode.

The Debug Toolkit parameter option hasbeen relocated to the Top-Level Settingstab of the IP Parameter Editor.

This move provides easier access tothe IP Parameter Editor option toenable or disable the Debug Toolkitfeature.

The link_up_o, dll_up_o,ltssm_state_o, andsurprise_down_err_o signals are all partof the Hard IP Status Interface in the 21.4release of Intel Quartus Prime.

These signals are available by defaultwithout any dependency on any IPParameter Editor parameter.




Gen4 x16512-bit S C T H S C T H S C T H S C T H

(1) N/A N/A 400 MHz 400 MHz N/A

Gen4 x8/x8256-bit S C T H N/A S C T H S C T

H (1) N/A N/A 450 MHz 450 MHz 350 MHz

Gen4x4/x4/x4/x4


Gen3 x16512-bit S C T H S C T H S C T H S C T

H (1) N/A N/A 250 MHz 250 MHz 250 MHz


H (1) N/A N/A 250 MHz 250 MHz 250 MHz

Gen3x4/x4/x4/x4


(1) The Performance design example only has SCT support.


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Send Feedback P-Tile IP for PCI Express* IP Core Release Notes

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Configuration




H (1) N/A N/A 500MHz

500MHz

450MHz N/A



500MHz

450MHz

400MHz

Gen4x4/x4/x4/x4


MHz500MHz

450MHz

400MHz



250MHz

250MHz

250MHz



250MHz

250MHz

250MHz

Gen3x4/x4/x4/x4


MHz250MHz

250MHz

250MHz







Table 7. v6.0.0 2021.10.04


21.3 The following signals are added to the PowerManagement Interface:sys_aux_pwr_det_i

apps_ready_entr_l23_i

apps_pm_xmt_turnoff_i

app_xfer_pending_i

User application is required toaccommodate the new signals for thePower Management Interface. Upgradeto Intel Quartus Prime Pro Editionv21.3 if Power Management support isrequired.

Added support for Gen4 x8/x8 512-bitconfiguration.

The data bus width increase allowsbetter performance.

Added support for Gen3 x16 256-bitconfiguration.

The new data bus width providestiming closure flexibility.

continued...


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The P-tile Avalon® Streaming and AvalonMemory-mapped IPs for PCIe do not supportparallel PIPE simulations.

There is no plan to add support forparallel PIPE simulations.

The Power Management behavior of P-tile IPsfor PCIe was updated to align with the

behavior of the IPs for other tiles.

EP/UP RP/DP

L2/L3 entry Ok Ok

L2 exitHost to

initiate orCold Reset

Cold Reset

L3 exit Cold Reset Cold Reset

The Power Management behavior isnow aligned for IPs for PCIe acrossP/F/R-tiles.

Added support to enable ECRC and LCRCerror counters.

Improved error telemetry capabilitiesby allowing the counting of ECRC andLCRC errors on a PCIe link.





Gen4 x8/x8256-bit S C T H N/A S C T H S C T H N/A N/A 450 MHz 450 MHz N/A

Gen4x4/x4/x4/x4

128-bitN/A S C T H S C T H N/A N/A N/A 450 MHz 450 MHz N/A



Gen3x4/x4/x4/x4



Configuration




MHz500MHz

450MHz N/A


MHz500MHz

450MHz

400MHz

continued...


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Configuration



Gen4x4/x4/x4/x4


MHz500MHz

450MHz

400MHz


MHz250MHz

250MHz

250MHz


MHz250MHz

250MHz

250MHz

Gen3x4/x4/x4/x4


MHz250MHz

250MHz

250MHz







Table 10. v5.0.0 2021.06.25


21.2 The issue of missing unique tags in modulenames in generated RTL files for simulationhas been fixed in this release.

You can run simulations havingmultiple PCIe IP instances using thegenerated RTL files for simulation.

Added 450 MHz support forcoreclkout_hip for Intel Stratix® 10 DX inGen4 x8x8 and Gen4 x4x4x4x4 modes.

Application logic can have betterperformance running at 450 MHz.

Added support for Debug Toolkit while inEndpoint mode and using Linux OS.

Using the Debug Toolkit, you can:• Report protocol parameters on a

per-port basis.• Read PHY status information.• Perform Eye-plotting for all 16

channels and in x8x8 mode.

Added timing optimization for the AvalonStreaming PIO design example.

Timing margins for the PIO designexample for the P-tile AvalonStreaming IP for PCI Express havebeen improved.

The Completion Timeout Interface of theAvalon Streaming PIO design example hasbeen exposed.

You can use the Completion TimeoutInterface when generating the AvalonStreaming PIO design example for theP-tile Avalon Streaming IP for PCIExpress.

continued...


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Added support for independent PERST# inx8x8 mode.

You can implement an independentreset for each of the ports in the x8x8configuration by following theguidelines in Appendix E of the P-tileAvalon Streaming IP for PCI ExpressUser Guide.

A new checkbox, CvP (Intel VSEC), hasbeen introduced in the IP Parameter Editor toenable CvP support for both the Intel Stratix10 DX and Intel Agilex™ device families.

When migrating existing CvP designsto Intel Quartus Prime Pro Editionv21.2, regenerate the IP with the CvP(Intel VSEC) checkbox enabled andrecompile the design for the newsetting to take effect.

Fixed the issues with Attention ButtonPressed and Power Fault Detected Hot-Plugslot events by updating internal IP registersettings.

No impact on user interfaces. Upgradeto Intel Quartus Prime Pro Editionv21.2 if Hot Plug support is required.

Enable 10-bit tag support interfaceoption is introduced to expose thep0_10bits_tag_req_en_o [7:0] signalindicating the 10-bit Tag Requester Enablebit of Device Control 2 Register is enabled.However, this feature has the followinglimitation:This feature requires the software at the hostside to write to the Device Control 2 Registerin 1 DWord size. Otherwise, it will cause anincorrect value being provided to the userapplication. This limitation will be resolved ina future release of Intel Quartus Prime ProEdition.

This new feature is optional.

There is a limitation on the fix for the issuewhere the last Physical Function (PF)indicates an incorrect next function number.It does not work correctly when the IP isconfigured with one Physical Function andmultiple Virtual Functions and withAlternative Routing-ID Interpretation (ARI)and Control Services Function Groupcapabilities enabled.

The IP configuration mentioned in thedescription is not supported in IntelQuartus Prime Pro Edition v21.2. It willbe addressed in a future release.

The IP Parameter Editor window has beentidied up and the IP User Guide has beenupdated to reflect the changes.

No functional impact due to thesechanges is expected for existingcustomers.

Table 11. P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for IntelStratix 10 DX DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T =timing, H = hardware, N/A = configuration not supported





Gen4x4/x4/x4/x4


continued...


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Gen3x4/x4/x4/x4


Table 12. P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for IntelAgilex DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T =timing, H = hardware, N/A = configuration not supported



Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 500 MHz 500 MHz N/A


Gen4x4/x4/x4/x4


Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz


Gen3x4/x4/x4/x4









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Table 13. v4.0.0 2020.12.14


20.4 Migrating a design using a P-tile AvalonStreaming or Avalon Memory-mapped IPfrom an earlier Intel Quartus Prime versionto the 20.4 version requires an IP upgrade.

You must regenerate any design usinga P-tile Avalon Streaming or AvalonMemory-mapped IP when moving froman earlier Intel Quartus Prime versionto the 20.4 version.

Parameters to enable independent resets forthe ports in the bifurcated x8x8 Endpointmode have been added to the IP ParameterEditor of the P-tile Avalon Streaming andAvalon Memory-mapped IPs.

Each port in the bifurcated x8x8Endpoint mode can be resetindependently of the other port. Twonew reset signals(p0_pld_clrpcs_n,p1_pld_clrpcs_n) are exported tothe top-level block symbol whenindependent resets are enabled. Thesesignals can be assigned to GPIO pins.Contact your local Field ApplicationsEngineer (FAE) for more details.

The parameter to enable the MSI-X capabilityhas been removed from the IP ParameterEditor when the P-tile Avalon Streaming orAvalon Memory-mapped IP is in Root Port(RP) mode.

The P-tile Avalon Streaming or AvalonMemory-mapped IP is not required tosupport sending MSI-X in RP mode.

The parameter to enable extended tagsupport has been added to the IP ParameterEditor of the P-tile Avalon Streaming IP.

The P-tile Avalon Streaming IP cansupport extended tag in this release.

Options to set acceptable Power Managementlatencies for Endpoints were added to the IPParameter Editor of the P-tile AvalonMemory-mapped IP.

L0s and L1s acceptable latencies cannow be configured in the IP ParameterEditor of the P-tile Avalon Memory-mapped IP in Endpoint mode.

Options to configure the VSEC parameters inEndpoint mode were added to the IPParameter Editor of the P-tile AvalonMemory-mapped IP.

VSEC parameters can now beconfigured in the IP Parameter Editorof the P-tile Avalon Memory-mapped IPin Endpoint mode.

The parameter to enable VirtIO and SR-IOVcapabilities have been removed from the IPParameter Editor when the P-tile AvalonStreaming IP is in Root Port (RP) mode.

The P-tile Avalon Streaming IP is notrequired to support VirtIO or SR-IOV inRP mode.

Options for BAR configuration, Multi-functionand SR-IOV support have been removedfrom the IP Parameter Editor when the P-tileAvalon Streaming IP is in TLP Bypass mode.

The P-tile Avalon Streaming IP is notrequired to support these features inTLP Bypass mode.

Options for Multi-function and SR-IOVsupport support are now visible for Port 1when the P-tile Avalon Streaming IP is in abifurcated mode.

Multi-function and SR-IOV support canbe enabled for Port 1 when the P-tileAvalon Streaming IP is in a bifurcatedmode.

The IP Parameter Editor response time hasbeen improved for the P-tile AvalonStreaming IP.

The turnaround time after each userinput in the IP Parameter Editor issignificantly reduced for the P-tileAvalon Streaming IP in this release.


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Gen4x4/x4/x4/x4




Gen3x4/x4/x4/x4







Gen4x4/x4/x4/x4




Gen3x4/x4/x4/x4



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Table 16. P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCIe Support Matrix forIntel Stratix 10 DX DevicesEP = Endpoint, RP = Root Port. Support level keys: S = simulation, C = compilation, T = timing, H = hardware,N/A = configuration not supported


EP RP EP RP -1 -2 -3

Gen4 x16 512-bit S C T H (††) S C T H (†) (††) 350 MHz 350 MHz N/A

Gen4 x8/x8 512-bit S C T H N/A S C T H (†) N/A 200 MHz 200 MHz N/A

Gen4 x4/x4/x4/x4256-bit N/A S C T H N/A (††) 200 MHz 200 MHz N/A




Note: (†) The design example available in the 20.4 release supports the DMA mode withData Movers. A design example supporting the Bursting Slave mode may be availablein a future release.

Note: (††) This support may be available in a future release of Intel Quartus Prime.

Table 17. P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCIe Support Matrix forIntel Agilex DevicesEP = Endpoint, RP = Root Port. Support level keys: S = simulation, C = compilation, T = timing, H = hardware,N/A = configuration not supported












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Table 18. v4.0.0 2021.03.29


21.1 The P-tile Avalon Memory-mapped IP will notbe supported in future releases of IntelQuartus Prime.

The P-tile Avalon Memory-mapped IPwill not be available in the IP Catalogin future releases of Intel QuartusPrime. The replacement IP is theMCDMA-based PCIe Avalon Memory-mapped IP.

The IP version of the P-tile Avalon StreamingIP is the same in the 21.1 release and 20.4release. However, the IP needs to beregenerated when migrating from 20.4 to21.1.

Regenerating the P-tile AvalonStreaming IP when migrating from20.4 to 21.1 allows you to takeadvantage of the 21.1 IP bug fixes andenhancements.

The following note was removed from the P-tile Avalon Streaming IP for PCI Express*User Guide:Note: If VirtIO is enabled, the CII is used

for VirtIO transport and is notavailable to the application logic forother purposes.

In 21.1, when VirtIO is enabled,Configuration accesses to the PF/VFVirtIO Capability register range andcertain PF/VF PCIe Capability registerranges are not visible to theConfiguration Intercept Interface (CII)and can still be issued by theapplication logic. Refer to the P-tileAvalon Streaming IP for PCI ExpressUser Guide for more details.

The design implementation for the VirtIOfeature of the P-tile Avalon Streaming IP hasbeen improved.

Resource utilization has been reducedfor the P-tile Avalon Streaming IPwhen VirtIO is enabled.

The unconstrained clocks issue in the P-tileAvalon Streaming IP has been fixed.

This fix allows you to run acomprehensive timing analysis with allthe required clocks constrained on thisIP.

Critical timing paths have been optimized forthe P-tile Avalon Streaming IP. The timingclosure issue when VirtIO is enabled has alsobeen addressed in this release.

Timing margins have been improvedfor the P-tile Avalon Streaming IP.

The 2048 VFs issue when VirtIO is enabled inthe P-tile Avalon Streaming IP has beenaddressed.

In 21.1, you can enable all 2048 VFswhen VirtIO is enabled.

The P-tile Avalon Memory-mapped IP doesnot export the legacy interrupt pin(intx_req_i) when the Enable LegacyInterrupts option is enabled in the IPParameter Editor.

The P-tile Avalon Memory-mapped IPdoes not support legacy interrupts inthis release. Use MSI or MSI-X insteadfor interrupts.


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Gen4x4/x4/x4/x4




Gen3x4/x4/x4/x4







Gen4x4/x4/x4/x4




Gen3x4/x4/x4/x4



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Gen4 x16 512-bit S C T H N/A S C T H N/A 350 MHz 350 MHz N/A

Gen4 x8/x8 512-bit S C T H N/A S C T H N/A 200 MHz 200 MHz N/A

Gen4 x4/x4/x4/x4256-bit N/A S C T H N/A N/A 200 MHz 200 MHz N/A




Note: The design example available in the 21.1 release supports the DMA mode with DataMovers.










Note: The design example available in the 21.1 release supports the DMA mode with DataMovers.





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Table 23. v3.1.0 2020.10.05


20.3 The BFM for Endpoint mode simulations isnot available in this release. It may beavailable in a future release.

Use a third-party BFM for Endpointmode simulations.

For the P-Tile Avalon Streaming IP,configurations with the Adapter enabled arenot available in this release.

For the P-Tile Avalon Streaming IP,Gen4 x8 512-bit and Gen4 x4 256-bitconfigurations are not available in thisrelease.

The Parameter Editor of the P-Tile AvalonStreaming IP indicates support for a 125 MHzapplication clock frequency in someconfigurations of the IP. However, thisfrequency is not supported. If selected, theIP will be generated using a 250 MHzapplication clock.

For more details, refer to the followingentry in the Intel Knowledge Basepage: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/ip/2020/when-using-the-intel--fpga-p-tile-avalon-streaming-ip-for-pci--e.html






Gen4x4/x4/x4/x4




Gen3x4/x4/x4/x4



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https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/ip/2020/when-using-the-intel--fpga-p-tile-avalon-streaming-ip-for-pci--e.html












Gen4x4/x4/x4/x4




Gen3x4/x4/x4/x4














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Table 28. v3.0.0 2020.07.10


20.2 The VirtIO feature has timing issues in thisrelease of Intel Quartus Prime.

Only compilation and simulation aresupported for the VirtIO feature in thisrelease.

The Eye Plot feature in the Debug Toolkit isonly available for Channel 0.

Eye Plot support for Channels otherthan Channel 0 may be available in afuture release of Intel Quartus Prime.

continued...


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The P-Tile Avalon-ST and Avalon-MM IPs forPCIe support the PCIe Link Inspector in thisrelease.

The PCIe Link Inspector allows you tomonitor the PCIe link status at thePhysical, Data Link and TransactionLayers.

The P-Tile Avalon-ST IP adds Modelsimsupport for design example simulation in thisrelease.

The P-Tile Avalon-ST IP can supportModelsim and VCS simulators in the20.2 release of Intel Quartus Prime.The P-Tile Avalon-MM IP still onlysupports VCS. Other simulators maybe supported in a future release.

The independent pin_perst option is nolonger available in the P-Tile Avalon-ST IP inthis release.

When a x16 port is bifurcated into twox8 ports, a reset via pin_perstimpacts both x8 ports.

The P-Tile Avalon-MM IP for PCIe does notsupport 10-bit tags for the x16 core in thisrelease.

The x16 core of the P-Tile Avalon-MMIP for PCIe only supports up to 64outstanding Non-Posted Requests(NPRs) in this release.

The Root Port (RP) BFM for Endpointconfigurations is not available in this release.It may be available in a future release.

Use a third-party BFM to simulate theP-Tile Root Port design examples.

Configurations with the Adapter enabled arenot available in this release.

Gen4 x8, 512-bit and Gen4 x4 256-bitconfigurations are not available in thisrelease.

You cannot change the PCIe SerDes pinallocations for the P-Tile Avalon-ST andAvalon-MM IPs for PCIe in the Intel QuartusPrime project.

To ease PCB routing, you can takeadvantage of the lane reversal andpolarity inversion features supportedby the P-Tile Avalon-ST and Avalon-MMIPs for PCIe.


Configuration



Gen4 x16 S C T H S C T H S C T H S C T H N/A N/A 400 MHz 400 MHz N/A

Gen4x8/x8

256-bitS C T H N/A S C T H S C T H N/A N/A 400 MHz 400 MHz N/A

Gen4x4/x4/x4/x4 128-

bit

N/A S C T H S C T H N/A N/A N/A 400 MHz 400 MHz N/A

Gen3 x16 S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz

Gen3x8/x8 S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz

Gen3x4/x4/x4/

x4N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz


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Configuration




Gen4x8/x8


Gen4x4/x4/x4/x4 128-

bit




Gen3x4/x4/x4/



Configuration



Gen4 x16 S C T H (**) S C T H (*) (**) 350 MHz 350 MHz N/A

Gen4 x8/x8 S C T H N/A S C T H (*) N/A 350 MHz 350 MHz N/A

Gen4x4/x4/x4/x4 N/A S C T H N/A (**) 350 MHz 350 MHz N/A




Note: (*) The design example available in the 20.2 release supports the DMA mode withData Movers. A design example supporting the Bursting Slave mode may be availablein a future release.

Note: (**) This support may be available in a future release of Intel Quartus Prime.


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Configuration

















Table 33. v2.0.0 2020.04.20


20.1 The VirtIO feature has timing issues in thisrelease of Intel Quartus Prime.


The Eye Plot feature in the Debug Toolkit isonly available for Channel 0.

Eye Plot support for Channels otherthan Channel 0 may be available in afuture release of Intel Quartus Prime.

The P-Tile Avalon-ST and Avalon-MM IPs forPCIe only support VCS for design examplesimulation in this release.

Use VCS for design example simulationin the 20.1 release of Intel QuartusPrime. Other simulators may besupported in a future release.

continued...


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The P-Tile Avalon-ST and Avalon-MM IPs forPCIe do not support parallel PIPE simulationsin this release.

Only Serial data interface simulationsare supported in the 20.1 release ofIntel Quartus Prime, which will resultin longer simulation time. Parallel PIPEsimulations may be supported in afuture release.

The independent pin_perst option is onlyavailable in the P-Tile Avalon-ST IP in thisrelease.

For guidelines on implementing twoindependent pin_perst, contactFactory Applications.

The P-Tile BFM is not supported in thisrelease. It may be available in a futurerelease.

Use a third-party BFM to simulate theP-Tile design examples.

Parity is supported in this release. However,it is not supported when the Adapter isenabled.

Configurations with the Adapterenabled (i.e., Gen4 x8, 512-bit andGen4 x4 256-bit) do not have paritysupport.


Configuration




Gen4x8/x8


Gen4x8/x8

512-bitS C T N/A S C T H S C T N/A N/A 400 MHz

(*)400 MHz

(*) N/A

Gen4x4/x4/x4/x4 128-

bit


Gen4x4/x4/x4/x4 256-

bit

N/A S C T H S C T H N/A N/A N/A 400 MHz(*)

400 MHz(*) N/A



Gen3x4/x4/x4/


Note: (*) User Application will see a clock frequency of 200 MHz with double the data buswidth.


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Configuration




Gen4x8/x8


Gen4x8/x8

512-bitS C T N/A S C T H S C T N/A N/A 500 MHz

(*)500 MHz

(*) N/A

Gen4x4/x4/x4/x4 128-

bit


Gen4x4/x4/x4/x4 256-

bit

N/A S C T H S C T H N/A N/A N/A 500 MHz(*)

500 MHz(*) N/A

Gen3 x16 S C T H S C T H S C T H C T H N/A N/A 250 MHz 250 MHz 250 MHz

Gen3x8/x8 S C N/A S C T C N/A N/A 250 MHz 250 MHz 250 MHz

Gen3x4/x4/x4/


Note: (*) User Application will see a clock frequency of 250 MHz with double the data buswidth.


Configuration



Gen4 x16 S C (**) (**) (**) (**) (**) N/A

Gen4 x8/x8 (**) N/A (**) N/A (**) (**) N/A

Gen4x4/x4/x4/x4 N/A (**) N/A (**) (**) (**) N/A

Gen3 x16 S C T H (**) C T H (*) (**) 250 MHz 250 MHz N/A

Gen3 x8/x8 (**) N/A (**) N/A (**) (**) N/A

Gen3x4/x4/x4/x4 N/A (**) N/A (**) (**) (**) N/A



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Configuration



Gen4 x16 S C (**) (**) (**) (**) (**) N/A

Gen4 x8/x8 (**) N/A (**) N/A (**) (**) N/A

Gen4x4/x4/x4/x4 N/A (**) N/A (**) (**) (**) N/A

Gen3 x16 S C T (**) C T (*) (**) 250 MHz 250 MHz N/A

Gen3 x8/x8 (**) N/A (**) N/A (**) (**) N/A

Gen3x4/x4/x4/x4 N/A (**) N/A (**) (**) (**) N/A





The IP versioning scheme (X.Y.Z) number changes from one software version toanother. A change in:




Table 38. v1.1.0 2019.12.16


19.4 The VirtIO feature still has timing issues inthis release of Intel Quartus Prime.


An SR-IOV design example has been addedfor the P-Tile Avalon-ST IP for PCIe.

This design example supports Gen3x16 and Gen4 x16 Endpointconfigurations.

continued...


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No P-Tile IP upgrade is supported in the 19.4release of Intel Quartus Prime.

Users cannot upgrade a 19.3 P-TileAvalon-ST or Avalon-MM IP to a 19.4version.

The P-Tile Avalon-MM IP for PCIe does notsupport design example simulation in thisrelease.

The P-Tile Avalon-MM IP for PCIe maysupport design example simulation in afuture release of Intel Quartus Prime.

A high-bandwidth Adapter has beenintroduced for the P-Tile Avalon Streaming IP.

This Adapter allows the applicationlogic to run Gen4 x8 and Gen4 x4configurations with an application clockfrequency of 250 MHz by doubling theAvalon Streaming data bus width. TheAdapter is enabled automatically byIntel Quartus Prime when either the512-bit Gen4 x8 or 256-bit Gen4 x4configuration is selected.

The P-Tile Avalon Streaming IP for PCIExpress does not support parity protectionfor the RX and TX Avalon Streaminginterfaces in this release of Intel QuartusPrime.

Parity protection for the RX and TXAvalon Streaming interfaces will besupported in a future release of IntelQuartus Prime.

1.11. P-Tile IP for PCI Express IP Cores v19.3

Table 39. 19.3 September 2019

Description Impact

Initial release of the P-Tile Avalon-MM IP for PCI Express.This IP supports both Intel Stratix 10 DX and Intel Agilexdevices.

Added this new IP component to enable Avalon-MM supportfor P-Tile in the Gen3 x16 for Endpoint configuration. Thesupport level is Advance.Other configurations may be supported in a future releaseof Intel Quartus Prime.

The P-Tile Avalon-MM IP for PCI Express includes internalRead Data Mover and Write Data Mover to support DMAoperations.

This IP includes Data Mover interfaces to communicate withan external DMA Controller. The Intel Quartus Prime 19.3release includes a PCIe DMA design example, whichprovides a DMA Controller that can interface with theinternal Data Movers of the P-Tile Avalon-MM IP for PCIExpress to perform DMA operations. Alternatively, you canbuild your custom DMA Controller in your application logic.

Added support for the Debug Toolkit for both P-Tile Avalon-MM and P-Tile Avalon-ST IPs for PCI Express.

The P-Tile Debug Toolkit is a System Console-based toolthat provides real-time control, monitoring and debuggingof the PCIe links at the Physical Layer.

Clocking topologies with Separate Reference Clockarchitectures are supported in this release.

P-Tile IPs for PCI Express support the Separate ReferenceClock with no Spread Spectrum Clocking (SRNS)architecture by default, and the Separate Reference Clockwith Independent Spread Spectrum (SRIS) Clockingarchitecture, which can be enabled from the IP ParameterEditor.

The P-Tile Avalon-MM IP for PCI Express does not supportthe Interrupt Interface, Error Interface and ConfigurationIntercept Interface in this release.

The P-Tile Avalon-ST IP for PCI Express does support theseinterfaces.The P-Tile Avalon-MM IP for PCI Express may support theseinterfaces in a future release of Intel Quartus Prime.

The P-Tile Avalon-MM IP for PCI Express does not supportdesign example simulation in this release.

The P-Tile Avalon-ST IP for PCI Express does support designexample simulation.The P-Tile Avalon-MM IP for PCI Express may support designexample simulation in a future release of Intel QuartusPrime.

continued...


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Description Impact

You can still simulate the P-Tile Avalon-MM IP for PCIExpress by using a third-party Bus Functional Model (BFM).

Related Information

• P-Tile Avalon Streaming (ST) IP for PCI Express User GuideFor the Avalon-ST Interface to the Application Layer.

• Errata for the Hard IP for PCI Express IP Core in the Knowledge Base

• Introduction to Intel FPGA IP CoresProvides general information about all Intel FPGA IP cores, includingparameterizing, generating, upgrading, and simulating IP cores.

1.12. P-Tile IP for PCI Express IP Cores v19.2

Table 40. 19.2 June 2019

Description Impact

Initial release of the P-Tile Avalon-ST IP for PCI Express.This IP supports both Intel Stratix 10 DX and Intel Agilexdevices.

Added this new IP component to enable Avalon-ST nativesupport for P-Tile in the Gen3 x16/x8 for Endpoint, Gen4x16/x8 for Endpoint, Gen3 x16/x4 for Root Port and Gen4x16/x4 for Root Port configurations. The support level isAdvance.Other configurations can be supported through linknegotiations.

Support for Single-Root I/O Virtualization (SR-IOV) isavailable.

The P-Tile Avalon-ST IP for PCI Express supports up to 8physical functions (PFs) and 2048 virtual functions (VFs) inSR-IOV mode.

Port bifurcation is supported. This IP can support one x16 or two x8 interfaces in Endpointmode, and four x4 interfaces in Root Port mode.

TLP Bypass mode is supported. This IP supports a TLP Bypass mode for both upstream anddownstream ports, thus allowing the implementation ofadvanced features such as:• The upstream port or downstream port of a switch.• A custom implementation of a Transaction Layer to meet

specific user requirements.

1.13. P-Tile IPs for PCI Express User Guide Archives

For the latest and previous versions of these user guides, refer to the P-Tile AvalonStreaming IP for PCI Express User Guide and the P-Tile Avalon Memory-mapped IP forPCI Express User Guide. If an IP or software version is not listed, the user guide forthe previous IP or software version applies.


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https://www.intel.com/content/www/us/en/docs/programmable/683059/21-4-7-0-0/introduction.html

https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html#sort=%40articlepublisheddate%20descending

https://www.intel.com/content/www/us/en/docs/programmable/683102/21-3/introduction-to-cores.html






p-tile ip for pci express* ip core release notes

Documents