oxide-oxide bond processing and characterization for … · 2019. 10. 1. · fraunhofer institute...
TRANSCRIPT
© Fraunhofer IZM
17.09.2019
OXIDE-OXIDE BOND PROCESSING AND CHARACTERIZATION FOR CHIP-TO-CHIP CU-SIO2 HYBRID BONDINGSTREAM WP5: TECHNOLOGY INTEGRATION
Sarah Busef (ESR 14) Supervisor: Thomas Fritzsch
Fraunhofer Institute for Reliability and Microintegration, Dept. Wafer Level System Integration (WLSI)
Smart Sensor Technologies and Training for Radiation Enhanced Applications and Measurements (STREAM) is a project funded by the European Commission under the Horizon 2020 Framework Program aunder the Grant Agreement no 675587 (January 2016 – Present)
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Sarah Busef, Thomas Fritzsch, WLSI
Agenda Introduction
Motivation
Bonding Technologies
Process
Hybrid Oxide-Metal-Bonding - Mechanism and Process Flow
Chip Handling and Surface Preparation
Bonding and Evaluation
Evaluation Methods
Surface Activation – Contact Angle Measurement
Bond Result – Scanning Accoustic Microscopy
Surface Planarity – Atomic Force Microscopy
Chip and Wafer Processing
Hybrid Bonding Evaluation Design
Chemical Mechanical Polishing (CMP)
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Hybridization of Pixel Detector Modules
Readout Chip
Pixel Sensor Chip
Sensor Pixel
Communication, Data processing
Flip Chip Interconnection
Back Side Electrode
CMS ITK Module
One or more readout chips are bonded onto one sensor die
Every individual sensor pixel bonded to one readout cell by a solder bump
ATLAS FE-I4 IBL Module AGIPD x-ray camera @ XFEL
Applications:
Hybrid pixel detector modules are part of
the inner tracking detectors of ATLAS and CMS
x-ray imaging cameras in synchrotron and free electron laser facilities
diagnostic tools for x-ray medicine
Don‘t be confused: Hybrid Pixel Detector Module doesn‘t mean Hybrid-Oxide-Metal-Bonding!
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Reduction of interconnection pitch and structure size
Solder balls for PCB assembly:
Pitch 500…300µm
Ball size: 300…150µm
Material: BGA Solder balls
Fine pitch bumping:
Pitch 100…50µm
Bump size: 50…25µm
Material: Solder bumps, pillar bumps with solder cap
50µm pitch
Solder µ-bump bonding:
Pitch 50…20µm
Bump size: 25…12µm
Material: Solder bumps, pillar bumps with solder cap
25µm pitch
Sub-10µ-pitch:
Pitch 10… < 2µm
Pad size: 6…1µm
Material: planarized Cu pads; Cu-SiO2 Hybrid bonding
Cu/SiO2
Cu/SiO2
Tessera DBI ®
Bonding Technologies
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Hybrid Oxide-Metal-Bonding: Motivation
Ultra fine pitch
Compatible with 3D integration
Low bonding temperature
Increased reliability
Reduced packaging volume
Increased spatial resolution
Fast signal processing
Hybrid Oxide-Metal-Bonding:
Wafer to wafer bonding XPERI DBI-Process
Chip to chip bonding for heterogeneous integration: ???
Courtesy of Dr. Hermann Oppermann (Fraunhofer IZM)
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Sarah Busef, Thomas Fritzsch, WLSI
Hybrid-Oxide-Metal-Bonding: Mechanism
Wafer Surface: SiO2 on CMOS with planarized metal interconnects (i.e. Cu)
Activation of oxide surface
Hydrophilic oxide-oxide bonding
Cu-Cu inter-diffusion during annealing step
I. Hybrid Bonding
• Room-temperature
• No pressure
• Instant
II. Post-bond Annealing
• Up to 200 C
• 2 hours or less
sub-nm roughness contaminant-free activated
critical surface criteria:
CMOS
CMOS
SiO2
SiO2
Cu
Cu
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Sarah Busef, Thomas Fritzsch, WLSI
Hybrid Bonding Microfabrication – Project Planning
Characterization
Chip-level, thermal oxide
Phase II
Chip preparationaccording to phase I
Chip bonding
Chip bondqualification
Concept Development
Phase I
Process Development
Single chip handling
Chip surface cleaning
Surface activation
Qualification methods
Planarization
Wafer-level, PE-CVD oxide
Phase III
Wafer preparationwith oxide deposition
CMP process at waferlevel
Qualification of oxideCMP
Chip bond test andqualification
Concept Extension
Wafer/Chip-level, Cu + PE-CVD oxide
Phase IV
Wafer preparationoxide + Cu deposition
CMP process at waferlevel
Qualification of Cu CMP
Wafer preparation withAl + oxide + Cudeposition
Chip bond test andqualification
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Sarah Busef, Thomas Fritzsch, WLSI
DicingDicing
Chip HandlingChip Handling
CleanClean
ActivateActivate
BondBond
AnnealAnneal
Phase I: Hybrid Bonding Microfabrication - Process Flow
Oxide Application/GrowthOxide Application/Growth
Lithographic Dry EtchLithographic Dry Etch
Plating Base SputterPlating Base Sputter
Metal ElectrodepositionMetal Electrodeposition
Plating Base EtchPlating Base Etch
Metal, Oxide Chemical Mechanical Planarization (CMP)
Metal, Oxide Chemical Mechanical Planarization (CMP)
Si + CMOS
SiO2
Si + CMOS
SiO2 SiO2
Mask Mask
Si + CMOS
SiO2 SiO2
Si + CMOS
SiO2 SiO2
Si + CMOS
SiO2 SiO2
MaskMask
Si + CMOS
SiO2 SiO2
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DicingDicing
Chip HandlingChip Handling
CleanClean
ActivateActivate
BondBond
AnnealAnneal
Phase I: Chip Handling: Preventative Measures
Dicing stage generates most particle contaminants that are not easily removed
Oxide chipping and non-planarity caused by dicing prevent bonding
pro
cess com
plexity
SiSiO2
protective resistapplication
Si
ResistSiO2
etching of dicing street
dicing
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Phase I: Chip Handling Tool
Contact-less chip cleaning, activation, bonding and storage
100 mm (4”) modular setup, baseplate and stacked chip cage
compatible with wafer processing equipment (cleaning, activation, P&P)
DicingDicing
Chip HandlingChip Handling
CleanClean
ActivateActivate
BondBond
AnnealAnneal
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Phase I/II: Chip Surface Cleaning
Isopropanol Cascade Clean RCA SC-1
DicingDicing
Chip HandlingChip Handling
CleanClean
ActivateActivate
BondBond
AnnealAnnealIsoprop. / DI Water Clean Alkaline Chemical Clean Plasma Surface Treatment
Wet Chemical Cleaning Plasma Cleaning
RCA SC-1: high-temperature, water-based solution of hydrogen peroxide and ammonium hydroxide
Reactive Ion Etching (RIE) usingAr, SF6, O2, H2-Plasma
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Hydrophilicity increases with H2 gas phase content
Hydrophilic up to 96 h (4 d) after activation
Phase I/II: Evaluating Surface Activation: Contact Angle Measurement
0 24 48 72 96-10
-5
0
5
10
15
20
25
30
35
Con
tact
Ang
le (°
)
Time (h)
0h 120h
0
5
10
15
20
25
30 Activate 1 Activate 2 No Activate
Con
tact
Ang
le (°
)
Time
Activate 1: H2-Basis
Activate 2: O2-Basis
Plasma activated surface:
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Phase II: Chip-to-Chip Oxide Bonding
200mm Si wafer with 1µm thermal oxide layer
Dicing of 3 chip sizes
3 mm
6 mm
12 mm
Surface cleaning
Surface activation
Chip To Chip Bonding
Annealing
bond toolChip on carrier
SEM image of oxide-oxide bond interface
Shear testing:
3x3mm² sample
Shear strength ~25 MPa
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Sarah Busef, Thomas Fritzsch, WLSI
Phase II: Evaluating Bond Qualility with Scanning Acoustic Microscopy (C-SAM)
Case 1:
i.e. Water to Si
Case 2:
i.e. SiO2 to air (void)
Case 3:
i.e. Si to Si
Z = *V
: material density
V: ultrasonic velocity (Ns/m3)
Ultrasonic transducer frequency: 10MHz…230MHz
Acoustic Impedance Z
© Sonoscan
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Sarah Busef, Thomas Fritzsch, WLSI
Phase II: Evaluating Bond Qualility Using Scanning Acoustic Microscopy (SAM)
Analysis of bond area from binary image for quantitative comparison of bond quality
Void Quantity & SizeBonded Area %
87%
13%
12 mm
<
1
Scanning Acoustic Microscopy (C-SAM): SAM Result Analisys:
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Phase II: Evaluating Bond Quality: Scanning Acoustic MicroscopyCleaning Comparison
Direct correlation between cleaning efficiency and bonded area [%]
RCA SC-1: > 85%Isopropanol Bath: < 25% Ultrasonic Bath: > 95%
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Sarah Busef, Thomas Fritzsch, WLSI
Phase II: Evaluating Bond Quality: Scanning Acoustic Microscopy
Image software based void analysis
Highest count void diameter in 50-100 µm bin
Literature: void/particle ratio 10.000/1
Corresponding particle size to generate void:
5 – 10 nm (ProSys, Inc., CEA, EV Group)
Higher resolution surface inspection system (30 nm)
Particle contamination prevention strategy0 100 200 300 400 500
0
5
10
15
20
25
30
Cou
nt
Void diameter (µm)
© KLA-Tencor Corp.
C-SAM image of oxide-oxide bonded chip couple:
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Sarah Busef, Thomas Fritzsch, WLSI
Phase III: Evaluating Planarity by Atomic Force Microscopy (AFM)
Scanning probe microscopy; non-contact mode
Sub-nanometre atomic roughness critical (thermal oxide Rq < 0.2 nm)
Evaluation of oxide roughness, Cu roughness, Cu dishing
Rq = 0.143 nm
Example Measurement plots on thermal oxide layer:
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Phase III: Wafer Level Processes – Qualification of Oxide Roughness
development effort on CMP with following specifications targeted:Low SiO2 roughness in the range of less than 0.5nm
First wafer batch with PECVD SiO2 SiO2 CMP
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Example of AFM measurement of SiO2 Rq roughness(Ref is a blank Si Wafer, PECVD is after oxide depositionand PECVD CMP after oxide-CMP)
CMP – Chemical Mechanical Polishing:
Step 1: Deposition ofCMP-Slurry
Step 2: Chemical MechanicalPolishing
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Phase IV: Wafer Level Processes – Qualification of Cu Roughness and Dishing
development effort on CMP with following specifications targeted:Controlled Cu Dishing in the range of 5nm required
Second wafer batch with hybrid Interface study Cu-CMP
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Example of AFM measurement: Cu dishing after CMP ~ 30nmparameter optimization ongoing
Sample: Cu pads with PE-CVD oxideafter CMP
dishing
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Sarah Busef, Thomas Fritzsch, WLSI
Phase IV: Chip-to-Chip Hybrid Bonding Test Design
200mm wafer layout:
Chip design right
Substrate design left
Al + Cu + PE-CVD SiO2
Pitch: 10 µm
Pad Diameter: 5 µm
Chip-level FC fiducials
Chip-on-substrate Kelvin structures
Suitable for electrical resistance probe and capacity measurement
Bottom part
(„substrates“)
Top part
(„chips“)
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Phase IV: Chip-to-Chip Hybrid Bonding – Wafer Preparation
Status:
Aluminum lines patterned
Oxide deposition
Oxide-CMP
Oxide Etch-Passivation Opening
Cu deposition
Cu-CMP
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Summary
Proof of concept for first phase hydrophilic SiO2-SiO2 bonding
Chip handling for particle prevention and sample ramp up
Evaluation of wafer cleaning, activation and bonding using contact angle measurement, Scanning Acoustic Microscopy (SAM) and Atomic Force Microscopy (AFM),
Key findings
sub-nanometer surface roughness
active surface up to 96 hours
consistent bond area of over 85%
Outlook:
Addressing limitations: particle contamination and reliability of sub-nm measurements
Optimization of CMP process
Preparation of wafers for PE-CVD oxide and Cu + PE-CVD oxide for hybrid-oxide-metal-bonding
© Fraunhofer IZM
17.09.2019
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