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material prepared by: MUKESH BOHRA

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BOOLEAN ALGEBRA

Boolean Algebra is a set of rules, laws and theorems by which logical operations can be

mathematically expressed. This algebra was first introduced by “George Boole”, an English

mathematician.

Boolean algebra deals with boolean variables (characters allowed A-Z, a-z), the operators

. (AND) , + (OR), and ’ (NOT) and the symbols ( ) and =.

Basic Theorems/Properties of Boolean Algebra Theorem/Law/Axioms Over (.) Over (+)

1. Properties of 0 x.0 = 0 x+0 = x

2. Properties of 1 x.1 = x x+1 = 1

3. Indempotence Law (Identity Law) x.x = x x+x = x

4. Complementarity Law x.x’ = 0 x+x’ = 1

5. Commutative Law x.y = y.x x+y = y+x

6. Associative Law x.(y.z) = (x.y).z x+(y+z) = (x+y)+z

7. Distributive Law x+(y.z) = (x+y).(x+z) x.(y+z) = xy+xz

8. Absorption Law (Redundance Law) x(x+y) = x x+xy = x

9. De-Morgan’s Law (x.y)' = x’+y’ (x+y)’ = x’.y’

10. Involution Law (Negation Law) (x’)’ = x

Principle of Duality: It states that starting with a boolean relation; another boolean relation can be derived by:

1) Changing each OR (+) sign to an AND (.) sign.

2) Changing each AND (.) to an OR (+) sign.

3) Replacing each 0 by1 & vice-versa.

e.g. The Dual of an expression x+xy = x is x.(x+y) = x

Tautology Fallacy If the result of a boolean expression is

always TRUE or 1, it is called a tautology.

e.g. x + 1 is a tautology.

If the result of a boolean expression is

always FALSE or 0, it is called Fallacy.

e.g. x . 0 is a fallacy.

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LOGIC GATES

Logic gates are small electronic circuits that work on digital signals. Basically logic gates

are of two types:

Basic Gates Derived Gates

AND gate NAND gate OR gate NOR gate

NOT gate X-OR gate

X-NOR gate

BASIC GATES:

1. AND gate

Operation : logical multiplication

Symbol : . or ^

Graphical symbol :

A

i/p lines Y=A.B

B o/p line

Truth Table:

INPUT OUTPUT

A B Y= A.B

0 0 0

0 1 0

1 0 0

1 1 1

It is concluded from the above truth table that; the output of an AND gate is TRUE

(i.e. 1) only when both the inputs are TRUE, and in all other cases it is always FALSE.

2. OR gate

Operation : logical addition

Symbol : + or v

Graphical symbol :

A

i/p lines Y = A + B

B o/p line

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Truth Table:

INPUT OUTPUT

A B Y= A+B

0 0 0

0 1 1

1 0 1

1 1 1

It is concluded from the above truth table that; the output of an OR gate is FALSE

(i.e. 0) only when both the inputs are FALSE, and in all other cases it is always TRUE.

3. NOT gate ( Inverter)

Operation : Compliment

Symbol : „ or

Graphical symbol :

i/p line A Y = A‟ (or A ) o/p line

Truth Table:

Input output

A Y = A‟

0 1

1 0

It is concluded from the above truth table that; the NOT gate simply inverts the input.

DERIVED GATES: ( obtained by combining two or more basic gates)

1. NAND gate: [compliment of AND gate]

It is obtained by complimenting the output of AND gate.

A A.B

Y = A.B

B

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Graphical symbol:

A

i/p lines Y=A.B

B o/p line

Truth Table:

INPUT

A.B

OUTPUT

A B Y= A.B

0 0 0 1

0 1 0 1

1 0 0 1

1 1 1 0

It is concluded from the above truth table that; the output of an NAND gate is FALSE

(i.e. 0) only when both the inputs are TRUE, and in all other cases it is always TRUE.

2. NOR gate: [compliment of OR gate]

It is obtained by complimenting the output of OR gate.

A A+B

Y = A + B

B

Graphical symbol:

A

i/p lines Y = A + B

B o/p line

INPUT

A+B

OUTPUT

A B Y= A+B

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

It is concluded from the above truth table that; the output of an NOR gate is TRUE

(i.e. 1) only when both the inputs are FALSE, and in all other cases it is always FALSE.

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3. X-OR gate:

It is a special case in OR gate. It is obtained as:

A‟

A A‟B

i/p

Y=A + B

o/p

B AB‟

B‟

Graphical symbol:

A

i/p lines Y = A + B = A’B + AB’

B o/p line

Truth Table:

INPUT

A‟

B‟

A‟B

AB‟

OUTPUT

A B Y = A + B

= A’B + AB’

0 0 1 1 0 0 0

0 1 1 0 1 0 1

1 0 0 1 0 1 1

1 1 0 0 0 0 0

It is concluded from the above truth table that; the output of an X-OR gate is FALSE

(i.e. 0) when both the inputs are SAME, and in all other cases it is always TRUE.

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4. X-NOR gate:

It is obtained by complementing the output of X-OR gate.

A‟

A A‟B

i/p A + B Y=A . B

o/p

B AB‟

B‟

Graphical symbol:

A

i/p lines Y = A . B = AB + A’B’

B o/p line

Truth Table:

INPUT

A‟

B‟

A‟B

AB‟

AB‟ + AB‟

OUTPUT

A B Y = A . B

= AB + A’B’

0 0 1 1 0 0 0 1

0 1 1 0 1 0 1 0

1 0 0 1 0 1 1 0

1 1 0 0 0 0 0 1

It is concluded from the above truth table that; the output of an X-NOR gate is TRUE

(i.e. 1) when both the inputs are SAME, and in all other cases it is always FALSE.

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Universal gates: [ NAND & NOR ] NAND and NOR gates are known as universal gates because any other gate / any logic

circuit can be constructed using only NAND as well as only NOR.

i. Construction of basic gates using NAND gate:

1) NOT gate using NAND

A Y = A

2) AND gate using NAND

A A.B Y = A.B = A.B

B

3) OR gate using NAND

A

A

Y = A. B = A + B = A + B

B

B

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ii. Construction of basic gates using NOR gate:

1) NOT gate using NOR

Y = A

A

2) OR gate using NOR

A A+B Y = A+B = A+B

B

3) AND gate using NOR

A

A

Y = A + B = A . B = A . B

B

B

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Minimizing A Boolean Expression A given boolean expression can be minimized or reduced to a simpler form before

implementing it into a circuit. By doing so, we can remove complexities of a circuit to a

larger extent.

There are two methods of minimizing a boolean expression:

Algebraic method [using laws of boolean algebra]

Map method [using K-map]

K- MAP ( Karnaugh Map) K-map is a graphical arrangement of a truth-table in the form of a grid, which provides a

simplest & systematic way of minimizing a boolean expression.

Key Terms: Literal A single variable or its compliment. Gray Code A binary code in which each successive number differs only in one

place. Canonical Form Standard SOP or Standard POS expressions where all variables/literals

are present in each term of the expression.

Maxterm SUM term containing sum of all the literals, with or without bar Minterm PRODUCT term containing product of all the literals, with or without

bar Points to remember while drawing a K-map:

1) In SOP; each minterm is marked as binary 1 in the corresponding cell of the map.

In POS; each maxterm is marked as binary 0 in the corresponding cell of the map.

2) While grouping the cells, check firstly for large groups. i.e. check first for a group

of 16cells, then 8cells, then 4cells, then 2cells and lastly for 1cell. At each step

don’t forget to roll/fold the map.

3) Redundant groups should not be taken.

4) For each group, take the common row-variables and the column-variables and

multiply them to get the simplified minterm (or add them to get the simplified

maxterm).

[In SOP: 0-complemented; 1-uncomplemeted]

[In POS: 0-uncomplemented; 1-complemeted]

Repeat the procedure for all the groups.

5) Finally, add all the minterms obtained (or multiply all the maxterms obtained) to get

the final minimized expression.

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EXAMPLE 1: Reduce the following Boolean Expression using K-map:

F(A, B, C, D) = ∑ (0, 1, 2, 4, 5, 6, 8, 10) [CBSE 2011]

Solution:

No. of variables = 4

Therefore, no of cells in the map= 24 = 16

So let‟s draw the K-map with 16 cells

g1 g2

CD

AB 00 01 11 10

00

01

11

10

g3

For group g1: it‟s a quad containing cells (m0, m1, m4, m5)

A=0 i.e A‟

C=0 i.e. C‟

Combining both the literals, we‟ll get the minterm

A‟C‟

1

m0

1

m1

m3

1

m2

1

m4

1

m5

m7

1

m6

m12

m13

m15

m14

1

m8

m9

m11

1

m10

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For group g2: it‟s a quad containing cells (m0, m2, m4, m6)

A=0 i.e A‟

A‟D‟

D=0 i.e D‟

For group g3: it‟s a quad (obtained on map folding) containing cells (m0, m2, m8, m10)

B=0 i.e B‟

B‟D‟

D=0 i.e D‟

Now, Combining the minterms obtained above; we‟ll get the reduced boolean exp. as:

F(A, B, C, D) = A‟C‟ + A‟D‟ + B‟D‟

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EXAMPLE 2: Minimize the following Boolean Expression using K-map:

F (K, L, M, N) = ∏ (1, 3, 4, 5, 6, 7, 12, 13)

Solution: Given expression is in POS form.

g2 g3 MN

KL 00 01 11 10

00

g1

01

11

10

For g1(Quad M4M5M12M13) : L’ + M

For g2(Quad M1M3M5M7) : K + N’

For g3(Quad M4M5M7M6) : K + L’

Combining the Maxterms, we’ll get the required reduced expression,

F (K, L, M, N)= (L’ + M)( K + N’)( K + L’)

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M0

0

M1

0

M3

M2

0

M4

0

M5

0

M7

0

M6

0

M12

0

M13

M15

M14

M8

M9

M11

M10

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Use of Boolean operators (AND, OR) in search engine queries

Boolean logic allows you to combine words and phrases into search statements to retrieve

documents from searchable databases.

Boolean logic consists of three logical operators:

OR

AND

NOT

i) OR logic: OR logic is most commonly used to search for synonymous terms or

concepts. It allows pages with at least one of the terms.

e.g. “college OR university” retrieves all the unique

records containing one term, the other term, or both of them.

Search terms Results

College 396,482

University 590,791

college OR university 819,214

The more terms or concepts we combine in a search with OR logic, the more results we will retrieve.

ii) AND logic: AND logic combined in a search retrieves the records in which BOTH of

the search terms are present.

e.g. “poverty AND crime” retrieves all the records

containing both the words poverty and logic. It must be noted that, it will not retrieve any records with only "poverty" or only "crime"

Search terms Results

poverty 76,342

crime 348,252

poverty AND crime 12,998

The more terms or concepts we combine in a search with AND logic, the fewer results we will retrieve.

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iii) NOT logic: NOT logic excludes records from your search results.

e.g. “cats NOT dogs” retrieves all the records

containing the word cats BUT no records are retrieved where the word dogs appears [even the overlapping area where both cats and dogs appear, will not be retrieved].

NOTE: Virtually all general search engines on the Web default to AND logic. In other

words, when you type words into a search box and generate your search, Boolean AND

logic is going on behind the scenes.

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Other Activities: Practice the following:

1) Minimization Problems using K-maps & algebraically also.

2) Realization of a given Boolean expression using:

Any Logic NAND NOR

gate(s) gate only gate only

3) To draw out the output from a logic circuit and vice-versa.

4) Writing SOP or POS forms from truth tables.

5) SOP to POS conversion and vice-versa.

6) Proving the laws or a given expression

Algebraically

Using truth–tables.

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