Optimization of the EE 432 Class Fabrication Process

May 07 – 16

Advisor/ClientProfessor Tuttle

Team MembersJerome Helbert

Leah HenzeRyan McDermottAlexander Smith

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Project Overview

•Objective: To improve the fabrication process used by students in the Microelectronics Fabrication lab (EE 432)

• The class creates transistors, resistors and capacitors using a series of boron and phosphorus diffusions

• Problems with current process:

• Badly scratched photolithography mask

• Low tolerance for alignment errors

• Non-ohmic contacts

• Non-uniform p-type diffusions

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Project Overview•Anticipated End Users

• EE 432 Course Instructors

• EE 432 Lab TAs

• Students in the EE 432 Class

•General Approach

• Photolithography Mask Set

• Design a new mask set

• Contacts and P-wells

• Identify solutions through experimentation, simulations and research

• Propose changes to the CMOS 70 fabrication process

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Project Milestones• Fall Semester

• P-wells and Contacts

• Perform characterization experiments

• Mask

• Select relevant devices for inclusion

• Produce mask design

• Fabricate mask (Contingent upon resource availability)

• Spring Semester

• P-wells and Contacts

• Continue experimentation

• Perform simulations using SUPREM

• Research contact materials4

Contact and P-Well Considerations

• Technical Requirements

• Contacts must be Ohmic

• To provide good contact with devices

• P-wells must be uniform across the wafer and provide appropriate background doping for the formation of devices

• The process must be consistent and repeatable between runs

• Economic Considerations

• Proposed process changes should not require expensive or unavailable equipment or materials

• There is not funding available to provide these materials to the fabrication class.

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Contact and P-Well Considerations

•End Use Consideration

• The final process should be compatible with the current CMOS 70 process

• Require a similar amount of time to complete as there is a finite amount of lab time each semester

• Make use the equipment available in the NSF lab

• Final process should be documented

• For use by the course instructor, detailing why changes were made

• For use by students

• Process instructions for use in the lab6

-0.06

-0.04

-0.02

0

0.02

0.04

0.06

-4 -3 -2 -1 0 1 2 3 4

Voltage (V)

Current (A)

Non-Ohmic Ohmic

Ohmic vs Non-Ohmic Contacts

• Ohmic contacts (shown in red) produce a linear relationship between voltage and current

• Non-Ohmic Contacts (shown in blue) cause unpredictable relationships between voltage and current

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Contact Experiment

• Tested the characteristics of the contacts on wafers of differing concentrations of dopants

• One heavily doped n-type wafer, one lightly doped n-type wafer, and one heavily doped p-type wafer

• The heavily doped n-type wafer exhibited excellent ohmic characteristics before and after sintering

• The lightly doped n-type wafer exhibited complete non-ohmic characteristics before and after sintering

• The heavily doped p-type wafer exhibited complete non-ohmic characteristics before sintering, but excellent ohmic characteristics after sintering

• The p-type wafer revealed a severe non-uniformity in the contact resistivity values

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Non-Uniformity of P-type Diffusions

Contact Resistivity

0.00E+00

5.00E-04

1.00E-03

1.50E-03

2.00E-03

2.50E-03

3.00E-03

DIE 1DIE 2DIE 3DIE 4DIE 5DIE 6DIE 7DIE 8DIE 9DIE 10DIE 11DIE 12DIE 13DIE 14DIE 15DIE 16

(ohm/cm2)

Die Arrangement

1 2 3 45 6 7 89 10 11 12

13 14 15 16

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Sintering Issues

• Sintering caused artifacts to form on some of the n-type contact wafers

• These did not affect device performance

• Could have been caused by water vapor underneath the metal layer

• Will be investigated in future experiments

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Boron Uniformity Experiment

• A new set of boron source wafers were prepared to replace the aging source wafers

• Source wafers recommend using a fully loaded wafer boat for deposition, the lab has usually used a partially loaded boat

• Compared diffusion characteristics of a fully loaded wafer boat to a partially loaded wafer boat

• Experiment showed slight improvement in uniformity using the fully loaded boat. A fully loaded wafer boat will be used from now on

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Boron Uniformity with Alternate Diffusion Boat

Experiment • Current wafer boats allowed

wafers to move around, this allowed gas flow patterns to vary

• Older wafer boats held wafers firmly in one place, creating a more uniform gas flow pattern

• Old wafer boat resulted in a more uniform diffusion. It will be used for boron depositions from now on

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Future Experiments• Contact Improvement Experiment

• Examine effect of thickened aluminum layer and increased etch time

• NMOS Diffusion Characterization Experiment

• Begin testing the effects of our process changes on simple devices

• Contact Material Experiment

• Test the effectiveness of alternative metals on contact performance

• Boron Deposition Parameter Variation Experiment

• Through experimentation, find the ideal deposition parameters for creating large and small boron diffusions

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Photolithography Mask Redesign

• Old mask characteristics

• N/PMOS sizes ranged from 10μm to 80μm in width

• Contains many devices that are unlikely to be test in EE 432 (NAND, NOR etc.)

• Much area was empty on the wafer

• Over time mask has developed scratches from lab use

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New Mask Constraints

• No more than the established 6 masks

• More masks would increase the cost

• No need to make the process more complicated with another step

• Die layout shall not exceed 3.81 cm by 3.81 cm to keep border region same on existing mask

• Must have large areas for proper vision through the mask while alignment

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New Mask Considerations

• Should the process switch to a PMOS process?+ This would eliminate the p-well thus removing a

current problem in the process

+ Simpler process would increase number of working devices

- Lab component of EE432 would be drastically shortened

- CMOS is the current standard in industry

• Decided to continue the CMOS process to keep EE 432 lab relevant to current industry process

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Device & Size Consideration

• Should all devices be kept?

+ Some devices are interesting to look at

- Are not typically tested in class and not required

- Take up room that could be used to fit more devices

• Decided to remove all but the NMOS, PMOS, BJT, capacitors, one inverter, one NAND, Van der Paws and TLM devices

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Cadence or L-Edit?

• Cadence+ More accessible on campus computers

- When a test design was imported it included an unneeded layer

• L-Edit+ Established program at MRC for mask generation

+ Old mask files were found

• Decided to use L-Edit since old files could easily be edited to form the new design

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Mask Design Changes

• Smallest device features (vias) were increased• Generator limit of 4 μm feature size

• Via size could be affecting the contact reliability

• Wafer layout• Die layout was changed to make it smaller to fit

more die per wafer

• New devices• A new set of N/PMOS with longer channel lengths

(20 & 40 μm) were included

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Design Summary• Contact/Diffusion Summary

• Increased aluminum thickness and increased etch time to improve contact reliability

• Using alternate wafer boat and using more guard wafers to create an even gas flow to increase diffusion uniformity

• Still need to perform more research and simulations on contacts and diffusions, as well as update process documentation

• Mask Redesign Summary

• Completed mask redesign

• Smaller die sizes allow for more die on each wafer

• Eliminated unused devices

• Increased tolerance of each device

• Still need to prepare documentation, fabricate masks, and test masks

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Design Evaluation

FunctionalityRelative

ImportanceEvaluation

ScoreResultant

Score

Documentation of new die layout 20% 100% 20.0%

Larger devices for more tolerance of errors 15% 90% 13.5%

Adequate "vision" to be able to do alignments 10% 90% 9.0%

Ability to be fabricated locally on MRC mask generator 5% 100% 5.0%

Ability to generate functional contacts 15% 95% 14.3%

Develop a process the creates uniform diffusions 5% 85% 4.3%

Process that generates devices with intended characteristics 10% 80% 8.0%

Update lab documentation to reflect changes in fabrication process 20% 95% 19.0%

Total 100% 93.0%

Requirement for a successful design 85%

The project has exceeded the requirement for a successful design by 8.0%

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