Optimal Design of H5 Bridge Based LLCConverter with Ultra-Wide Input Voltage

Range and Synchronous RectificationMingde Zhou, Student Member, IEEE, and Haoyu Wang, Senior Member, IEEE

School of Information Science and TechnologyShanghaiTech University, Shanghai, China

wanghy.shanghaitech@gmail.com

Abstract—The dilemma between wide input range andnarrow frequency band is a classic problem for the frequencymodulated LLC converters. Using reconfiguring bridge canmitigate this issue effectively. However, there is a lack of sys-tematic consideration in converter design and optimization.To address this challenge, this work introduces a six-modeLLC converter based on a reconfigurable H5 bridge, and sys-tematically presents its optimal design methodology in ultra-wide input range applications. The dual LLC resonant tanksare driven by identical switching frequency, and provide anormalized gain range from 1 to 5. Synchronized rectificationis employed on the secondary side to improve the gain andefficiency. The load distributions between dual tanks areanalyzed in detail. It indicates that the equivalent outputcapacitance of the primary-side MOSFETs is reduced. Thisenhances the ZVS performance and reduces the circulatingloss. The optimal design of transformer ensures a continuousvoltage gain over adjacent modes. A 48V, 500W laboratoryprototype is designed to validate the concept. The designedprototype is adapted to an 80V∼400V input range. Themaximum efficiency is 96.95%.

Index Terms—High step-down, LLC resonant converter,reconfigurable bridge, ultra-wide input range.

I. INTRODUCTION

The LLC converter is widely used as isolated dc/dcconverter due to its wide load range ZVS and highpower density [1]–[3]. In energy storage unit poweredelectronic systems with low supply voltage, LLC con-verter needs to be adapted to an ultra-wide input voltagerange and a high step-down ratio. In some systems, theenergy storage unit acts as buffer. Thus, the nominal out-put voltage is in the middle of output voltage range [4].Traditional LLC converter can not provide a good overallperformance. For those applications, the frequency ofLLC converter needs to swing over a wide range. Thisleads to increased conduction loss due to circulatingcurrent at low switching frequency. Conventionally, tosqueeze the frequency band, a small magnetizing induc-tance is necessary [3], [5]. This results in a high magne-tizing current, which leads to a large peak flux and theusage of high power-rating devices. In general, a narrowfrequency band and moderate magnetizing inductanceare expected in designing the ultra-wide input range LLCconverters.

To achieve the target of wide input voltage range,many researches have been done. Some focus on de-veloping LLC derived topologies. In [6], [7], an input-series-output-parallel converter is proposed. However,the number of control units scales up with the numberof modules. This incurs a high control complexity. In[8], a two-stage LLC-buck topology is proposed. ZVSis realized in the buck stage at high input voltage.Nevertheless, with the decrease of input voltage, the ZVSof buck stage tends to get lost.

Another way to widen the input voltage range isusing multi-mode converters. In [9], a reconfigurableLLC converter with dual bridges is proposed. It uses sixMOSFETs to provide two bridge modes. It comes withhigh cost and low reliability. In [10], an LLC topologywith two transformers and four modes is proposed.However, this technique is unsuitable for high step-down usages. When both transformers are enabled, theauxiliary MOSFETs suffer from high voltage stresses. In[11], we propose a modified four-mode gain LLC con-verter using a reconfigurable H5 bridge. Furthermore,in [12], the four-mode gain is extended into a six-modegain profile by introducing an asymmetric resonant tank.However, they are targeted for wide output range appli-cations and there is a lack of systematic analysis.

This work extended the H5 bridge based LLC topol-ogy into ultra wide input range applications. Synchro-nized rectification is enforced to improve the efficiencyperformance under low voltage and high current. Theschematic of the proposed converter is plotted in Fig.1. To tolerant the mismatch between dual tanks, seriescapacitors are added to the secondary side of dual tanks.Analysis and modeling of H5 topology are illustrated.Load distribution between dual tanks is analyzed. Op-timal design methodology for transformers to evenlycover the voltage range is shown.

II. MODE CONFIGURATION

The converter uses a re-configurable bridge to achievewide gain range. It has six operation modes. Each modecan works independently at its designed region. Thedetailed switch patterns are shown in Fig. 2.

978-1-7281-4829-8/20/$31.00 ©2020 IEEE 2073

Q5

Q2Q1

Q4Q3

LmA

LmB

TA

nA:1:1Vin

a

c

b

nB:1:1

isecCrA LrA

irAvCrA

CrB LrB

irBvCrB

TBCoB

vA

vB

VoA

VoB

SR1

SR2

SR4

SR3

RoVoVo

RoVo

RoVo

CoACoA

CoCo

Fig. 1. Schematic of the H5 bridge based LLC converter.

In Mode 1, the inverter stage works as half bridge (HB)for resonant tank A (RTA) and idle state for resonanttank B (RTB). In Mode 2, the inverter stage works as HBfor RTB and idle state for RTA. In Mode 3, the inverterstage works as HB for both RTA and RTB . In Mode 4,the inverter stage works as HB for RTB and full bridge(FB) for RTA. In Mode 5, the inverter stage works as HBfor RTA and FB for RTB . In Mode 6, the inverter stageworks as FB for both RTA and RTB .

Mode 1 Mode 2 Mode 3

ir,Bt

ir,At

vgs2

vgs1,3

t

t

t

vgs5

vgs4

0

0

0

0

0

ir,B

t

ir,At

vgs4

vgs1,5

t

t

t

vgs2

vgs30

0

0

0

0

ir,Bt

t

ir,A

vgs2

vgs1t

t

t

vgs3,5

0

0

0

0

0

vgs4

Mode 4

ir,Bt

ir,At

vgs2,5

vgs1,4

t

t

t

vgs3

0

0

0

0

0

Mode 4

ir,Bt

ir,At

vgs2,5

vgs1,4

t

t

t

vgs3

0

0

0

0

0

Mode 5

ir,B t

ir,At

vgs1t

t

t

vgs4,5

vgs2,3

0

0

0

0

0

Mode 5

ir,B t

ir,At

vgs1t

t

t

vgs4,5

vgs2,3

0

0

0

0

0

Mode 6

ir,B

t

ir,At

vgs1,4

t

t

t

vgs5

vgs2,3

0

0

0

0

0

Mode 6

ir,B

t

ir,At

vgs1,4

t

t

t

vgs5

vgs2,3

0

0

0

0

0

Fig. 2. Key steady state waveforms in different modes.

Cr,ALr,A

Lm,A

nA:1

vA

Cr,BLr,B

Lm,BvB

nB:1

RL,BRL,Bvo,B RL,Bvo,B RL,Bvo,B

RL,ARL,Avo,A RL,Avo,A RL,Avo,A

Fig. 3. Two resonant tanks model.

TABLE ISUMMARY OF MODE CONFIGURATIONS

Mode Resonant Tank InputConfiguration Description VA VB

I HB for RTA idle for RTB 2Vin/π 0II idle for RTA HB for RTB 0 2Vin/πIII HB for RTA HB for RTB 2Vin/π 2Vin/πIV FB for RTA HB for RTB 4Vin/π 2Vin/πV HB for RTA FB for RTB 2Vin/π 4Vin/πVI FB for RTA FB forRTB 4Vin/π 4Vin/π

III. FREQUENCY-DOMAIN ANALYSIS OFRECONFIGURABLE H5 BRIDGE BASED RESONANT

CONVERTER

A. Load distribution between dual tanks of H5 topology

For the H5 topology in Fig. 1, it can be divided intotwo sub-circuits following the voltage division prin-ciple as shown in Fig. 3, where vA and vB are twofundamental components of vab and vcb. vA and vBhave completely opposite phases. VA and VB are theiramplitudes, respectively, as summarized in TABLE I.

According to the principle of voltage division,

RL,A +RL,B = Ro. (1)

Then, the output power ratio is determined. Isec is theroot mean square (RMS) of output current.

Po,APo,B

=I2secRL,AI2secRL,B

=Vo,AVo,B

=nBVAGAnAVBGB

(2)

GA and GB are transfer functions of two resonant tanks.

Gi|i=A,B = niVo,i/Vi

=F 2i Ln,i√

(F 2i (1 + Ln,i)− 1)2 + (F 2

i − 1)2L2n,iQ

2iF

2i

(3)

Fi is the normalized switching frequency. Ln,i is theinductance ratio. Qi is the figure of merit (FOM).

Fi = fs,i/fr1,i (4)Ln,i = Lm,i/Lr,i (5)

Qi = π2

(√Lr,i/Cr,i

)/(8n2

iRL,i) (6)

To make the output power distributed evenly betweentwo resonant tanks, their gain range is better to have asimilar growth rate. Due to Mode IV and Mode V mirroreach other, series resonant frequencies of RTA and RTBare expected to match. Thus, the normalized switchingfrequencies of RTA and RTB can be treated as the same.

FA ≈ FB (7)

B. Iterative model for load distribution

From (2), at series resonant frequencies,

RL,ARL,B

=Vo,AVo,B

=nBVAnAVB

. (8)

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Start

Mode Configuration

Fi,k = 1, k = 0

Calculate RL,i,k+1 with (9) (10)

Fi,k+1 = Fi,k −∆F

Calculate Qi,k+1, Gi,k+1 with RL,i,k+1, Fi,k+1

k = k + 1

Hit frequency boundary?

Output all RL,i,k

Stop

N

Y

Fig. 4. Flow chat of the iterative model.

Since the secondary side is series connected, RL,A willchange if RL,B varies. In a specific mode, load distri-bution does not demonstrate a discontinuity betweenadjacent frequencies.

RL,A,k+1 =nBVAGA,k

nBVAGA,k + nAVBGB,kRo (9)

RL,B,k+1 =nAVBGB,k

nBVAGA,k + nAVBGB,kRo (10)

To calculate the voltage gains at Fi,k+1, RL,i,k+1 is used.

Fi,k+1 = Fi,k −∆F (11)

∆F is the step of Fk.When the switching frequency is below series resonant

frequency, ∆F ≥ 0. When the switching frequency isabove series resonant frequency, ∆F ≤ 0.

C. Input impedence and boundary gainIn Fig. 3, the input impedances of resonant tanks are

Zin,i =F 2i L

2n,iQi

1 + F 2i Q

2iL

2n,i

√Lr,iCr,i

+ jFiLn,i

1 + F 2i Q

2iL

2n,i

√Lr,iCr,i

+ jF 2i − 1

Fi

√Lr,iCr,i

(12)

The peak gain occurs at resistive input impedance point.At that point, input impedance has no imaginary part.

Im(Zin,i) =Fi,minLn,i

1 + F 2i,minQ

2iL

2n,i

√Lr,iCr,i

+F 2i,min − 1

Fi,min

√Lr,iCr,i

= 0

(13)

At the peak gain point, the corresponding maximumFOM can be calculated.

Qi,max =

√1

Ln,i − Ln,iF 2i,min

− 1

(Ln,iFi,min)2 (14)

From (3), design of the LLC converter should be ableto achieve the maximum gain at heavy load and theminimum gain at light load.

Gi,max = Gi(Fi,min, Qi,max)

=Fi,minLn,i√

F 2i,min(L2

n,i + Ln,i)− Ln,i(15)

Gi,min = limQi→0

Gi(Fi,max, Qi)

=F 2i,maxLn,i(

F 2i,max(1 + Ln,i)− 1

) (16)

IV. GAIN RANGE ANALYSIS

A. Evenly distributed mode configuration boundaryWith six modes in H5 topology, the gain range can be

widely expanded. Since the output voltage is regulatedto be constant, the division of input voltage ranges needsto be optimized. At the resonant point,

Vo/Vin,M1 = 12GA

nA= 1

21nA

Vo/Vin,M2 = 12GB

nB= 1

21nB

Vo/Vin,M3 = 12 (GA

nA+ GB

nB) = 1

2 ( 1nA

+ 1nB

)

Vo/Vin,M4 = GA

nA+ 1

2GB

nB= 1

nA+ 1

21nB

Vo/Vin,M5 = 12GA

nA+ GB

nB= 1

21nA

+ 1nB

Vo/Vin,M6 = GA

nA+ GB

nB= 1

nA+ 1

nB

(17)

It should be noted that nB=k nA, and Vin,Mi(i =1,2,3,4,5,6) is distributed evenly.

u = (Vin,M1 − Vin,M2)2

+ (Vin,M2 − Vin,M3)2

+ (Vin,M3 − Vin,M4)2

+ (Vin,M4 − Vin,M5)2

+ (Vin,M5 − Vin,M6)2

(18)

The six modes are fully utilized with the minimum u.In this situation, k=3/4.

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B. Continuous voltage gain range

Since in Mode 1, the H5 bridge is operated in halfbridge mode, according to (3), (15) the maximum con-version ratio of Mode 1 is

Mmax,1 =Vo

Vin,M1,min=Gmax,1,A

2nA(19)

according to (16) the minimum conversion ratio of Mode2 is

Mmin,2 =Vo

Vin,M2,max=Gmin,2,B

2nB(20)

Since the output voltage is constant Vo, Mmin,2shouldbe larger than Mmax,1

Mmin,2 ≥Mmax,1 (21)

Similarily, the maximum conversion ratios of othermodes are:

Mmax,2 =Vo

Vin,M2,min=Gmax,2,B

2nB(22)

Mmax,3 =Vo

Vin,M3,min=Gmax,3,A

2nA+Gmax,3,B

2nB(23)

Mmax,4 =Vo

Vin,M4,min=Gmax,4,A

nA+Gmax,4,B

2nB(24)

Mmax,5 =Vo

Vin,M5,min=Gmax,5,A

2nA+Gmax,5,B

nB(25)

Mmax,6 =Vo

Vin,M6,min=Gmax,6,A

nA+Gmax,6,B

nB(26)

The minimum conversion ratio of other modes are:

Mmin,1 =Vo

Vin,M1,max=Gmin,1,A

2nA(27)

Mmin,3 =Vo

Vin,M3,max=Gmin,3,A

2nA+Gmin,3,B

2nB(28)

Mmin,4 =Vo

Vin,M4,max=Gmin,4,A

nA+Gmin,4,B

2nB(29)

Mmin,5 =Vo

Vin,M5,max=Gmin,5,A

2nA+Gmin,5,B

nB(30)

Mmin,6 =Vo

Vin,M6,max=Gmin,6,A

nA+Gmin,6,B

nB(31)

To achieve a continuous voltage gain range,

Mmin,2 ≥Mmax,1 (32)Mmin,3 ≥Mmax,2 (33)Mmin,4 ≥Mmax,3 (34)Mmin,5 ≥Mmax,4 (35)Mmin,6 ≥Mmax,5 (36)

C. Parameter calculation

The relationship among quality factor, turns ratio,resonant capacitance, equivalent ac load and resonantfrequency can be expressed as,

Qifr1,i =

√Lr,iCr,i

1

n2iRL,i

1

2π√Lr,iCr,i

=1

2πn2iCr,iRL,i

(37)

Thus, resonant capacitance have a minimum value:

Qi =1

2πn2iCr,iRL,ifr,i

≤ Qi,max

⇒ Cr,i ≥1

2πn2iQi,maxRL,i,minfr1,i

(38)

With the minimum resonant capacitance, the maxi-mum resonant inductance can be achieved,

Lr,i =1

(2πfr1,i)2Cr,i(39)

With the designed inductance ratio , the magnetizinginductance can be calculated,

Lm,i = Ln,iLr,i (40)

Lm should provide enough energy to facilitate theZVS,

1

2(Lr,A + Lm,A)

(nAVo,ALm,A

Ts4

)2

+1

2(Lr,B + Lm,B)

(nBVo,BLm,B

Ts4

)2

≥ 1

2CeqV

2in

(41)

Ceq = 4Coss + Cstray (42)

Cstray is the stray capacitance due to PCB parasitics.The final Lm,A and Lm,B should satisfy requirements ofboth gain and ZVS.

V. LOSS ANALYSIS

A. Conduction loss

Main part of conduction loss consists of two parts:semiconductor loss, copper loss and parasitic loss. Semi-conductor loss is introduced by Rds,on of MOSFETschannel and Vd of body diodes. Copper loss is the loss ontransmission line and inductor windings. Parasitic lossis introduced by equivalent series resistance of resonantcapacitors, input and output capacitors. Parasitic loss canbe reduced by parelling resonant capacitors and widecopper foils.

1) Semiconductor loss: Semiconductor loss is mainlydetermined by the peak of resonant current and sec-ondary current [13].

ILr,i,peak =

√2

8

Vo,iniRL,i

√2n4

iR2L,i

L2m,if

2s

+ 8π2 (43)

Isec,i,peak =

√2

4

Vo,iniRL,i

√5π2 − 48

12π2

n4iR

2L,i

L2m,if

2s

+ π2 (44)

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So, a larger magnetizing inductance or a smaller MOS-FET on resistance can reduce the semiconductor loss. Alower frequency makes a larger peak current. Thus, awide frequency band will cause large loss.

2) Copper loss: Copper loss consists of two aspects.One is the PCB transimission line loss; another is themagnetizing component conduction loss.

PCB transimission line loss is mainly determined bythe ac resistance of copper foils due to the skin effect.The skin depth ξ is determined in [14].

ξ =1√

πfsµg(45)

fs is the switching frequency. µ is the absolute magneticpermeability of the conductor. g is the conductivity ofthe conductor in S/m. If the copper foil is thinner thanthe skin depth, then the ac resistance’s effect is mitigated.

The magnetic component conduction loss is due to theproximity effect of inductor or transformer windings.To inductors, for a M layer winding, since it can nothave a interleave winding, the proximity effect makesan increased ac resistance [15].

Rproxi =1

3

h

ξ(2M2 + 1)Rdc (46)

h is the winding thickness. To a litz wire, h/ξ ≈ 1To some ferrite magnetic components with large air

gaps, the fringing effect also needs to be considered. Theaccurate loss can be only determined by finite elementsimulations. A qualitative relation of this part of loss isdetermined by the physical winding turns and currentamplitude. More windings, more loss. Larger current,larger loss. The physical winding turns is limited by thesaturation of ferrite cores.

B. Switching loss

The converter works in ZVS region. Thus, the turn onloss of primary MOSFETs can be neglected. Total turnoff loss of primary MOSFETs can be estimated [16].

Poff =(Iofftfall)

2fs3Ctotal

(47)

From HB condition (Mode 1 and mode 2),

Poff =(Iofftfall)

2fs6Coss

(48)

From other condition (Mode 3-6),

Poff =(Iofftfall)

2fs15Coss

(49)

To secondary rectifiers, even when fs ≥ fr the rectifiercurrent is in critical conduction mode (CRM). Due tothe implementation of SR, ZVS for MOSFET is natural.Since main part of current is conducted in the channelof SR MOSFET, the reverse recovery of body diode ismitigated. The switching loss of secondary SR MOSFETsis very small.

C. Core loss

Core loss can be estimated with the Steinmetz equa-tion [17].

pLr,i = Cm fα B̂βLr,i (50)

pTX,i = Cm fα B̂βTX,i (51)

For resonant inductors, since the resonant current hasno dc bias, B̂Lr,A and B̂Lr,B is proportional to theircorresponding peak resonant current.

For transformers, B̂A and B̂B are calculated as

B̂TX,i =λp,i

2ns,iAe=

Vo,i4ns,iAefs

(52)

λp,A and λp,B are the maximum volt-second on trans-former. ns,A and ns,B are the secondary winding turns.Ae is the equivalent core areas.

When the converter works in mode 3 to 6, in primaryside the conduction loss is reduced due to two parallelresonant tanks. Since the output voltage are divided intotwo parts, the core loss are reduced in mode 3 to 6.The converter can achieve a good efficiency at mode 3-6.When design the converter, the normal operating voltageshould be designed there.

VI. DESIGN CONSIDERATIONS

A. Synchronized rectification

Researches have been done regarding sychronizedrectification (SR) [18]–[21]. Their mechanisms can bedivided into two catageroies: (a) signal launched (b)adapative control.

Signal launched SR is categorized into two types. Typeone uses current sensor transformer and maintains goodaccuracy [22]. However, additional winding and corelosses are introduced. Moreover, the magnetic compo-nents are bulky and difficult to design. Type two usessensing vds, the voltage drop between the drain andsource of SR MOSFETs [21], [23]. When vds is negativeand reaches its body diode conducting thresholdVth,d,SR MOSFETs turn on; when vds is negative and reachesthe turn off thresholdVth,c, which is manually set, SRMOSFETs turn off. When implementing this strategy, thePCB parasitic inductance might cause an early turn off ofSR MOSFETs’ channel. This incurs additional loss frombody diodes. This strategy is very sensitive to noise andthe accuracy is not moderate.

Adapative control in SR is widely used in digitalcontrol. In [20], the secondary MOSFETs are turned onsynchronously with primary side. In the turning offprocess, a window counter to accumulate times of vds <Vth,d is added to turn off the SR MOSFETs adapatively.It is easy to implement and successfully commercialized.Many commercial chips are made to implement the SRcontrol. In this work, a SR commercial chip, SRK2001 bySTMicroelectronics. is used to realize the SR.

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B. Mode transition

In the mode transition process, one output voltage oftwo resonant tanks increases while the other decreases.In order to maintain a stable output voltage, the processshould be done in a short period of time. As the primaryside LLC is a current source [24], the secondary side deltaconnected rectifier capacitor can be charged quickly.In our work, the output inductance ratio is selectedempirically a) to maintain a good output regulation, b)to achieve a smooth mode switching and c) to toleratethe unequal resonant current.

CoA = Co,B =1

100Co (53)

VII. EXPERIMENTAL RESULTS

A. Design parameters

The input range of the designed prototype is set as80V∼400V. The resonant frequency of two tanks aredesigned at 100kHz.

TABLE IIDESIGN PARAMETERS

Parameters ValueQ1 −Q5 SCT 3120ALLm,A(µH) 182.3Lr,A(µH) 38.2Cr,A(nF ) 64.9Lm,B(µH) 147.64Lr,B(µH) 30.5Cr,B(nF ) 84.5

nA 16:4:4nB 15:5:5

SR1 − SR4 IRFB 4115Co (µF ) 100

Co,A, Co,B (µF ) 1

B. ZVS verification

ZVS verification waveforms are shown in Fig. 5. Asshown, the designed parameters facilitate a good ZVSperformance in different operation modes.

The steady-state experimental waveforms in Mode3,4,5 and 6 are captured in Fig.6. From these figures,both RTA and RTB work well in HB or FB. All thesewaveforms are captured at 500W.

C. Synchronized rectification

The synchronized rectifier strategy uses commercialICs. The experiment waveforms are shown in Fig. 7.From the result, the SR performance is good both inabove resonance and below resonance situation.

D. Mode transition

Mode transition experiments are done in this work.Fig. 8 demonstrates the transients during the modetransitions. As shown, the transitions are smooth andthe output voltage is stable.

vgs4 (10 V/div)

iLr,A (5 A/div)

vds4 (250 V/div)

4 ms/div

(a) Mode 1

iLr,B (5 A/div)

vgs4 (10 V/div)

vds4 (250 V/div)

4 ms/div

(b) Mode 2

iLr,B

(5 A/div)

iLr,A

(5 A/div)

vgs4 (25 V/div)

vds4 (125 V/div)

4 ms/div

(c) Mode 3

iLr,B

(5 A/div)

iLr,A

(5 A/div)

vgs4 (25 V/div)

vds4 (125 V/div)

4 ms/div

(d) Mode 4

vgs4 (25 V/div)

vds4 (125 V/div)

iLr,B

(5 A/div)

iLr,A

(5 A/div)

4 ms/div

(e) Mode 5

iLr,B

(5 A/div)

iLr,A

(5 A/div)

vgs4 (25 V/div)

vds4 (125 V/div)

4 ms/div

(f) Mode 6

Fig. 5. ZVS verification in different modes.

iLr,B (10 A/div)

iLr,A (10 A/div)

vcb (250 V/div)

vab (250 V/div)

4 ms/div

(a) Mode 3 at 143V

iLr,B (10 A/div)

iLr,A (10 A/div)

vcb (125 V/div)

vab (125 V/div)

4 ms/div

(b) Mode 4 at 110V

iLr,B (10 A/div)

iLr,A (10 A/div)

vcb (250 V/div)

vab (250 V/div)

4 ms/div

(c) Mode 5 at 102V

iLr,B (10 A/div)

iLr,A (10 A/div)

vcb (125V/div)

vab (125 V/div)

4 ms/div

(d) Mode 6 at 80V

Fig. 6. Working waveforms in Mode 3,4,5 and 6.

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iSR1 (10 A/div)

iSR4 (10 A/div)

vgs,SR4 (25 V/div)

vgs,SR1 (25 V/div)

4 ms/div

(a) Working above resonance

4 ms/div

iSR1 (10 A/div)

iSR4 (10 A/div)

vgs,SR4 (25 V/div)

vgs,SR1 (25 V/div)

(b) Working below resonance

Fig. 7. Synchronized rectifier waveforms at 500W output power.

iLr,A (10 A/div)

iLr,B (10 A/div)

vab (250 V/div)

vo (50 V/div)

4 ms/div

(a) Switching from Mode 3 toMode 4 at 150V 500W

iLr,A (10 A/div)

iLr,B (10 A/div)

vab (250 V/div)

vo (50 V/div)

4 ms/div

(b) Switching from Mode 4 toMode 3 at 150V 500W

iLr,A (10 A/div)

iLr,B (10 A/div)

vab (250 V/div)

vo (50 V/div)

4 ms/div

(c) Switching from Mode 4 toMode 5 at 120V 500W

4 ms/div

iLr,A (10 A/div)

iLr,B (10 A/div)

vab (250 V/div)

vo (50 V/div)

(d) Switching from Mode 5 toMode 4 at 120V 500W

Fig. 8. Mode switching waveforms.

E. Efficiency

Conversion efficiency in six modes at different powerlevels are measured and plotted in Fig. 9. It can beobserved that the converter working in mode 3-6 demon-strates a higher efficiency. In order to provide a smoothmode transient, the overlap zone between two modesare designed to avoid a frequent mode transition.

VIII. CONCLUSIONS

In this work, a six-mode dual tank resonant con-verter based on a re-configurable H5 bridge is proposedfor high step-down applications. The optimal designmethod is detailed. An iterative gain model is presentedto estimate the load distribution. A 500W prototypeis designed to verify the model. It provides 5 timesnormalized peak gain. The input voltage range is fullycovered. Losses component are estimated. The maximumefficiency is 96.95%. A wide ZVS range and smoothmode transitions are achieved experimentally.

150 250 350 450

90.5

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400V360V320VE

ffic

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cy [

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Fig. 9. Efficiency in different modes.

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