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Optical Receiver DesignOptical Receiver Design

ECE 453 FinalECE 453 FinalPresentationPresentation

Dave BowenDave Bowen

Wei Min ChanWei Min Chan

Ben Cipriany Ben Cipriany

Kent En LohKent En Loh

December 2December 2ndnd 20052005



Optical Network MotivationsOptical Network Motivations

Data transmission occurs typically atData transmission occurs typically atbasebandbaseband ² ² optical wavelength·soptical wavelength·sfrequency is the carrierfrequency is the carrier

Short, medium, and long Short, medium, and long--haulhaulapplicationsapplications

Typically highTypically high--data ratedata ratecommunicationscommunications

Low extrinsic noise and interference atLow extrinsic noise and interference atoptical frequenciesoptical frequencies

http://www.jdsu.com/site/primer/launch.html



Basic Optical Receiver FrontBasic Optical Receiver Front--EndEnd

Current to VoltageCurrent to VoltageSignal ConversionSignal Conversion

Photodiode TransimpendenceAmplifier (TIA)

LimitingAmplifier (LA)

OutputBuffer (OB)

Automatic Gain

Control (AGC)

To Maintain SignalTo Maintain SignalLinearity andLinearity andGain LevelGain Level

Reshapes Signal forReshapes Signal forInput to DigitalInput to Digital

SystemSystem

Output Drive andOutput Drive andCircuit BufferCircuit Buffer

Optical INOptical IN --> Electrical OUT> Electrical OUT



Optical Receiver ApplicationOptical Receiver Application

RequirementsRequirements General:General: Low Low--noise electronics for optical to electrical signal conversionnoise electronics for optical to electrical signal conversion

Short to medium haul applicationShort to medium haul application 2+ Gbps data rate2+ Gbps data rate

Input side:Input side: InGaAs Photodiode with junction capacitance ~ 100 fF·sInGaAs Photodiode with junction capacitance ~ 100 fF·s

Optical powers ranging fromOptical powers ranging from --20 to +10 dBm, causing input20 to +10 dBm, causing input

currents from 10uA to 10mAcurrents from 10uA to 10mA

Output side:Output side: Drive a capacitive load representing subsequent MOSFET gateDrive a capacitive load representing subsequent MOSFET gate Digital signal RZDigital signal RZ--type outputtype output



Transimpedance AmplifierTransimpedance Amplifier

Adjustable gainAdjustable gain

Prevent damage to subsequent stagesPrevent damage to subsequent stages

Maximize range of smallMaximize range of small--signal operationsignal operation

Prevent data distortion from clipping Prevent data distortion from clipping

Output 100+ mV to LA stage for proper operationOutput 100+ mV to LA stage for proper operation

Simple and fastSimple and fast

Must provide 2+ GHz bandwidth over entire adjustableMust provide 2+ GHz bandwidth over entire adjustablerangerange

Be able to provide a consistent DC bias level at stageBe able to provide a consistent DC bias level at stageoutputoutput



Transimpedance AmplifierTransimpedance Amplifier

Variable Gain TIAVariable Gain TIA

Common gateCommon gateconfigurationconfiguration

All NFETs forAll NFETs for

maximum bandwidthmaximum bandwidth Gain adjustmentGain adjustment

transistor operating intransistor operating in

linear regimelinear regime

Fixed Gain DifferentialFixed Gain DifferentialAmplifier CascadeAmplifier Cascade

Basic NFETBasic NFET

differential pairdifferential pairdesign for maximumdesign for maximum

bandwidthbandwidth



Transimpedance Amplifier:Transimpedance Amplifier:

Adjustable GainAdjustable Gain

Output Voltage vs. Time for Varying Current InputOutput Voltage vs. Time for Varying Current Input

Input Conditions: 2GHz, square pulse, 50% duty cycleInput Conditions: 2GHz, square pulse, 50% duty cycle




Linear Dynamic RangeLinear Dynamic Range





Automatic Gain Controller (AGC)Automatic Gain Controller (AGC)




Assume AC signal centered around some DCAssume AC signal centered around some DC

offsetoffset

Mean of any periodic DC offset signal will beMean of any periodic DC offset signal will bethe DC Offsetthe DC Offset ² ² How do we measure the ACHow do we measure the ACportion?portion?

Solution? Use the square of the input AC Signal.Solution? Use the square of the input AC Signal.



Envelope Detector: MathEnvelope Detector: Math

This is the expected output of mixedThis is the expected output of mixed

and integrated sinusoid with DCand integrated sinusoid with DC

voltage offset:voltage offset:

2

2

0

2

0

*2

0

22

0

02

2

0

2

0

2

0

22

0

2

0

2

0

*202

1)sin(

**2)(sin

2

)*)sin(*2)(sin(2

1

))sin((

2

1

dc

pi

dcdc

dcdc

dc

V A

dt V t dt V A

t dt A

dt V V t At A

dt V t A

!

!

!

´ ´´

´

´

T T

T

T

T [

T [

T

[[T

[

T

0 0 .05 0 .1 0 .15 0 .2 0 .25 0. 3 0 .35 0 .4 0 .45 0 .53 .12

3 .14

3 .16

3 .18

3. 2

3 .22

3 .24

3 .26

3 .28Envelope detector Output

O

utput DC

Voltage

Input AC M agnitude



0 50 100 150 200 250 300 350 4000 5

1

1 5

2

2

5

3

3 5S

¡

gna¢ £

nput

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o¥

tage

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me


AGC Input Signal



0 50 100 150 200 250 300 350 4000.5

1

1.5

2

2.5

3

3.5

M ix¦

§ O ̈

©

̈

©

V

l

i

¦


AGC Output DC voltage



Automatic Gain Control (AGC)Automatic Gain Control (AGC)

AGC response to varying input AC magnitudes




AGC Signal response through output CS amplifier cascade




Fanning effect of output amplifiers in AGC circuit




TIA output controlled by AGC output



Limiting AmplifierLimiting Amplifier -- DesignDesign

ConsiderationsConsiderations

TIA outputTIA output -- few hundred millivoltsfew hundred millivolts

To drive digital circuitry as our loadTo drive digital circuitry as our load

LA outputLA output ² ² need signal swing close to logicalneed signal swing close to logicallevelslevels

Need high voltage gain and swing Need high voltage gain and swing

BandwidthBandwidth--Gain trade off Gain trade off Cascaded amplifier stages of diff ampsCascaded amplifier stages of diff amps



Cascade IssuesCascade Issues



GainGain--Bandwidth TradeBandwidth Trade--off off

Higher, lower gainHigher, lower gain



Limiting AmplifierLimiting Amplifier -- SchematicSchematic



Schmitt TriggerSchmitt Trigger



Limiting AmplifierLimiting Amplifier -- SimulationSimulation

LA output with noisy input



Output Waveform of LA Output Waveform of LA



Output Buffer ImplementationOutput Buffer Implementation



Output Buffer StageOutput Buffer Stage



DescriptionDescription

Cascaded inverter topology Cascaded inverter topology

Why use inverters?Why use inverters?

Boost output of previous stage up to railBoost output of previous stage up to rail--toto--rail voltage for driving rail voltage for driving minimal inverterminimal inverter

First inverters have small swing and act as linear amplifiersFirst inverters have small swing and act as linear amplifiers

Somewhere in the chain it is amplified until it clips against the powerSomewhere in the chain it is amplified until it clips against the powersupply.supply.

Subsequent inverters shape the signal by giving it faster rise and fall times.Subsequent inverters shape the signal by giving it faster rise and fall times.

AdvantagesAdvantages

Large dynamic rangeLarge dynamic range

Simple design => less poles => easier to achieve high bandwidthSimple design => less poles => easier to achieve high bandwidth

Output Buffer TopologyOutput Buffer Topology



Analog OptionAnalog Option -- Inductive Peaking BufferInductive Peaking Buffer



ReferencesReferences

High Speed CMOS Circuits for Optical Receivers.High Speed CMOS Circuits for Optical Receivers. J. Savoj andJ. Savoj andB. Razavi. Kluwer Academic Publishers, 2001.B. Razavi. Kluwer Academic Publishers, 2001.

Integrated CMOS Circuits for Optical CommunicationsIntegrated CMOS Circuits for Optical Communications..

M.Ingels and M.Steyaert. Springer Publications, 2004.M.Ingels and M.Steyaert. Springer Publications, 2004. Optical Communication Receiver Design.Optical Communication Receiver Design. S. Alexander. SPIES. Alexander. SPIE

Press, 1997.Press, 1997.



Questions?Questions?

Thank you!Thank you!

optical receiver2

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