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AN2455Operational Amplifier PSpice® Model of 8-Bit PIC® Microcontrollers

INTRODUCTION

This application note discusses the PSpice® model ofthe 8-bit PIC® MCUs’ internal operational amplifier(op amp). The PSpice op amp model can be used inanalyzing and simulating related op amp circuits. Themodel can also verify the characteristics of the internalop amp.

OPERATIONAL AMPLIFIER CHARACTERISTICS

The PSpice op amp model is an encrypted subcircuitnetlist with the symbol shown in Figure 1. The op ampmodel uses macromodeling to simulate the op amp’sbehavior and response under normal operating condi-tions. The model represents a single operating point ofthe op amp. Actual devices may vary within the limitsspecified in the specific data sheet. Table 1 lists someof the op amp characteristics that can be found on the8-bit PIC microcontroller’s data sheet. The parameterscan be measured by using test circuits which can bedone in PSpice.

FIGURE 1: PIC16F1769 OP AMP PSpice® PINOUT

Author: June Anthony AsistioMicrochip Technology Inc.

TABLE 1: ELECTRICAL CHARACTERISTICS OF THE PIC16F1769 INTERNAL OPERATIONAL AMPLIFIER

Parameters Symbol Minimum Typical Maximum Units

Gain-Bandwidth Product GBWP — 2 — MHz

Open-Loop Gain AOL — 90 — dB

Phase Margin ΦM — 40 — degrees

Slew Rate SR — 3 — V/µs

Input Offset Voltage VIO — ±3 ±9 mV

Common-Mode Rejection Ratio CMRR 52 70 — dB

Power Supply Rejection Ratio PSRR — 80 — dB

PSpice® NETLIST PINOUT PSpice SYMBOL

.SUBCKT PIC16F1769 1 2 3 4 5 * | | | | |* | | | | Output * | | | Negative Supply * | | Positive Supply * | Inverting Input * Non-inverting Input

1

2

3

4

OUT

V+

V-

5

U1PIC16F1769

2017 Microchip Technology Inc. DS00002455A-page 1

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Measuring Open-Loop Gain, Phase Margin and Gain-Bandwidth Product

The unity Gain-Bandwidth Product (GBWP) is thefrequency at which the open-loop gain (AOL) of the opamp becomes unity. Open-loop gain is the ratio of theoutput voltage to the differential input voltage, asshown in Equation 1. AOL is greatest at the DC voltageand falls off with frequency.

EQUATION 1: OPEN-LOOP GAIN

Phase margin (ΦM) is the difference between 180° andthe phase of the output voltage, relative to the inputvoltage, when the open-loop gain has reached unity.Phase margin is depicted in Equation 2.

EQUATION 2: PHASE MARGIN

The AOL, ΦM and the GBWP can be measured byplotting the open-loop gain and the phase versus thefrequency. Figure 2 shows the setup for getting thefrequency sweep of the open-loop gain. The op amp isconfigured as a differential amplifier. Two signals of 180°out of phase are injected at the VIN+ and VIN- terminalsof the op amp. Figure 3 shows the simulation results onthe PSpice and Figure 4 shows the actual measurementsof the frequency response of the op amp.

FIGURE 2: OPEN-LOOP GAIN TEST CIRCUIT (VDD = 3.3V)

AOL

VOUT

VDIFF

---------------V

OUT

VIN+ V

IN-–------------------------------= =

ΦM = 180° – Φ

+

–

+

–

+

–

+

–

+

–

C1{CL}RL

{RL}

OUT

R1

10k

OUT

V+

V-

VDD

1

2

INP

INM

VEE

U2

PIC16F1769

RN

1k

IN

V1

0

-1 VAC1.65 VDC

0

VSS0

VDD{VDD}

RP

1m

PARAMETERS:VDD = 3.3RL = 10kCL = 50pRF = 1

AC LOOPAC ANALYSISDB(V(OUT)/V(IN))P(V(OUT)/V(IN))

0 0

1 VAC

1.65 VDC

3

4

5

DS00002455A-page 2 2017 Microchip Technology Inc.

AN2455

FIGURE 3: FREQUENCY RESPONSE OPEN-LOOP GAIN (PSpice®)

FIGURE 4: FREQUENCY RESPONSE OF OPEN-LOOP GAIN (ACTUAL BODE PLOT)


AN2455

Table 2 provides a comparison of the PSpice resultswith actual measurements using Bode 100 equipment.

Measuring Slew Rate

The Slew Rate (SR) of the op amp is the rate at which theoutput voltage changes in response to the input voltage.SR is expressed mathematically in Equation 3.

EQUATION 3: SLEW RATE

SR can be measured using the test circuit in Figure 5,which is a non-inverting op amp configuration. Largesignal analysis is performed by injecting a VIN pulsetrain having a rise time of 1 ns, a fall time of 1 ns and aperiod of 1 ms. The transition time (rise time) for VOUTto go from minimum to maximum is measured. SR iscomputed using Equation 3. The SR for the positiverising edge and negative falling edge at differenttemperatures is shown in Figure 6.

FIGURE 5: SLEW RATE TEST CIRCUIT

TABLE 2: AC GAIN AND PHASE TEST RESULTS COMPARISON

ParameterPSpice®

Simulation Result

Actual Bode Plot

GBWP 2.5 MHz 2.794 MHz

ΦM 20° 25.990°

AOL 85 dB 78 dB

SRV

OUT

t------------------=

SR+

VMIN

VMAX

–

tRISE

---------------------------------=

SR-

VMAX

VMIN

–

tFALL

---------------------------------=

+

–

+

–

+

–

OUT

V+

V-

+

–

VDD{VDD}

VSS{VDD}

VIN

0

IN RP

10k

INP

INM

VDD

VEE

1

2

3

4

5

RG

10k

RF

{RF}

U1

PIC16F1769

OUT

RL{RL}

CL{CL}

0 0

PARAMETERS:VDD = 2.75RL = 10kCL = 1pRF = 90k

V1 = 200mV2 = 200mTD = 0.75µTR = 1nTF = 1nPW = 5µPER = 1m

SLEW RATETRANSIENT ANALYSISD(V(5))SWEEP TEMP -40C to 125CVDD +/-2.75V

V

V

V0


AN2455

FIGURE 6: SLEW RATE (VDD = 5.5V) SIMULATION TEST RESULT

Measuring the Input Offset Voltage

The input offset voltage (VIO) of the op amp is thedifferential voltage required between the VIN+ and VIN-inputs to make the output zero. VIO is expressed math-ematically in Equation 4. VIO is affected by temperatureand the VDD.

EQUATION 4: INPUT OFFSET VOLTAGE

VIO VIN+ VIN-–=

Note: When VOUT = 0.


AN2455

In Figure 7, the setup to measure VIO is done at VDD of5.5V. The test circuit is a unity follower configurationwith an input voltage, VIN = 0V. The voltage differenceat the inverting and non-inverting inputs of the op ampcorresponds to VIO. The results in Figure 8 show thatVIO increases with temperature. VIO is still within themaximum specification limit of 9 mV.

FIGURE 7: INPUT OFFSET VOLTAGE TEST CIRCUIT (VDD = 5.5V)

FIGURE 8: INPUT OFFSET VOLTAGE vs. TEMPERATURE

+

–

+

–

+

–

OUT

V+

V-

+

–

VDD{VDD}

VSS{VDD}

VIN

0

IN RP

10k

INP

INM

VDD

VEE

1

2

3

4

5

RG

10k

RF

{RF}

U1

PIC16F1769

OUT

RL{RL}

CL{CL}

0 0

PARAMETERS:VDD = 2.75RL = 1 MEGCL = 1pRF = 10k

V1 = 0V2 = 0TD = 100mTR = 20µTF = 20µPW = 5PER = 10

VOS VS TEMPERATURE TESTTRANSIENT ANALYSISV(OUT)

0

RZ

1m


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Measuring Common-Mode Rejection Ratio

Common-Mode Rejection Ratio (CMRR) is the ability ofthe op amp to reject a Common-mode input signal andamplify the differential input signal. CMRR is expressedas the ratio of the differential gain to the Common-modegain, as illustrated in Equation 5.

EQUATION 5: COMMON-MODE REJECTION RATIO

In Figure 9, the subtractor op amp configuration can beused to measure the CMRR. On the AC side, aCommon-mode signal, VIN, is applied to the VIN+ andVIN- terminals of the op amp. The effect of the Common-mode voltage on VOUT is almost negligible. On the DCside, V1 is added to VIN before the VIN- terminal to can-cel the effect of the input offset voltage on the VOUT. ADC voltage, V3, is applied to the VIN+ via the R1 resistor.The differential input voltage, VDIFF, is computed as V3– V1. VDIFF is approximately equal to V3. The CMRR isapproximately the ratio of VOUT and VIN+.

FIGURE 9: COMMON-MODE REJECTION RATIO TEST CIRCUIT

CMRRA

DIFF

ACM

---------------=

VDB

+

–

+

–

+

–

C1{CL}RL

{RL}

OUT

R2

{RF}

OUT

V+

V-

VDD

1

2

INP

INM

VEE

U2

PIC16F1769

0

VSS0

VDD{VDD}

RP

{RG}

PARAMETERS:VDD = 3.3RL = 10kCL = 50pRF = 1k

COMMON-MODE REJECTION RATIOAC ANALYSISPLOT DB(V(OUT))/(V(INP))

+

–

+–

VIN1 VAC0 VDC

V3 R1

{RF}1.65 VDC

+

–

IN

3

4

RG

{RG} 0 0

V1

RG = 1k

-0.001 VDC

5


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Figure 10 shows the PSpice results of CMRR versusfrequency of the input signal. Figure 11 shows theactual bode plot measurement.

FIGURE 10: CMRR vs. FREQUENCY SIMULATION RESULT

FIGURE 11: CMRR vs. FREQUENCY (ACTUAL BODE PLOT)


AN2455

Measuring the Power Supply Rejection Ratio

The Power Supply Rejection Ratio (PSRR) measuresthe change of output voltage with the change of thesupply voltage. For a single supply op amp, there isonly PSRR+. The value of PSRR+ can be computedusing Equation 6.

EQUATION 6: POWER SUPPLY REJECTION RATIO

Figure 12 shows the setup for measuring the PSRR+ ofthe op amp. The op amp is connected in an invertingamplifier configuration with a DC gain of -1. V1 is addedto the input voltage, VP, to cancel the effect of the inputoffset voltage on the output of the op amp. The VDDsupply voltage is imposed with a varying 1 VAC voltage,in which the varying ratio of VDD and VOUT is plotted.The PSRR+ results with frequency are shown inFigure 13.

FIGURE 12: PSRR+ TEST CIRCUIT (VDD = 3.3V)

PSRR+V

DD

VOUT

------------------=

VDB

VDB

+

–

+

–

C1{CL}R1

{RL}

OUT

R2

1k

OUT

V+

V-

VDD

1

2

INP

INM

VEE

U2PIC16F1769

0

VSS0

VDD1 VAC

PARAMETERS:VDD = 3.3RL = 10KCL = 1p

TEST PSRR PLUSAC ANALYSISDB(V(VDD)/(V(OUT))

+

–

RP

1m

+

–

IN

3

4

0 0

VP

{VDD}

+

–

RP1

1k

-1.65V1

0.0010 VDC

RZ

1m

5

VDD


AN2455

FIGURE 13: PSRR+ vs. FREQUENCY SIMULATION RESULTS

FIGURE 14: PSRR+ vs. FREQUENCY (ACTUAL BODE PLOT)


AN2455

INVERTING AMPLIFIER CONFIGURATION

A commonly used circuit for the op amp is the invertingamplifier configuration. Figure 15 shows how to per-form the transient analysis of the inverting amplifier.

The amplifier is injected with a VIN of 1 kHz sine wavewith an AC component of 200 mVp-p and a DC offsetof 2.5V. The transient analysis is set at a duration of100 µs.

FIGURE 15: TRANSIENT ANALYSIS SETUP FOR THE INVERTING AMPLIFIER

VDB

+

–

R2

22k

+

–

OUT

V-

V+

2

1

VSS

4

3+

–

R1

2.2k

+

–

IN

V1

0

VOFF = 2.5VAMPL = 100mFREQ = 1kAC =

VDD

VDD

VSS

VSS

0

5 VDC

0 VDC

0

R3100k

R4100k

REF

VDD

INM

REF

5

IN

OUT

0VDD

PIC16F1769U1

RL10k


AN2455

Figure 16 shows the transient response of the invertingamplifier.

FIGURE 16: TRANSIENT RESPONSE OF THE INVERTING AMPLIFIER


AN2455

The AC gain can be computed using Equation 7. Thecomputed AC gain can be verified by measuring VOUTand substituting the value in Equation 8.

EQUATION 7: INVERTING AMPLIFIER AC GAIN

EQUATION 8: MEASURING THE INVERTING AMPLIFIER AC GAIN

Frequency analysis can also be done on the invertingamplifier. Figure 17 shows the setup for getting the fre-quency response. The results in Figure 18 show thatthe inverting amplifier has a phase margin of 34.917°.

FIGURE 17: AC ANALYSIS SETUP FOR THE INVERTING AMPLIFIER

AV AC

R– 2R1----------

22k–2.2k------------ 10–= = =

AV AC

VOUT

VIN-–

VIN

VIN-–-------------------------------

VOUT

VREF

–

VIN

VREF

–---------------------------------= =

AV AC

1.9987VP P–

200mVP P–

-------------------------------- 9.9935= =

AV AC

VOUT

VIN

------------------=

+

–

+

–

VDD

VDD

VSS

VSS

0

5 VDC

0 VDC

+

–

IN

V1

0

1 VAC2.5 VDC

0

R3100k

R4100k

REF

VDD

R2

22k

+

–

OUT

V-

V+

2

1

VSS

4

3

R1

2.2k

INM

REF

5

IN

OUT

0VDD

PIC16F1769U1

RL10k


AN2455

FIGURE 18: FREQUENCY RESPONSE OF THE INVERTING AMPLIFIER


AN2455

CONCLUSION

The PSpice op amp model has shown that the char-acteristics are within the specification limits of theactual op amp. The PSpice model helps in analyzingthe design of analog circuits that use the op amp of the8-bit PIC microcontrollers.


AN2455

NOTES:


Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights unless otherwise stated.

2017 Microchip Technology Inc.

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISO/TS 16949 ==

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© 2017, Microchip Technology Incorporated, All Rights Reserved.

ISBN: 978-1-5224-1881-8

DS00002455A-page 17


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