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Operating Systems Virtual Memory and Page Replacement Peter Lipp, Daniel Gruss October 10, 2019 www.iaik.tugraz.at

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Page 1: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Operating Systems

Virtual Memory and Page Replacement

Peter Lipp, Daniel Gruss

October 10, 2019

www.iaik.tugraz.at

Page 2: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Table of contents www.tugraz.at

1. Efficient Address Translation

2. Memory Layout

3. Page Replacement

1 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 3: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Efficient Address Translation

Page 4: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Efficient Address Translation www.tugraz.at

• What about speed?

• How many actual memory accesses per

intended memory access?

PDI (10 bit) PTI (10 bit) Offset (12 bit)

32-bit virtual address

CR3Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 1023

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 1023

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-32

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

PML4I (9 bit) PDPTI (9 bit) PDI (9 bit) PTI (9 bit) Offset (12 bit)

48-bit virtual address

CR3PML4

PML4E 0

PML4E 1···

#PML4I···

PML4E 511

PDPT

PDPTE 0

PDPTE 1···

#PDPTI···

PDPTE 511

Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 511

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 511

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-64

• 1 access into page-map-level-4

• 1 access into the page-directory pointer

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

2 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 5: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Efficient Address Translation www.tugraz.at

• What about speed?

• How many actual memory accesses per

intended memory access?

PDI (10 bit) PTI (10 bit) Offset (12 bit)

32-bit virtual address

CR3Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 1023

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 1023

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-32

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

PML4I (9 bit) PDPTI (9 bit) PDI (9 bit) PTI (9 bit) Offset (12 bit)

48-bit virtual address

CR3PML4

PML4E 0

PML4E 1···

#PML4I···

PML4E 511

PDPT

PDPTE 0

PDPTE 1···

#PDPTI···

PDPTE 511

Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 511

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 511

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-64

• 1 access into page-map-level-4

• 1 access into the page-directory pointer

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

2 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 6: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Efficient Address Translation www.tugraz.at

• What about speed?

• How many actual memory accesses per

intended memory access?

PDI (10 bit) PTI (10 bit) Offset (12 bit)

32-bit virtual address

CR3Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 1023

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 1023

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-32

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

PML4I (9 bit) PDPTI (9 bit) PDI (9 bit) PTI (9 bit) Offset (12 bit)

48-bit virtual address

CR3PML4

PML4E 0

PML4E 1···

#PML4I···

PML4E 511

PDPT

PDPTE 0

PDPTE 1···

#PDPTI···

PDPTE 511

Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 511

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 511

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-64

• 1 access into page-map-level-4

• 1 access into the page-directory pointer

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

2 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 7: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Efficient Address Translation www.tugraz.at

• What about speed?

• How many actual memory accesses per

intended memory access?

PDI (10 bit) PTI (10 bit) Offset (12 bit)

32-bit virtual address

CR3Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 1023

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 1023

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-32

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

PML4I (9 bit) PDPTI (9 bit) PDI (9 bit) PTI (9 bit) Offset (12 bit)

48-bit virtual address

CR3PML4

PML4E 0

PML4E 1···

#PML4I···

PML4E 511

PDPT

PDPTE 0

PDPTE 1···

#PDPTI···

PDPTE 511

Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 511

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 511

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-64

• 1 access into page-map-level-4

• 1 access into the page-directory pointer

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

2 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 8: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Efficient Address Translation www.tugraz.at

• What about speed?

• How many actual memory accesses per

intended memory access?

PDI (10 bit) PTI (10 bit) Offset (12 bit)

32-bit virtual address

CR3Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 1023

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 1023

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-32

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

PML4I (9 bit) PDPTI (9 bit) PDI (9 bit) PTI (9 bit) Offset (12 bit)

48-bit virtual address

CR3PML4

PML4E 0

PML4E 1···

#PML4I···

PML4E 511

PDPT

PDPTE 0

PDPTE 1···

#PDPTI···

PDPTE 511

Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 511

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 511

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-64

• 1 access into page-map-level-4

• 1 access into the page-directory pointer

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

2 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 9: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Efficient Address Translation www.tugraz.at

• What about speed?

• How many actual memory accesses per

intended memory access?

PDI (10 bit) PTI (10 bit) Offset (12 bit)

32-bit virtual address

CR3Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 1023

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 1023

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-32

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

PML4I (9 bit) PDPTI (9 bit) PDI (9 bit) PTI (9 bit) Offset (12 bit)

48-bit virtual address

CR3PML4

PML4E 0

PML4E 1···

#PML4I···

PML4E 511

PDPT

PDPTE 0

PDPTE 1···

#PDPTI···

PDPTE 511

Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 511

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 511

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-64

• 1 access into page-map-level-4

• 1 access into the page-directory pointer

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

2 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 10: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Efficient Address Translation www.tugraz.at

• What about speed?

• How many actual memory accesses per

intended memory access?

PDI (10 bit) PTI (10 bit) Offset (12 bit)

32-bit virtual address

CR3Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 1023

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 1023

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-32

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

PML4I (9 bit) PDPTI (9 bit) PDI (9 bit) PTI (9 bit) Offset (12 bit)

48-bit virtual address

CR3PML4

PML4E 0

PML4E 1···

#PML4I···

PML4E 511

PDPT

PDPTE 0

PDPTE 1···

#PDPTI···

PDPTE 511

Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 511

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 511

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-64

• 1 access into page-map-level-4

• 1 access into the page-directory pointer

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

2 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 11: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Efficient Address Translation www.tugraz.at

• What about speed?

• How many actual memory accesses per

intended memory access?

PDI (10 bit) PTI (10 bit) Offset (12 bit)

32-bit virtual address

CR3Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 1023

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 1023

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-32

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

PML4I (9 bit) PDPTI (9 bit) PDI (9 bit) PTI (9 bit) Offset (12 bit)

48-bit virtual address

CR3PML4

PML4E 0

PML4E 1···

#PML4I···

PML4E 511

PDPT

PDPTE 0

PDPTE 1···

#PDPTI···

PDPTE 511

Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 511

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 511

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-64

• 1 access into page-map-level-4

• 1 access into the page-directory pointer

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

2 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 12: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Efficient Address Translation www.tugraz.at

• What about speed?

• How many actual memory accesses per

intended memory access?

PDI (10 bit) PTI (10 bit) Offset (12 bit)

32-bit virtual address

CR3Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 1023

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 1023

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-32

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

PML4I (9 bit) PDPTI (9 bit) PDI (9 bit) PTI (9 bit) Offset (12 bit)

48-bit virtual address

CR3PML4

PML4E 0

PML4E 1···

#PML4I···

PML4E 511

PDPT

PDPTE 0

PDPTE 1···

#PDPTI···

PDPTE 511

Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 511

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 511

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-64

• 1 access into page-map-level-4

• 1 access into the page-directory pointer

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

2 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 13: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Efficient Address Translation www.tugraz.at

• What about speed?

• How many actual memory accesses per

intended memory access?

PDI (10 bit) PTI (10 bit) Offset (12 bit)

32-bit virtual address

CR3Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 1023

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 1023

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-32

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

PML4I (9 bit) PDPTI (9 bit) PDI (9 bit) PTI (9 bit) Offset (12 bit)

48-bit virtual address

CR3PML4

PML4E 0

PML4E 1···

#PML4I···

PML4E 511

PDPT

PDPTE 0

PDPTE 1···

#PDPTI···

PDPTE 511

Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 511

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 511

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-64

• 1 access into page-map-level-4

• 1 access into the page-directory pointer

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

2 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 14: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Efficient Address Translation www.tugraz.at

• What about speed?

• How many actual memory accesses per

intended memory access?

PDI (10 bit) PTI (10 bit) Offset (12 bit)

32-bit virtual address

CR3Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 1023

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 1023

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-32

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

PML4I (9 bit) PDPTI (9 bit) PDI (9 bit) PTI (9 bit) Offset (12 bit)

48-bit virtual address

CR3PML4

PML4E 0

PML4E 1···

#PML4I···

PML4E 511

PDPT

PDPTE 0

PDPTE 1···

#PDPTI···

PDPTE 511

Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 511

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 511

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-64

• 1 access into page-map-level-4

• 1 access into the page-directory pointer

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

2 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 15: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Efficient Address Translation www.tugraz.at

• What about speed?

• How many actual memory accesses per

intended memory access?

PDI (10 bit) PTI (10 bit) Offset (12 bit)

32-bit virtual address

CR3Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 1023

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 1023

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-32

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

PML4I (9 bit) PDPTI (9 bit) PDI (9 bit) PTI (9 bit) Offset (12 bit)

48-bit virtual address

CR3PML4

PML4E 0

PML4E 1···

#PML4I···

PML4E 511

PDPT

PDPTE 0

PDPTE 1···

#PDPTI···

PDPTE 511

Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 511

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 511

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-64

• 1 access into page-map-level-4

• 1 access into the page-directory pointer

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

2 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 16: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Efficient Address Translation www.tugraz.at

• What about speed?

• How many actual memory accesses per

intended memory access?

PDI (10 bit) PTI (10 bit) Offset (12 bit)

32-bit virtual address

CR3Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 1023

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 1023

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-32

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

PML4I (9 bit) PDPTI (9 bit) PDI (9 bit) PTI (9 bit) Offset (12 bit)

48-bit virtual address

CR3PML4

PML4E 0

PML4E 1···

#PML4I···

PML4E 511

PDPT

PDPTE 0

PDPTE 1···

#PDPTI···

PDPTE 511

Page Directory

PDE 0

PDE 1···

PDE #PDI···

PDE 511

Page Table

PTE 0

PTE 1···

PTE #PTI···

PTE 511

4 KiB Page

Byte 0

Byte 1···

Offset···

Byte 4095

x86-64

• 1 access into page-map-level-4

• 1 access into the page-directory pointer

• 1 access into page directory

• 1 access into the page table page

• 1 access into memory

2 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 17: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Speed up things again www.tugraz.at

• Translation Look-aside Buffer (TLB)

• Cache recent virtual → physical translations

• TLB: A page-table-entry cache

• Cache hit: use translation

• Cache miss: walk multi-level page table

• TLB entry

• virtual page number

• physical page frame number

• access permissions

3 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 18: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Speed up things again www.tugraz.at

• Translation Look-aside Buffer (TLB)

• Cache recent virtual → physical translations

• TLB: A page-table-entry cache

• Cache hit: use translation

• Cache miss: walk multi-level page table

• TLB entry

• virtual page number

• physical page frame number

• access permissions

3 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 19: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Speed up things again www.tugraz.at

• Translation Look-aside Buffer (TLB)

• Cache recent virtual → physical translations

• TLB: A page-table-entry cache

• Cache hit: use translation

• Cache miss: walk multi-level page table

• TLB entry

• virtual page number

• physical page frame number

• access permissions

3 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 20: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Speed up things again www.tugraz.at

• Translation Look-aside Buffer (TLB)

• Cache recent virtual → physical translations

• TLB: A page-table-entry cache

• Cache hit: use translation

• Cache miss: walk multi-level page table

• TLB entry

• virtual page number

• physical page frame number

• access permissions

3 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 21: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Speed up things again www.tugraz.at

• Translation Look-aside Buffer (TLB)

• Cache recent virtual → physical translations

• TLB: A page-table-entry cache

• Cache hit: use translation

• Cache miss: walk multi-level page table

• TLB entry

• virtual page number

• physical page frame number

• access permissions

3 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 22: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Speed up things again www.tugraz.at

• Translation Look-aside Buffer (TLB)

• Cache recent virtual → physical translations

• TLB: A page-table-entry cache

• Cache hit: use translation

• Cache miss: walk multi-level page table

• TLB entry

• virtual page number

• physical page frame number

• access permissions

3 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 23: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Speed up things again www.tugraz.at

• Translation Look-aside Buffer (TLB)

• Cache recent virtual → physical translations

• TLB: A page-table-entry cache

• Cache hit: use translation

• Cache miss: walk multi-level page table

• TLB entry

• virtual page number

• physical page frame number

• access permissions

3 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 24: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Speed up things again www.tugraz.at

• Translation Look-aside Buffer (TLB)

• Cache recent virtual → physical translations

• TLB: A page-table-entry cache

• Cache hit: use translation

• Cache miss: walk multi-level page table

• TLB entry

• virtual page number

• physical page frame number

• access permissions

3 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 25: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Speed up things again www.tugraz.at

• Translation Look-aside Buffer (TLB)

• Cache recent virtual → physical translations

• TLB: A page-table-entry cache

• Cache hit: use translation

• Cache miss: walk multi-level page table

• TLB entry

• virtual page number

• physical page frame number

• access permissions

3 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 26: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How many memory accesses per cache miss? www.tugraz.at

Lookup

direction

Core 0 Core 1

Page table structures in DRAM (physicalmemory)

4 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 27: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How many memory accesses per cache miss? www.tugraz.at

Lookup

direction

Core 0 Core 1

ITLB DTLBITLB DTLB

Page table structures in DRAM (physicalmemory)

4 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 28: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How many memory accesses per cache miss? www.tugraz.at

Lookup

direction

Core 0 Core 1

ITLB DTLBITLB DTLB

PDE cache PDE cache

Page table structures in DRAM (physicalmemory)

4 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 29: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How many memory accesses per cache miss? www.tugraz.at

Lookup

direction

Core 0 Core 1

ITLB DTLBITLB DTLB

PDE cache PDE cache

Lookup

directionPage table structures in DRAM (physicalmemory)

4 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 30: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How many memory accesses per cache miss? www.tugraz.at

Lookup

direction

Core 0 Core 1

ITLB DTLBITLB DTLB

PDE cache PDE cache

Lookup

direction

PDPTE cache PDPTE cache

Page table structures in DRAM (physicalmemory)

4 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 31: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How many memory accesses per cache miss? www.tugraz.at

Lookup

direction

Core 0 Core 1

ITLB DTLBITLB DTLB

PDE cache PDE cache

Lookup

direction

PDPTE cache PDPTE cache

PML4E cache PML4E cache

Page table structures in DRAM (physicalmemory)

4 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 32: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How many memory accesses per cache miss? www.tugraz.at

Lookup

direction

Core 0 Core 1

ITLB DTLBITLB DTLB

PDE cache PDE cache

Lookup

direction

PDPTE cache PDPTE cache

PML4E cache PML4E cache

Page table structures cached indata caches (L1/L2/L3 cache)

Page table structures in DRAM (physicalmemory)

4 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 33: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How many memory accesses per cache miss? www.tugraz.at

Lookup

direction

Core 0 Core 1

ITLB DTLBITLB DTLB

PDE cache PDE cache

Lookup

direction

PDPTE cache PDPTE cache

PML4E cache PML4E cache

Page table structures cached indata caches (L1/L2/L3 cache)

Page table structures inDRAM (physical memory)

Page table structures in DRAM (physicalmemory)

4 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 34: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

TLB / Caching www.tugraz.at

• Why does caching help?

• Principle of locality

• If a memory address is accessed, likely nearby addresses are referenced in the future

• Nearby: same page, uses identical address translation (without offset)

• High degree of locality: almost all page translations from TLB

5 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 35: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

TLB / Caching www.tugraz.at

• Why does caching help?

• Principle of locality

• If a memory address is accessed, likely nearby addresses are referenced in the future

• Nearby: same page, uses identical address translation (without offset)

• High degree of locality: almost all page translations from TLB

5 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 36: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

TLB / Caching www.tugraz.at

• Why does caching help?

• Principle of locality

• If a memory address is accessed, likely nearby addresses are referenced in the future

• Nearby: same page, uses identical address translation (without offset)

• High degree of locality: almost all page translations from TLB

5 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 37: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

TLB / Caching www.tugraz.at

• Why does caching help?

• Principle of locality

• If a memory address is accessed, likely nearby addresses are referenced in the future

• Nearby: same page, uses identical address translation (without offset)

• High degree of locality: almost all page translations from TLB

5 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 38: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

TLB / Caching www.tugraz.at

• Why does caching help?

• Principle of locality

• If a memory address is accessed, likely nearby addresses are referenced in the future

• Nearby: same page, uses identical address translation (without offset)

• High degree of locality: almost all page translations from TLB

5 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 39: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

TLB / Caching www.tugraz.at

• Why does caching help?

• Principle of locality

• If a memory address is accessed, likely nearby addresses are referenced in the future

• Nearby: same page, uses identical address translation (without offset)

• High degree of locality: almost all page translations from TLB

5 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 40: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

TLB www.tugraz.at

6 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 41: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

When Do TLBs Work/Not Work? www.tugraz.at

• Video Frame Buffer: 32 bits x 1K x 1K = 4MB

• redraw screen - processor may touch every pixel

• 1024 TLB entries required

7 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 42: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

When Do TLBs Work/Not Work? www.tugraz.at

• Video Frame Buffer: 32 bits x 1K x 1K = 4MB

• redraw screen - processor may touch every pixel

• 1024 TLB entries required

7 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 43: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

When Do TLBs Work/Not Work? www.tugraz.at

• Video Frame Buffer: 32 bits x 1K x 1K = 4MB

• redraw screen - processor may touch every pixel

• 1024 TLB entries required

7 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 44: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Superpages / Page sizes www.tugraz.at

Set of contiguous pages in physical memory that map a contiguous region of virtual memory

• e.g. 2 MB superpage consists of 512 regular pages (4 KB)

• aligned to lie on a 2 MB boundary

→ fewer TLB-Entries needed

8 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 45: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Superpages / Page sizes www.tugraz.at

Set of contiguous pages in physical memory that map a contiguous region of virtual memory

• e.g. 2 MB superpage consists of 512 regular pages (4 KB)

• aligned to lie on a 2 MB boundary

→ fewer TLB-Entries needed

8 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 46: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How long does the TLB stay valid? www.tugraz.at

Context switches:

• Do we have to invalidate the entire TLB?

Solution: Tagged TLB

• Each TLB entry has a tag (PID or CR3 or ...)

• TLB hit only if tag matches current register state

9 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 47: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How long does the TLB stay valid? www.tugraz.at

Context switches:

• Do we have to invalidate the entire TLB?

Solution: Tagged TLB

• Each TLB entry has a tag (PID or CR3 or ...)

• TLB hit only if tag matches current register state

9 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 48: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How long does the TLB stay valid? www.tugraz.at

Context switches:

• Do we have to invalidate the entire TLB?

Solution: Tagged TLB

• Each TLB entry has a tag (PID or CR3 or ...)

• TLB hit only if tag matches current register state

9 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 49: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How long does the TLB stay valid? www.tugraz.at

Context switches:

• Do we have to invalidate the entire TLB?

Solution: Tagged TLB

• Each TLB entry has a tag (PID or CR3 or ...)

• TLB hit only if tag matches current register state

9 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 50: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How long does the TLB stay valid? www.tugraz.at

Context switches:

• Do we have to invalidate the entire TLB?

Solution: Tagged TLB

• Each TLB entry has a tag (PID or CR3 or ...)

• TLB hit only if tag matches current register state

9 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 51: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How long does the TLB stay valid? www.tugraz.at

Context switches:

• Do we have to invalidate the entire TLB?

Solution: Tagged TLB

• Each TLB entry has a tag (PID or CR3 or ...)

• TLB hit only if tag matches current register state

9 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 52: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Tagged TLB www.tugraz.at

10 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 53: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How long does the TLB stay valid? (2) www.tugraz.at

What happens when OS changes permissions on a page?

• demand paging (zero on reference)

• copy on write

TLB may contain old information

• OS must ask hardware to purge TLB entry

On a multicore: TLB shootdown

• OS must ask each CPU to purge TLB entry

11 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 54: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How long does the TLB stay valid? (2) www.tugraz.at

What happens when OS changes permissions on a page?

• demand paging (zero on reference)

• copy on write

TLB may contain old information

• OS must ask hardware to purge TLB entry

On a multicore: TLB shootdown

• OS must ask each CPU to purge TLB entry

11 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 55: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How long does the TLB stay valid? (2) www.tugraz.at

What happens when OS changes permissions on a page?

• demand paging (zero on reference)

• copy on write

TLB may contain old information

• OS must ask hardware to purge TLB entry

On a multicore: TLB shootdown

• OS must ask each CPU to purge TLB entry

11 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 56: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How long does the TLB stay valid? (2) www.tugraz.at

What happens when OS changes permissions on a page?

• demand paging (zero on reference)

• copy on write

TLB may contain old information

• OS must ask hardware to purge TLB entry

On a multicore: TLB shootdown

• OS must ask each CPU to purge TLB entry

11 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 57: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How long does the TLB stay valid? (2) www.tugraz.at

What happens when OS changes permissions on a page?

• demand paging (zero on reference)

• copy on write

TLB may contain old information

• OS must ask hardware to purge TLB entry

On a multicore: TLB shootdown

• OS must ask each CPU to purge TLB entry

11 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 58: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

How long does the TLB stay valid? (2) www.tugraz.at

What happens when OS changes permissions on a page?

• demand paging (zero on reference)

• copy on write

TLB may contain old information

• OS must ask hardware to purge TLB entry

On a multicore: TLB shootdown

• OS must ask each CPU to purge TLB entry

11 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 59: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Memory Layout

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Loader www.tugraz.at

• Parse binary (headers)

• different binary formats

• .COM - program always starts at byte 256 (also used in CP/M)

• a.out

• COFF

• Executable and Linking Format (ELF)

12 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Memory Layout User Space on www.tugraz.at

user space

0 247

• PLT: Procedure Linkage Table

• GOT: Global Object Table

13 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Memory Layout User Space on www.tugraz.at

0 247

• PLT: Procedure Linkage Table

• GOT: Global Object Table

13 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 63: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Memory Layout User Space on www.tugraz.at

cod

e

0 247

• PLT: Procedure Linkage Table

• GOT: Global Object Table

13 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 64: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Memory Layout User Space on www.tugraz.at

cod

e

da

ta

0 247

• PLT: Procedure Linkage Table

• GOT: Global Object Table

13 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 65: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Memory Layout User Space on www.tugraz.at

cod

e

da

ta

bss

0 247

• PLT: Procedure Linkage Table

• GOT: Global Object Table

13 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 66: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Memory Layout User Space on www.tugraz.at

cod

e

da

ta

bss

hea

p

0 247

• PLT: Procedure Linkage Table

• GOT: Global Object Table

13 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 67: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Memory Layout User Space on www.tugraz.at

cod

e

da

ta

bss

hea

p

shar

edm

emor

y

0 247

• PLT: Procedure Linkage Table

• GOT: Global Object Table

13 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 68: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Memory Layout User Space on www.tugraz.at

cod

e

da

ta

bss

hea

p

shar

edm

emor

y

shar

edlib

rari

es

0 247

• PLT: Procedure Linkage Table

• GOT: Global Object Table

13 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 69: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Memory Layout User Space on www.tugraz.at

cod

e

da

ta

bss

hea

p

shar

edm

emor

y

shar

edlib

rari

es

sta

ck

0 247

• PLT: Procedure Linkage Table

• GOT: Global Object Table

13 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 70: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Memory Layout User Space on www.tugraz.at

cod

e

plt

da

ta

bss

hea

p

shar

edm

emor

y

shar

edlib

rari

es

sta

ck

0 247

• PLT: Procedure Linkage Table

• GOT: Global Object Table

13 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 71: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Memory Layout User Space on www.tugraz.at

cod

e

plt

da

ta

go

t

bss

hea

p

shar

edm

emor

y

shar

edlib

rari

es

sta

ck

0 247

• PLT: Procedure Linkage Table

• GOT: Global Object Table

13 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Code www.tugraz.at

• Executable

• Usually readable

• Usually not writable

14 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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ELF Binaries www.tugraz.at

Equivalent C code

0 1 2 3 4 5 6 7 8 9 A B C D E F

00: 7F .E .L .F 01 01 01

10: 02 00 03 00 01 00 00 00 60 00 00 08 40 00 00 00

20: 34 00 20 00 01 00

40: 01 00 00 00 00 00 00 00 00 00 00 08 00 00 00 08

50: 70 00 00 00 70 00 00 00 05 00 00 00

60: BB 2A 00 00 00 B8 01 00 00 00 CD 80

code

ELF headeridentify as an ELF type

specify the architecture

x86 assembly

Fields Values

return 42;

me@nux:~$ ./minime@nux:~$ echo $?42

Program Headertable

Execution information

e_ident

EI_MAG

EI_CLASS, EI_DATA

EI_VERSION

e_type

e_machine

e_version

e_entry

e_phoff

e_ehsize

e_phentsize

e_phnum

p_type

p_offset

p_vaddr

p_paddr

p_filesz

p_memsz

p_flags

0x7F, "ELF"

1 ,1

1

2

3

1

0x8000060

0x0000040

0x0034

0x0020

0001

ELFDATA2LSBELFCLASS32

EV_CURRENT

ET_EXEC

EM_386

EV_CURRENT

1

0

0x8000000

0x8000000

0x0000070

0x0000070

5

PT_LOAD

PF_R|PF_X

mov ebx, 42

mov eax, 1

int 80h

SC_EXIT

15 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 74: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

ELF www.tugraz.at

• object files (compiled code)

• dynamic libraries

• static libraries

16 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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ELF www.tugraz.at

• object files (compiled code)

• dynamic libraries

• static libraries

16 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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ELF www.tugraz.at

• object files (compiled code)

• dynamic libraries

• static libraries

16 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 77: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Loading www.tugraz.at

• What about the stack?

• Size? Address?

• Locate a suitable address area for the stack

• Define the initial size of the area

• Load on demand

• Data from binary

• Zeros (security!)

17 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 78: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Loading www.tugraz.at

• What about the stack?

• Size? Address?

• Locate a suitable address area for the stack

• Define the initial size of the area

• Load on demand

• Data from binary

• Zeros (security!)

17 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 79: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Loading www.tugraz.at

• What about the stack?

• Size? Address?

• Locate a suitable address area for the stack

• Define the initial size of the area

• Load on demand

• Data from binary

• Zeros (security!)

17 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 80: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Loading www.tugraz.at

• What about the stack?

• Size? Address?

• Locate a suitable address area for the stack

• Define the initial size of the area

• Load on demand

• Data from binary

• Zeros (security!)

17 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 81: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Loading www.tugraz.at

• What about the stack?

• Size? Address?

• Locate a suitable address area for the stack

• Define the initial size of the area

• Load on demand

• Data from binary

• Zeros (security!)

17 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 82: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Loading www.tugraz.at

• What about the stack?

• Size? Address?

• Locate a suitable address area for the stack

• Define the initial size of the area

• Load on demand

• Data from binary

• Zeros (security!)

17 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Loading www.tugraz.at

• What about the stack?

• Size? Address?

• Locate a suitable address area for the stack

• Define the initial size of the area

• Load on demand

• Data from binary

• Zeros (security!)

17 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Address Space Layout Randomization (ASLR) www.tugraz.at

Every program start, use different

random offsets for

• program sections

• libraries

• heap

• stacks

→ Addresses are unpredictable for an

attacker

Process A

0 −1

Process B

0 −1

Process C

0 −1

18 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Address Space Layout Randomization (ASLR) www.tugraz.at

Every program start, use different

random offsets for

• program sections

• libraries

• heap

• stacks

→ Addresses are unpredictable for an

attacker

Process A

0 −1

Process B

0 −1

Process C

0 −1

18 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 86: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Address Space Layout Randomization (ASLR) www.tugraz.at

Every program start, use different

random offsets for

• program sections

• libraries

• heap

• stacks

→ Addresses are unpredictable for an

attacker

Process A

0 −1

Process B

0 −1

Process C

0 −1

18 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 87: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Address Space Layout Randomization (ASLR) www.tugraz.at

Every program start, use different

random offsets for

• program sections

• libraries

• heap

• stacks

→ Addresses are unpredictable for an

attacker

Process A

0 −1

Process B

0 −1

Process C

0 −1

18 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 88: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Address Space Layout Randomization (ASLR) www.tugraz.at

Every program start, use different

random offsets for

• program sections

• libraries

• heap

• stacks

→ Addresses are unpredictable for an

attacker

Process A

0 −1

Process B

0 −1

Process C

0 −1

18 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 89: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Memory Layout Revisited www.tugraz.at

• OS has to layout the linear memory for a process

• only addresses can be accessed that are mapped into the process address space via the

page table mechanism

• decision: do we also map the kernel into the process address space?

19 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 90: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Memory Layout Revisited www.tugraz.at

• OS has to layout the linear memory for a process

• only addresses can be accessed that are mapped into the process address space via the

page table mechanism

• decision: do we also map the kernel into the process address space?

19 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 91: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Memory Layout Revisited www.tugraz.at

• OS has to layout the linear memory for a process

• only addresses can be accessed that are mapped into the process address space via the

page table mechanism

• decision: do we also map the kernel into the process address space?

19 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Memory layout www.tugraz.at

20 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Memory Layout x86-32 www.tugraz.at

• 32-bit addresses: memory locations between 0 GB and 4 GB

• x86 requires a minimal region of the kernel to be mapped (for context switches)

• typically a large part of the linear address space is reserved for the kernel

• inaccessible due to userspace permission bit (set to 0 for kernel pages)

21 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Memory Layout x86-32 www.tugraz.at

• 32-bit addresses: memory locations between 0 GB and 4 GB

• x86 requires a minimal region of the kernel to be mapped (for context switches)

• typically a large part of the linear address space is reserved for the kernel

• inaccessible due to userspace permission bit (set to 0 for kernel pages)

21 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Memory Layout x86-32 www.tugraz.at

• 32-bit addresses: memory locations between 0 GB and 4 GB

• x86 requires a minimal region of the kernel to be mapped (for context switches)

• typically a large part of the linear address space is reserved for the kernel

• inaccessible due to userspace permission bit (set to 0 for kernel pages)

21 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Memory Layout x86-32 www.tugraz.at

• 32-bit addresses: memory locations between 0 GB and 4 GB

• x86 requires a minimal region of the kernel to be mapped (for context switches)

• typically a large part of the linear address space is reserved for the kernel

• inaccessible due to userspace permission bit (set to 0 for kernel pages)

21 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Linux Address Space on x86-64 www.tugraz.at

0000000000000000-00007fffffffffff (=47 bits) user space

ffff800000000000-ffff87ffffffffff (=43 bits) hypervisor

ffff880000000000-ffffc7ffffffffff (=64 TB) identity mapping

ffffc90000000000-ffffe8ffffffffff (=45 bits) vmalloc/ioremap space

ffffea0000000000-ffffeaffffffffff (=40 bits) virtual memory map

ffffec0000000000-fffffbffffffffff (=44 bits) KASAN shadow memory

ffffff0000000000-ffffff7fffffffff (=39 bits) ESP fixup stacks

ffffffef00000000-fffffffeffffffff (=64 GB) EFI region mappings

ffffffff80000000-ffffffff9fffffff (=512 MB) kernel code/data

ffffffffa0000000-ffffffffff5fffff (=1526 MB) kernel modules

ffffffffff600000-ffffffffffdfffff (=8 MB) vsyscalls

22 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Page Replacement

Page 99: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Replacement www.tugraz.at

• At some point in time, physical memory will become full

• We need to make space available → throw out (= evict ) a page

• Unmodified code and data could be reloaded from binary

• What about other memory contents (modified from disk or generated)?

• When do we perform page replacement?

For now:

• When not a single page is available, and

• a thread T tries to allocate a page.

→ We evict a page, clear it, and return it (the now free page) directly to thread T .

23 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 100: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Replacement www.tugraz.at

• At some point in time, physical memory will become full

• We need to make space available → throw out (= evict ) a page

• Unmodified code and data could be reloaded from binary

• What about other memory contents (modified from disk or generated)?

• When do we perform page replacement?

For now:

• When not a single page is available, and

• a thread T tries to allocate a page.

→ We evict a page, clear it, and return it (the now free page) directly to thread T .

23 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 101: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Replacement www.tugraz.at

• At some point in time, physical memory will become full

• We need to make space available → throw out (= evict ) a page

• Unmodified code and data could be reloaded from binary

• What about other memory contents (modified from disk or generated)?

• When do we perform page replacement?

For now:

• When not a single page is available, and

• a thread T tries to allocate a page.

→ We evict a page, clear it, and return it (the now free page) directly to thread T .

23 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 102: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Replacement www.tugraz.at

• At some point in time, physical memory will become full

• We need to make space available → throw out (= evict ) a page

• Unmodified code and data could be reloaded from binary

• What about other memory contents (modified from disk or generated)?

• When do we perform page replacement?

For now:

• When not a single page is available, and

• a thread T tries to allocate a page.

→ We evict a page, clear it, and return it (the now free page) directly to thread T .

23 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 103: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Replacement www.tugraz.at

• At some point in time, physical memory will become full

• We need to make space available → throw out (= evict ) a page

• Unmodified code and data could be reloaded from binary

• What about other memory contents (modified from disk or generated)?

• When do we perform page replacement?

For now:

• When not a single page is available, and

• a thread T tries to allocate a page.

→ We evict a page, clear it, and return it (the now free page) directly to thread T .

23 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 104: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Replacement www.tugraz.at

• At some point in time, physical memory will become full

• We need to make space available → throw out (= evict ) a page

• Unmodified code and data could be reloaded from binary

• What about other memory contents (modified from disk or generated)?

• When do we perform page replacement?

For now:

• When not a single page is available, and

• a thread T tries to allocate a page.

→ We evict a page, clear it, and return it (the now free page) directly to thread T .

23 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 105: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Replacement www.tugraz.at

• At some point in time, physical memory will become full

• We need to make space available → throw out (= evict ) a page

• Unmodified code and data could be reloaded from binary

• What about other memory contents (modified from disk or generated)?

• When do we perform page replacement? For now:

• When not a single page is available, and

• a thread T tries to allocate a page.

→ We evict a page, clear it, and return it (the now free page) directly to thread T .

23 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 106: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Replacement www.tugraz.at

• At some point in time, physical memory will become full

• We need to make space available → throw out (= evict ) a page

• Unmodified code and data could be reloaded from binary

• What about other memory contents (modified from disk or generated)?

• When do we perform page replacement? For now:

• When not a single page is available, and

• a thread T tries to allocate a page.

→ We evict a page, clear it, and return it (the now free page) directly to thread T .

23 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 107: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Replacement www.tugraz.at

• At some point in time, physical memory will become full

• We need to make space available → throw out (= evict ) a page

• Unmodified code and data could be reloaded from binary

• What about other memory contents (modified from disk or generated)?

• When do we perform page replacement? For now:

• When not a single page is available, and

• a thread T tries to allocate a page.

→ We evict a page, clear it, and return it (the now free page) directly to thread T .

23 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 108: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

What to do with modified pages? www.tugraz.at

Swap Out

• Reserve a special area on the disk

• swap file

• swap partition

• swap disk

• Write modified page there

• Evict it from RAM

24 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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What to do with modified pages? www.tugraz.at

Swap Out

• Reserve a special area on the disk

• swap file

• swap partition

• swap disk

• Write modified page there

• Evict it from RAM

24 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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What to do with modified pages? www.tugraz.at

Swap Out

• Reserve a special area on the disk

• swap file

• swap partition

• swap disk

• Write modified page there

• Evict it from RAM

24 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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What to do with modified pages? www.tugraz.at

Swap Out

• Reserve a special area on the disk

• swap file

• swap partition

• swap disk

• Write modified page there

• Evict it from RAM

24 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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What to do with modified pages? www.tugraz.at

Swap Out

• Reserve a special area on the disk

• swap file

• swap partition

• swap disk

• Write modified page there

• Evict it from RAM

24 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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What to do with modified pages? www.tugraz.at

Swap Out

• Reserve a special area on the disk

• swap file

• swap partition

• swap disk

• Write modified page there

• Evict it from RAM

24 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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What to do with modified pages? www.tugraz.at

Swap Out

• Reserve a special area on the disk

• swap file

• swap partition

• swap disk

• Write modified page there

• Evict it from RAM

24 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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What to do with modified pages? www.tugraz.at

Swap Out

• Reserve a special area on the disk

• swap file

• swap partition

• swap disk

• Write modified page there

• Evict it from RAM

24 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Swapping www.tugraz.at

• static assignment

• low overhead

• not “on demand”: waste of disk space

• dynamic assignment

• larger overhead

• on demand: no wasted disk space

25 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Swapping www.tugraz.at

• static assignment

• low overhead

• not “on demand”: waste of disk space

• dynamic assignment

• larger overhead

• on demand: no wasted disk space

25 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Swapping www.tugraz.at

• static assignment

• low overhead

• not “on demand”: waste of disk space

• dynamic assignment

• larger overhead

• on demand: no wasted disk space

25 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Swapping www.tugraz.at

• static assignment

• low overhead

• not “on demand”: waste of disk space

• dynamic assignment

• larger overhead

• on demand: no wasted disk space

25 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Swapping www.tugraz.at

• static assignment

• low overhead

• not “on demand”: waste of disk space

• dynamic assignment

• larger overhead

• on demand: no wasted disk space

25 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Swapping www.tugraz.at

• static assignment

• low overhead

• not “on demand”: waste of disk space

• dynamic assignment

• larger overhead

• on demand: no wasted disk space

25 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Swapping www.tugraz.at

• static assignment

• low overhead

• not “on demand”: waste of disk space

• dynamic assignment

• larger overhead

• on demand: no wasted disk space

25 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Swapping www.tugraz.at

• static assignment

• low overhead

• not “on demand”: waste of disk space

• dynamic assignment

• larger overhead

• on demand: no wasted disk space

25 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 124: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Swapping www.tugraz.at

• static assignment

• low overhead

• not “on demand”: waste of disk space

• dynamic assignment

• larger overhead

• on demand: no wasted disk space

25 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 125: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Swapping www.tugraz.at

• static assignment

• low overhead

• not “on demand”: waste of disk space

• dynamic assignment

• larger overhead

• on demand: no wasted disk space

25 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 126: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

The Most Simple Page Replacement Algorithm (PRA): Random www.tugraz.at

• Simply evict a random page, any page.

• How good is Random PRA? It’s a good start...

• Often used as replacement algorithm in caches (ARM processors)

• Source of randomness? Not that important, e.g., rdtsc

26 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 127: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

The Most Simple Page Replacement Algorithm (PRA): Random www.tugraz.at

• Simply evict a random page, any page.

• How good is Random PRA?

It’s a good start...

• Often used as replacement algorithm in caches (ARM processors)

• Source of randomness? Not that important, e.g., rdtsc

26 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 128: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

The Most Simple Page Replacement Algorithm (PRA): Random www.tugraz.at

• Simply evict a random page, any page.

• How good is Random PRA?

It’s a good start...

• Often used as replacement algorithm in caches (ARM processors)

• Source of randomness? Not that important, e.g., rdtsc

26 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 129: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

The Most Simple Page Replacement Algorithm (PRA): Random www.tugraz.at

• Simply evict a random page, any page.

• How good is Random PRA?

It’s a good start...

• Often used as replacement algorithm in caches (ARM processors)

• Source of randomness? Not that important, e.g., rdtsc

26 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 130: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

The Most Simple Page Replacement Algorithm (PRA): Random www.tugraz.at

• Simply evict a random page, any page.

• How good is Random PRA? It’s a good start...

• Often used as replacement algorithm in caches (ARM processors)

• Source of randomness?

Not that important, e.g., rdtsc

26 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 131: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

The Most Simple Page Replacement Algorithm (PRA): Random www.tugraz.at

• Simply evict a random page, any page.

• How good is Random PRA? It’s a good start...

• Often used as replacement algorithm in caches (ARM processors)

• Source of randomness?

Not that important, e.g., rdtsc

26 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 132: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

The Most Simple Page Replacement Algorithm (PRA): Random www.tugraz.at

• Simply evict a random page, any page.

• How good is Random PRA? It’s a good start...

• Often used as replacement algorithm in caches (ARM processors)

• Source of randomness?

Not that important, e.g., rdtsc

26 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 133: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

The Most Simple Page Replacement Algorithm (PRA): Random www.tugraz.at

• Simply evict a random page, any page.

• How good is Random PRA? It’s a good start...

• Often used as replacement algorithm in caches (ARM processors)

• Source of randomness? Not that important, e.g., rdtsc

26 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 134: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Pros:

• Very simple to implement in software or

hardware

• No state, no precomputations, fast

decision, tiny code base

• May perform better than several more

complex PRAs

Cons:

• PRA could use more information to not

evict pages which are frequently used /

required in the near future

27 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 135: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Pros:

• Very simple to implement in software or

hardware

• No state, no precomputations, fast

decision, tiny code base

• May perform better than several more

complex PRAs

Cons:

• PRA could use more information to not

evict pages which are frequently used /

required in the near future

27 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 136: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Pros:

• Very simple to implement in software or

hardware

• No state, no precomputations, fast

decision, tiny code base

• May perform better than several more

complex PRAs

Cons:

• PRA could use more information to not

evict pages which are frequently used /

required in the near future

27 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 137: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Pros:

• Very simple to implement in software or

hardware

• No state, no precomputations, fast

decision, tiny code base

• May perform better than several more

complex PRAs

Cons:

• PRA could use more information to not

evict pages which are frequently used /

required in the near future

27 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 138: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Pros:

• Very simple to implement in software or

hardware

• No state, no precomputations, fast

decision, tiny code base

• May perform better than several more

complex PRAs

Cons:

• PRA could use more information to not

evict pages which are frequently used /

required in the near future

27 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 139: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Pros:

• Very simple to implement in software or

hardware

• No state, no precomputations, fast

decision, tiny code base

• May perform better than several more

complex PRAs

Cons:

• PRA could use more information to not

evict pages which are frequently used /

required in the near future

27 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 140: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Pros:

• Very simple to implement in software or

hardware

• No state, no precomputations, fast

decision, tiny code base

• May perform better than several more

complex PRAs

Cons:

• PRA could use more information to not

evict pages which are frequently used /

required in the near future

27 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 141: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Pros:

• Very simple to implement in software or

hardware

• No state, no precomputations, fast

decision, tiny code base

• May perform better than several more

complex PRAs

Cons:

• PRA could use more information to not

evict pages which are frequently used /

required in the near future

27 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 142: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Pros:

• Very simple to implement in software or

hardware

• No state, no precomputations, fast

decision, tiny code base

• May perform better than several more

complex PRAs

Cons:

• PRA could use more information to not

evict pages which are frequently used /

required in the near future

27 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 143: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 144: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 145: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 146: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 147: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 148: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 55 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

?

?

?

?

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 149: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 55 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 150: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 22 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 151: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 00 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

0A

2C

?

?

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 152: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 77 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

0A

2C

?

?

0A

2C

?7H

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 153: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 66 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

0A

2C

?

?

0A

2C

?7H

6G

2C

?7H

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 154: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 77 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

0A

2C

?

?

0A

2C

?7H

6G

2C

?7H

6G

2C

?7H

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 155: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 33 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

0A

2C

?

?

0A

2C

?7H

6G

2C

?7H

6G

2C

?7H

3D

2C

?7H

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 156: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 11 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

0A

2C

?

?

0A

2C

?7H

6G

2C

?7H

6G

2C

?7H

3D

2C

?7H

3D

2C

?1B

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 157: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 77 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

0A

2C

?

?

0A

2C

?7H

6G

2C

?7H

6G

2C

?7H

3D

2C

?7H

3D

2C

?1B

3D

2C

?7H

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 158: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 66 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

0A

2C

?

?

0A

2C

?7H

6G

2C

?7H

6G

2C

?7H

3D

2C

?7H

3D

2C

?1B

3D

2C

?7H

3D

2C

?6G

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 159: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 22 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

0A

2C

?

?

0A

2C

?7H

6G

2C

?7H

6G

2C

?7H

3D

2C

?7H

3D

2C

?1B

3D

2C

?7H

3D

2C

?6G

3D

2C

?6G

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 160: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 77 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

0A

2C

?

?

0A

2C

?7H

6G

2C

?7H

6G

2C

?7H

3D

2C

?7H

3D

2C

?1B

3D

2C

?7H

3D

2C

?6G

3D

2C

?6G

3D

7H

?6G

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 161: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 00 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

0A

2C

?

?

0A

2C

?7H

6G

2C

?7H

6G

2C

?7H

3D

2C

?7H

3D

2C

?1B

3D

2C

?7H

3D

2C

?6G

3D

2C

?6G

3D

7H

?6G

0A

7H

?6G

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 162: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 55 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

0A

2C

?

?

0A

2C

?7H

6G

2C

?7H

6G

2C

?7H

3D

2C

?7H

3D

2C

?1B

3D

2C

?7H

3D

2C

?6G

3D

2C

?6G

3D

7H

?6G

0A

7H

?6G

0A

7H

5F

6G

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 163: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 44 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

0A

2C

?

?

0A

2C

?7H

6G

2C

?7H

6G

2C

?7H

3D

2C

?7H

3D

2C

?1B

3D

2C

?7H

3D

2C

?6G

3D

2C

?6G

3D

7H

?6G

0A

7H

?6G

0A

7H

5F

6G

0A

7H

4E

6G

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 164: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 33

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

0A

2C

?

?

0A

2C

?7H

6G

2C

?7H

6G

2C

?7H

3D

2C

?7H

3D

2C

?1B

3D

2C

?7H

3D

2C

?6G

3D

2C

?6G

3D

7H

?6G

0A

7H

?6G

0A

7H

5F

6G

0A

7H

4E

6G

0A

7H

3D

6G

2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 165: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Random PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

?

?

?

?

Time

5F

?

?

?

5F

2C

?

?

0A

2C

?

?

0A

2C

?7H

6G

2C

?7H

6G

2C

?7H

3D

2C

?7H

3D

2C

?1B

3D

2C

?7H

3D

2C

?6G

3D

2C

?6G

3D

7H

?6G

0A

7H

?6G

0A

7H

5F

6G

0A

7H

4E

6G

0A

7H

3D

6G

2 hits, 14 misses → rather bad2 hits, 14 misses → rather bad

28 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 166: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

The Best Replacement Algorithm: Optimal PRA www.tugraz.at

Let’s assume, we can predict the future

1. Store number of steps until next access (per page)

2. Remove page with largest number

29 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 167: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

The Best Replacement Algorithm: Optimal PRA www.tugraz.at

Let’s assume, we can predict the future

1. Store number of steps until next access (per page)

2. Remove page with largest number

29 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 168: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

The Best Replacement Algorithm: Optimal PRA www.tugraz.at

Let’s assume, we can predict the future

1. Store number of steps until next access (per page)

2. Remove page with largest number

29 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 169: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

?

?

?

?

?

?

?

?

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 170: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 55 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

14

?

?

?

?

?

?

?

5F

?

?

?

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 171: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 22 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

14

11

?

?

?

?

?

?

5F

?

?

?

5F

2C

?

?

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 172: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 00 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

14

11

13

?

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 173: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 77 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

14

11

13

6

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 174: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 66 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

10

11

13

6

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 175: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 77 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

10

11

13

9

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 176: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 33 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

10

11

16

9

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

2C

3D

7H

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 177: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 11 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

10

11

?

9

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

2C

3D

7H

6G

2C

1B

7H

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 178: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 77 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

10

11

?

12

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

2C

3D

7H

6G

2C

1B

7H

6G

2C

1B

7H

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 179: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 66 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

?

11

?

12

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

2C

3D

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 180: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 22 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

?

?

?

12

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

2C

3D

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 181: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 77 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

?

?

?

?

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

2C

3D

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 182: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 00 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

?

?

?

?

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

2C

3D

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

0A

2C

1B

7H

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 183: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 55 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

?

?

?

?

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

2C

3D

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

0A

2C

1B

7H

0A

2C

5F

7H

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 184: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 44 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

?

?

?

?

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

2C

3D

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

0A

2C

1B

7H

0A

2C

5F

7H

0A

2C

4E

7H

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 185: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 33

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Nex

tA

cces

s

atS

tep

:

?

?

?

?

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

2C

3D

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

0A

2C

1B

7H

0A

2C

5F

7H

0A

2C

4E

7H

0A

2C

3D

7H

5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 186: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Optimal PRA www.tugraz.at

Disk

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Time

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s

atS

tep

:

?

?

?

?

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

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0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

2C

3D

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

0A

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7H

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5F

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5 hits, 11 misses

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atS

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?

?

?

?

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5F

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5F

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5F

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0A

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5F

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2C

3D

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7H

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7H

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5 hits, 11 misses5 hits, 11 misses

30 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Predict the Future www.tugraz.at

• We can’t look into the future...

• Principle of locality

• future memory access might be near past memory accesses

• design idea of virtually all sophisticated PRAs

→ How do we learn past memory accesses?

31 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Predict the Future www.tugraz.at

• We can’t look into the future...

• Principle of locality

• future memory access might be near past memory accesses

• design idea of virtually all sophisticated PRAs

→ How do we learn past memory accesses?

31 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Predict the Future www.tugraz.at

• We can’t look into the future...

• Principle of locality

• future memory access might be near past memory accesses

• design idea of virtually all sophisticated PRAs

→ How do we learn past memory accesses?

31 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Predict the Future www.tugraz.at

• We can’t look into the future...

• Principle of locality

• future memory access might be near past memory accesses

• design idea of virtually all sophisticated PRAs

→ How do we learn past memory accesses?

31 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Predict the Future www.tugraz.at

• We can’t look into the future...

• Principle of locality

• future memory access might be near past memory accesses

• design idea of virtually all sophisticated PRAs

→ How do we learn past memory accesses?

31 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Predict the Future www.tugraz.at

• We can’t look into the future...

• Principle of locality

• future memory access might be near past memory accesses

• design idea of virtually all sophisticated PRAs

→ How do we learn past memory accesses?

31 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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32 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Physical Page Number

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Ignored

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How to detect accesses? www.tugraz.at

Problem: 1 bit of information is not a detailed trace of past memory accesses

How do we get the information we need?

33 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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34 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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34 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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34 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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34 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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34 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Detecting reads and writes www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Referenced

1

0

0

0

1

1

0

0

Dirty

1

0

0

0

0

0

0

0

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 44 3

Time

write

OSread

34 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 231: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Detecting reads and writes www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Referenced

1

0

0

1

1

1

0

0

Dirty

1

0

0

0

0

0

0

0

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 33

Time

write

OSread

34 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 232: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Detecting reads and writes www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Referenced

1

0

0

1

1

1

0

0

Dirty

1

0

0

0

0

0

0

0

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time

write

OS

read

and

rese

t

34 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 233: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Detecting reads and writes www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Referenced

0

0

0

0

0

0

0

0

Dirty

0

0

0

0

0

0

0

0

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time

write

OS

34 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 234: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

General Ideas on Page Replacement: Four Classes of Pages www.tugraz.at

Which is the best class to choose pages from for replacement?

Class Referenced Dirty Properties

0 0 0

1 0 1

2 1 0

3 1 1

Dirty = it’s not stored identically on the disk

35 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 235: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

General Ideas on Page Replacement: Four Classes of Pages www.tugraz.at

Which is the best class to choose pages from for replacement?

Class Referenced Dirty Properties

0 0 0 Not used in a while and not modified → just evict

1 0 1

2 1 0

3 1 1

Dirty = it’s not stored identically on the disk

35 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 236: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

General Ideas on Page Replacement: Four Classes of Pages www.tugraz.at

Which is the best class to choose pages from for replacement?

Class Referenced Dirty Properties

0 0 0 Not used in a while and not modified → just evict

1 0 1 Not used in a while but modified → write back, then evict

2 1 0

3 1 1

Dirty = it’s not stored identically on the disk

35 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 237: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

General Ideas on Page Replacement: Four Classes of Pages www.tugraz.at

Which is the best class to choose pages from for replacement?

Class Referenced Dirty Properties

0 0 0 Not used in a while and not modified → just evict

1 0 1 Not used in a while but modified → write back, then evict

2 1 0 Recently used but not modified→ prefer eviction of other pages

3 1 1

Dirty = it’s not stored identically on the disk

35 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 238: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

General Ideas on Page Replacement: Four Classes of Pages www.tugraz.at

Which is the best class to choose pages from for replacement?

Class Referenced Dirty Properties

0 0 0 Not used in a while and not modified → just evict

1 0 1 Not used in a while but modified → write back, then evict

2 1 0 Recently used but not modified→ prefer eviction of other pages

3 1 1 Recently used and modified → only evict as a last resort

Dirty = it’s not stored identically on the disk

35 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 239: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Not Recently Used PRA www.tugraz.at

• Basically: Random PRA with classes (0-3)

• Performes better than Random PRA

• Design Decision: How far does “recently” go?

36 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 240: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Not Recently Used PRA www.tugraz.at

• Basically: Random PRA with classes (0-3)

• Performes better than Random PRA

• Design Decision: How far does “recently” go?

36 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 241: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Not Recently Used PRA www.tugraz.at

• Basically: Random PRA with classes (0-3)

• Performes better than Random PRA

• Design Decision: How far does “recently” go?

36 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 242: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

0

0

0

0

?

?

?

?

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 243: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 55 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

3

0

0

0

?

?

?

?

5F

?

?

?

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 244: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 22 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

3

2

0

0

?

?

?

?

5F

?

?

?

5F

2C

?

?

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 245: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 00 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

3

2

0

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

?0A

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 246: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 77 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

3

2

3

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

?0A

5F

2C

7H

0A

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 247: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 66 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

1

2

3

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

?0A

5F

2C

7H

0A

5F

6G

7H

0A

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 248: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 77 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

1

2

3

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

?0A

5F

2C

7H

0A

5F

6G

7H

0A

5F

6G

7H

0A

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 249: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 33 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

2

2

3

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

?0A

5F

2C

7H

0A

5F

6G

7H

0A

5F

6G

7H

0A

3D

6G

7H

0A

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 250: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 11 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

2

2

3

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

?0A

5F

2C

7H

0A

5F

6G

7H

0A

5F

6G

7H

0A

3D

6G

7H

0A

3D

6G

7H

1B

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 251: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 77 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

2

0

3

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

?0A

5F

2C

7H

0A

5F

6G

7H

0A

5F

6G

7H

0A

3D

6G

7H

0A

3D

6G

7H

1B

3D

6G

7H

1B

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 252: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 66 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

2

3

3

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

?0A

5F

2C

7H

0A

5F

6G

7H

0A

5F

6G

7H

0A

3D

6G

7H

0A

3D

6G

7H

1B

3D

6G

7H

1B

3D

6G

7H

1B

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 253: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 22 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

2

3

3

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

?0A

5F

2C

7H

0A

5F

6G

7H

0A

5F

6G

7H

0A

3D

6G

7H

0A

3D

6G

7H

1B

3D

6G

7H

1B

3D

6G

7H

1B

2C

6G

7H

1B

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 254: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 77 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

2

3

3

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

?0A

5F

2C

7H

0A

5F

6G

7H

0A

5F

6G

7H

0A

3D

6G

7H

0A

3D

6G

7H

1B

3D

6G

7H

1B

3D

6G

7H

1B

2C

6G

7H

1B

2C

6G

7H

1B

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 255: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 00 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

2

3

3

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

?0A

5F

2C

7H

0A

5F

6G

7H

0A

5F

6G

7H

0A

3D

6G

7H

0A

3D

6G

7H

1B

3D

6G

7H

1B

3D

6G

7H

1B

2C

6G

7H

1B

2C

6G

7H

1B

2C

6G

7H

0A

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 256: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 55 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

2

1

3

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

?0A

5F

2C

7H

0A

5F

6G

7H

0A

5F

6G

7H

0A

3D

6G

7H

0A

3D

6G

7H

1B

3D

6G

7H

1B

3D

6G

7H

1B

2C

6G

7H

1B

2C

6G

7H

1B

2C

6G

7H

0A

5F

6G

7H

0A

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 257: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 44 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

2

2

3

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

?0A

5F

2C

7H

0A

5F

6G

7H

0A

5F

6G

7H

0A

3D

6G

7H

0A

3D

6G

7H

1B

3D

6G

7H

1B

3D

6G

7H

1B

2C

6G

7H

1B

2C

6G

7H

1B

2C

6G

7H

0A

5F

6G

7H

0A

5F

4E

7H

0A

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 258: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 33

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

2

2

1

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

?0A

5F

2C

7H

0A

5F

6G

7H

0A

5F

6G

7H

0A

3D

6G

7H

0A

3D

6G

7H

1B

3D

6G

7H

1B

3D

6G

7H

1B

2C

6G

7H

1B

2C

6G

7H

1B

2C

6G

7H

0A

5F

6G

7H

0A

5F

4E

7H

0A

3D

4E

7H

0A

4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 259: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Cla

ss

2

2

1

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

?0A

5F

2C

7H

0A

5F

6G

7H

0A

5F

6G

7H

0A

3D

6G

7H

0A

3D

6G

7H

1B

3D

6G

7H

1B

3D

6G

7H

1B

2C

6G

7H

1B

2C

6G

7H

1B

2C

6G

7H

0A

5F

6G

7H

0A

5F

4E

7H

0A

3D

4E

7H

0A

4 hits, 12 misses4 hits, 12 misses

37 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 260: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

First-In First-Out (FIFO) PRA www.tugraz.at

First-in First-Out

• Queue/List of all pages (e.g. std::queue)

• Load a page: push back

• Page to replace: pop front

• Very simple algorithm

• Rarely used in practice

• Performance can even be worse than Random PRA(!)

+ FIFO anomaly / Belady’s anomaly: increasing memory size can reduce performance

38 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 261: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

First-In First-Out (FIFO) PRA www.tugraz.at

First-in First-Out

• Queue/List of all pages (e.g. std::queue)

• Load a page: push back

• Page to replace: pop front

• Very simple algorithm

• Rarely used in practice

• Performance can even be worse than Random PRA(!)

+ FIFO anomaly / Belady’s anomaly: increasing memory size can reduce performance

38 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 262: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

First-In First-Out (FIFO) PRA www.tugraz.at

First-in First-Out

• Queue/List of all pages (e.g. std::queue)

• Load a page: push back

• Page to replace: pop front

• Very simple algorithm

• Rarely used in practice

• Performance can even be worse than Random PRA(!)

+ FIFO anomaly / Belady’s anomaly: increasing memory size can reduce performance

38 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 263: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

First-In First-Out (FIFO) PRA www.tugraz.at

First-in First-Out

• Queue/List of all pages (e.g. std::queue)

• Load a page: push back

• Page to replace: pop front

• Very simple algorithm

• Rarely used in practice

• Performance can even be worse than Random PRA(!)

+ FIFO anomaly / Belady’s anomaly: increasing memory size can reduce performance

38 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 264: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

First-In First-Out (FIFO) PRA www.tugraz.at

First-in First-Out

• Queue/List of all pages (e.g. std::queue)

• Load a page: push back

• Page to replace: pop front

• Very simple algorithm

• Rarely used in practice

• Performance can even be worse than Random PRA(!)

+ FIFO anomaly / Belady’s anomaly: increasing memory size can reduce performance

38 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 265: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

First-In First-Out (FIFO) PRA www.tugraz.at

First-in First-Out

• Queue/List of all pages (e.g. std::queue)

• Load a page: push back

• Page to replace: pop front

• Very simple algorithm

• Rarely used in practice

• Performance can even be worse than Random PRA(!)

+ FIFO anomaly / Belady’s anomaly: increasing memory size can reduce performance

38 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 266: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

First-In First-Out (FIFO) PRA www.tugraz.at

First-in First-Out

• Queue/List of all pages (e.g. std::queue)

• Load a page: push back

• Page to replace: pop front

• Very simple algorithm

• Rarely used in practice

• Performance can even be worse than Random PRA(!)

+ FIFO anomaly / Belady’s anomaly: increasing memory size can reduce performance

38 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 267: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 268: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 55 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 269: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 22 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 270: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 00 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 271: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 77 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 272: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 66 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 273: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 77 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 274: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 33 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 275: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 11 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 276: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 77 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 277: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 66 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 278: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 22 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 279: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 77 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 280: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 00 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

7H

1B

2C

0A

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 281: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 55 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

7H

1B

2C

0A

5F

7H

2C

0A

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 282: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 44 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

7H

1B

2C

0A

5F

7H

2C

0A

4E

5F

7H

0A

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 283: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 33

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

7H

1B

2C

0A

5F

7H

2C

0A

4E

5F

7H

0A

3D

4E

5F

0A

3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 284: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

FIFO PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

7H

1B

2C

0A

5F

7H

2C

0A

4E

5F

7H

0A

3D

4E

5F

0A

3 hits, 13 misses3 hits, 13 misses

39 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 285: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA www.tugraz.at

• Idea: Make FIFO great again!

• We could call it FI(ANR)FO: “First-in-and-not-referenced first-out”

• Check “referenced”-bit:

• R = 0? evict

• R = 1? set R = 0 and go to next page

• Performance may degenerate to FIFO PRA (→ which may be worse than Random PRA)

40 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 286: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA www.tugraz.at

• Idea: Make FIFO great again!

• We could call it FI(ANR)FO: “First-in-and-not-referenced first-out”

• Check “referenced”-bit:

• R = 0? evict

• R = 1? set R = 0 and go to next page

• Performance may degenerate to FIFO PRA (→ which may be worse than Random PRA)

40 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 287: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA www.tugraz.at

• Idea: Make FIFO great again!

• We could call it FI(ANR)FO: “First-in-and-not-referenced first-out”

• Check “referenced”-bit:

• R = 0? evict

• R = 1? set R = 0 and go to next page

• Performance may degenerate to FIFO PRA (→ which may be worse than Random PRA)

40 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 288: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA www.tugraz.at

• Idea: Make FIFO great again!

• We could call it FI(ANR)FO: “First-in-and-not-referenced first-out”

• Check “referenced”-bit:

• R = 0? evict

• R = 1? set R = 0 and go to next page

• Performance may degenerate to FIFO PRA (→ which may be worse than Random PRA)

40 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Second Chance PRA www.tugraz.at

• Idea: Make FIFO great again!

• We could call it FI(ANR)FO: “First-in-and-not-referenced first-out”

• Check “referenced”-bit:

• R = 0? evict

• R = 1? set R = 0 and go to next page

• Performance may degenerate to FIFO PRA (→ which may be worse than Random PRA)

40 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 290: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA www.tugraz.at

• Idea: Make FIFO great again!

• We could call it FI(ANR)FO: “First-in-and-not-referenced first-out”

• Check “referenced”-bit:

• R = 0? evict

• R = 1? set R = 0 and go to next page

• Performance may degenerate to FIFO PRA (→ which may be worse than Random PRA)

40 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Clock PRA www.tugraz.at

• Virtually identical to Second Chance!

• Only difference is the data structure

• Second Chance: List + List Operations (push back, pop front)

• Clock: Linked List + Pointer

• Performance may degenerate to FIFO PRA (→ which may be worse than Random PRA)

41 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 292: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Clock PRA www.tugraz.at

• Virtually identical to Second Chance!

• Only difference is the data structure

• Second Chance: List + List Operations (push back, pop front)

• Clock: Linked List + Pointer

• Performance may degenerate to FIFO PRA (→ which may be worse than Random PRA)

41 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 293: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Clock PRA www.tugraz.at

• Virtually identical to Second Chance!

• Only difference is the data structure

• Second Chance: List + List Operations (push back, pop front)

• Clock: Linked List + Pointer

• Performance may degenerate to FIFO PRA (→ which may be worse than Random PRA)

41 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 294: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Clock PRA www.tugraz.at

• Virtually identical to Second Chance!

• Only difference is the data structure

• Second Chance: List + List Operations (push back, pop front)

• Clock: Linked List + Pointer

• Performance may degenerate to FIFO PRA (→ which may be worse than Random PRA)

41 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 295: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Clock PRA www.tugraz.at

• Virtually identical to Second Chance!

• Only difference is the data structure

• Second Chance: List + List Operations (push back, pop front)

• Clock: Linked List + Pointer

• Performance may degenerate to FIFO PRA (→ which may be worse than Random PRA)

41 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Clock PRA www.tugraz.at

42 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

0

0

0

0

?

?

?

?

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 55 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

1

0

0

0

?

?

?

?

5F

?

?

?

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 22 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

1

1

0

0

?

?

?

?

5F

?

?

?

5F

2C

?

?

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 300: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 00 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

1

1

1

0

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 301: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 77 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

1

1

1

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 302: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

0

1

1

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 303: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

0

0

1

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 304: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

0

0

0

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 305: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

0

0

0

0

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 306: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 66 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

1

0

0

0

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 307: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA / Clock PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 77 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

1

0

0

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 33 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

1

1

0

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 11 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

1

1

1

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Second Chance PRA / Clock PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 77 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

1

1

1

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Second Chance PRA / Clock PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 66 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

1

1

1

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

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M

Time

Ref

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ced

?

1

1

1

0

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

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M

Time

Ref

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ced

?

0

1

1

0

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

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ced

?

0

0

1

0

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

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M

Time

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ced

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0

0

0

0

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 22 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

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ced

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0

0

0

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 77 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

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M

Time

Ref

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ced

?

1

0

0

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 00 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

1

1

0

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

7H

1B

2C

0A

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 55 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

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M

Time

Ref

eren

ced

?

1

1

1

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

7H

1B

2C

0A

5F

7H

2C

0A

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 320: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

1

1

1

0

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

7H

1B

2C

0A

5F

7H

2C

0A

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 321: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

0

1

1

0

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

7H

1B

2C

0A

5F

7H

2C

0A

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 322: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

0

0

1

0

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

7H

1B

2C

0A

5F

7H

2C

0A

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 323: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

0

0

0

0

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

7H

1B

2C

0A

5F

7H

2C

0A

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 324: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 44 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

0

0

0

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

7H

1B

2C

0A

5F

7H

2C

0A

4E

5F

7H

0A

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 33

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

1

0

0

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

7H

1B

2C

0A

5F

7H

2C

0A

4E

5F

7H

0A

3D

4E

5F

0A

3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 326: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Second Chance PRA / Clock PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ref

eren

ced

?

1

0

0

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

2C

7H

3D

1B

2C

7H

1B

2C

0A

5F

7H

2C

0A

4E

5F

7H

0A

3D

4E

5F

0A

3 hits, 13 misses3 hits, 13 misses

43 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 327: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Least Recently Used (LRU) www.tugraz.at

• Principle of Locality: Pages that were recently accessed will more likely be accessed again

• Idea: Evict the page that was least recently accessed (used)

• How do we find this page?

44 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 328: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Least Recently Used (LRU) www.tugraz.at

• Principle of Locality: Pages that were recently accessed will more likely be accessed again

• Idea: Evict the page that was least recently accessed (used)

• How do we find this page?

44 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 329: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Least Recently Used (LRU) www.tugraz.at

• Principle of Locality: Pages that were recently accessed will more likely be accessed again

• Idea: Evict the page that was least recently accessed (used)

• How do we find this page?

44 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 330: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Least Recently Used (LRU) www.tugraz.at

• LRU data structure:

• (Linked) list of all pages

• Upon access: Move page to end of list

• Page to evict? pop front

• Can this be done in software?

• Only with extreme performance penalty (enforce every memory access to cause a page fault)

• Can this be done in hardware?

• Reordering large data structures of variable size in hardware is difficult

45 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 331: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Least Recently Used (LRU) www.tugraz.at

• LRU data structure:

• (Linked) list of all pages

• Upon access: Move page to end of list

• Page to evict? pop front

• Can this be done in software?

• Only with extreme performance penalty (enforce every memory access to cause a page fault)

• Can this be done in hardware?

• Reordering large data structures of variable size in hardware is difficult

45 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 332: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Least Recently Used (LRU) www.tugraz.at

• LRU data structure:

• (Linked) list of all pages

• Upon access: Move page to end of list

• Page to evict? pop front

• Can this be done in software?

• Only with extreme performance penalty (enforce every memory access to cause a page fault)

• Can this be done in hardware?

• Reordering large data structures of variable size in hardware is difficult

45 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 333: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Least Recently Used (LRU) www.tugraz.at

• LRU data structure:

• (Linked) list of all pages

• Upon access: Move page to end of list

• Page to evict? pop front

• Can this be done in software?

• Only with extreme performance penalty (enforce every memory access to cause a page fault)

• Can this be done in hardware?

• Reordering large data structures of variable size in hardware is difficult

45 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 334: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Least Recently Used (LRU) www.tugraz.at

• LRU data structure:

• (Linked) list of all pages

• Upon access: Move page to end of list

• Page to evict? pop front

• Can this be done in software?

• Only with extreme performance penalty (enforce every memory access to cause a page fault)

• Can this be done in hardware?

• Reordering large data structures of variable size in hardware is difficult

45 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 335: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Least Recently Used (LRU) www.tugraz.at

• LRU data structure:

• (Linked) list of all pages

• Upon access: Move page to end of list

• Page to evict? pop front

• Can this be done in software?

• Only with extreme performance penalty (enforce every memory access to cause a page fault)

• Can this be done in hardware?

• Reordering large data structures of variable size in hardware is difficult

45 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 336: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Least Recently Used (LRU) www.tugraz.at

• LRU data structure:

• (Linked) list of all pages

• Upon access: Move page to end of list

• Page to evict? pop front

• Can this be done in software?

• Only with extreme performance penalty (enforce every memory access to cause a page fault)

• Can this be done in hardware?

• Reordering large data structures of variable size in hardware is difficult

45 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 337: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Least Recently Used (LRU) www.tugraz.at

• LRU data structure:

• (Linked) list of all pages

• Upon access: Move page to end of list

• Page to evict? pop front

• Can this be done in software?

• Only with extreme performance penalty (enforce every memory access to cause a page fault)

• Can this be done in hardware?

• Reordering large data structures of variable size in hardware is difficult

45 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 338: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Global data structure for physical page “ages”

• Related: Where do you store the reference count for CoW-pages?

• Upon access to a page: Store current value of rdtsc (cycle counter)

• Page replacement: Search data structure for lowest stored rdtsc value

Can we implement this?

46 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 339: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Global data structure for physical page “ages”

• Related: Where do you store the reference count for CoW-pages?

• Upon access to a page: Store current value of rdtsc (cycle counter)

• Page replacement: Search data structure for lowest stored rdtsc value

Can we implement this?

46 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 340: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Global data structure for physical page “ages”

• Related: Where do you store the reference count for CoW-pages?

• Upon access to a page: Store current value of rdtsc (cycle counter)

• Page replacement: Search data structure for lowest stored rdtsc value

Can we implement this?

46 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 341: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Global data structure for physical page “ages”

• Related: Where do you store the reference count for CoW-pages?

• Upon access to a page: Store current value of rdtsc (cycle counter)

• Page replacement: Search data structure for lowest stored rdtsc value

Can we implement this?

46 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 342: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Global data structure for physical page “ages”

• Related: Where do you store the reference count for CoW-pages?

• Upon access to a page: Store current value of rdtsc (cycle counter)

• Page replacement: Search data structure for lowest stored rdtsc value

Can we implement this?

46 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 343: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Global data structure for physical page “ages”

• Related: Where do you store the reference count for CoW-pages?

• Upon access to a page: Store current value of rdtsc (cycle counter)

• Page replacement: Search data structure for lowest stored rdtsc value

Can we implement this?

46 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 344: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Store rdtsc value as age in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= LRU PRA (which is actually pseudo-LRU)

Performance? You have 8 MB RAM and loop over a 8.1 MB array → very bad performance

47 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 345: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Store rdtsc value as age in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= LRU PRA (which is actually pseudo-LRU)

Performance? You have 8 MB RAM and loop over a 8.1 MB array → very bad performance

47 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 346: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Store rdtsc value as age in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= LRU PRA (which is actually pseudo-LRU)

Performance? You have 8 MB RAM and loop over a 8.1 MB array → very bad performance

47 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 347: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Store rdtsc value as age in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= LRU PRA (which is actually pseudo-LRU)

Performance? You have 8 MB RAM and loop over a 8.1 MB array → very bad performance

47 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 348: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Store rdtsc value as age in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= LRU PRA (which is actually pseudo-LRU)

Performance? You have 8 MB RAM and loop over a 8.1 MB array → very bad performance

47 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 349: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Store rdtsc value as age in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= LRU PRA (which is actually pseudo-LRU)

Performance? You have 8 MB RAM and loop over a 8.1 MB array → very bad performance

47 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 350: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Store rdtsc value as age in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= LRU PRA (which is actually pseudo-LRU)

Performance? You have 8 MB RAM and loop over a 8.1 MB array → very bad performance

47 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 351: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Store rdtsc value as age in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= LRU PRA (which is actually pseudo-LRU)

Performance? You have 8 MB RAM and loop over a 8.1 MB array → very bad performance

47 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 352: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Store rdtsc value as age in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= LRU PRA (which is actually pseudo-LRU)

Performance?

You have 8 MB RAM and loop over a 8.1 MB array → very bad performance

47 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 353: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pseudo-LRU www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Store rdtsc value as age in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= LRU PRA (which is actually pseudo-LRU)

Performance? You have 8 MB RAM and loop over a 8.1 MB array → very bad performance

47 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 354: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

?

?

?

?

?

?

?

?

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 355: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 55 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

1

?

?

?

?

?

?

?

5F

?

?

?

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 356: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 22 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

1

2

?

?

?

?

?

?

5F

?

?

?

5F

2C

?

?

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 357: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 00 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

1

2

3

?

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 358: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 77 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

1

2

3

4

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 359: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 66 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

5

2

3

4

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 360: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 77 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

5

2

3

6

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 361: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 33 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

5

7

3

6

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 362: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 11 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

5

7

8

6

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 363: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 77 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

5

7

8

9

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 364: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 66 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

10

7

8

9

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 365: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 22 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

10

11

8

9

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

2C

1B

7H

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 366: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 77 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

10

11

8

12

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 367: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 00 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

10

11

13

12

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

0A

7H

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 368: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 55 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

14

11

13

12

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

0A

7H

5F

2C

0A

7H

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 369: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 44 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

14

15

13

12

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

0A

7H

5F

2C

0A

7H

4E

5F

0A

7H

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 370: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 33

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

14

15

13

16

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

0A

7H

5F

2C

0A

7H

4E

5F

0A

7H

3D

5F

4E

0A

4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 371: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

LRU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Las

tU

sed

14

15

13

16

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

6G

3D

0A

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

3D

1B

7H

6G

2C

1B

7H

6G

2C

1B

7H

6G

2C

0A

7H

5F

2C

0A

7H

4E

5F

0A

7H

3D

5F

4E

0A

4 hits, 12 misses4 hits, 12 misses

48 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 372: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Not Frequently Used (NFU) www.tugraz.at

• Again: Principle of Locality

• Idea: Record frequency of accesses and evict page with lowest access frequency

• Approximate frequency by access count

• How do we obtain the access count?

49 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 373: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Not Frequently Used (NFU) www.tugraz.at

• Again: Principle of Locality

• Idea: Record frequency of accesses and evict page with lowest access frequency

• Approximate frequency by access count

• How do we obtain the access count?

49 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 374: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Not Frequently Used (NFU) www.tugraz.at

• Again: Principle of Locality

• Idea: Record frequency of accesses and evict page with lowest access frequency

• Approximate frequency by access count

• How do we obtain the access count?

49 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 375: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Not Frequently Used (NFU) www.tugraz.at

• Again: Principle of Locality

• Idea: Record frequency of accesses and evict page with lowest access frequency

• Approximate frequency by access count

• How do we obtain the access count?

49 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 376: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Not Frequently Used (NFU) www.tugraz.at

• Global data structure for physical page access frequency

• Upon access to a page: Increment access counter

• Page replacement: Search for lowest counter value

Can we implement this?

50 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 377: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Not Frequently Used (NFU) www.tugraz.at

• Global data structure for physical page access frequency

• Upon access to a page: Increment access counter

• Page replacement: Search for lowest counter value

Can we implement this?

50 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 378: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Not Frequently Used (NFU) www.tugraz.at

• Global data structure for physical page access frequency

• Upon access to a page: Increment access counter

• Page replacement: Search for lowest counter value

Can we implement this?

50 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 379: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Not Frequently Used (NFU) www.tugraz.at

• Global data structure for physical page access frequency

• Upon access to a page: Increment access counter

• Page replacement: Search for lowest counter value

Can we implement this?

50 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 380: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Not Frequently Used (NFU) www.tugraz.at

• Global data structure for physical page access frequency

• Upon access to a page: Increment access counter

• Page replacement: Search for lowest counter value

Can we implement this?

50 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 381: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Increment access counter in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= NFU PRA

• Performance?

Boot code very unlikely to be swapped (because it was used a lot during

boot up)

51 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 382: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Increment access counter in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= NFU PRA

• Performance?

Boot code very unlikely to be swapped (because it was used a lot during

boot up)

51 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 383: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Increment access counter in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= NFU PRA

• Performance?

Boot code very unlikely to be swapped (because it was used a lot during

boot up)

51 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 384: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Increment access counter in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= NFU PRA

• Performance?

Boot code very unlikely to be swapped (because it was used a lot during

boot up)

51 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 385: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Increment access counter in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= NFU PRA

• Performance?

Boot code very unlikely to be swapped (because it was used a lot during

boot up)

51 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 386: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Increment access counter in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= NFU PRA

• Performance?

Boot code very unlikely to be swapped (because it was used a lot during

boot up)

51 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 387: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Increment access counter in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= NFU PRA

• Performance?

Boot code very unlikely to be swapped (because it was used a lot during

boot up)

51 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 388: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Increment access counter in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= NFU PRA

• Performance?

Boot code very unlikely to be swapped (because it was used a lot during

boot up)

51 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 389: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Increment access counter in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= NFU PRA

• Performance?

Boot code very unlikely to be swapped (because it was used a lot during

boot up)

51 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 390: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

• Same trick as before:

• Poll page tables: read and reset referenced bits

• Increment access counter in the global data structure

• When do we do this?

• A thread continuously running and checking

• Upon de-scheduling

= NFU PRA

• Performance? Boot code very unlikely to be swapped (because it was used a lot during

boot up)

51 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 391: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

?

?

?

?

?

?

?

?

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 392: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 55 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

?

?

?

?

?

?

?

5F

?

?

?

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 393: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 22 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

1

?

?

?

?

?

?

5F

?

?

?

5F

2C

?

?

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 394: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 00 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

1

1

?

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 395: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 77 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

1

1

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 396: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 66 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

1

1

1

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 397: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 77 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

1

1

2

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 398: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 33 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

1

1

2

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 399: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 11 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

1

1

2

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

1B

6G

0A

7H

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 400: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 77 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

1

1

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 401: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 66 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

2

1

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 402: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 22 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

2

1

3

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

2C

6G

0A

7H

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 403: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 77 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

2

1

4

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

2C

6G

0A

7H

2C

6G

0A

7H

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 404: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 00 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

2

2

4

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

2C

6G

0A

7H

2C

6G

0A

7H

2C

6G

0A

7H

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 405: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 55 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

2

2

4

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

2C

6G

0A

7H

2C

6G

0A

7H

2C

6G

0A

7H

5F

6G

0A

7H

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 406: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 44 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

2

2

4

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

2C

6G

0A

7H

2C

6G

0A

7H

2C

6G

0A

7H

5F

6G

0A

7H

4E

6G

0A

7H

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 407: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 33

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

2

2

4

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

2C

6G

0A

7H

2C

6G

0A

7H

2C

6G

0A

7H

5F

6G

0A

7H

4E

6G

0A

7H

3D

6G

0A

7H

5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 408: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

NFU PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Acc

ess

Cou

nte

r

1

2

2

4

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

1B

6G

0A

7H

2C

6G

0A

7H

2C

6G

0A

7H

2C

6G

0A

7H

5F

6G

0A

7H

4E

6G

0A

7H

3D

6G

0A

7H

5 hits, 11 misses5 hits, 11 misses

52 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 409: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• NFU has problems because it never forgets (cf. human brain)

• Idea: Make NFU’s memories slowly fade away

→ Let access information age over time

• How do we observe an access to a page?

53 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 410: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• NFU has problems because it never forgets (cf. human brain)

• Idea: Make NFU’s memories slowly fade away

→ Let access information age over time

• How do we observe an access to a page?

53 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 411: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• NFU has problems because it never forgets (cf. human brain)

• Idea: Make NFU’s memories slowly fade away

→ Let access information age over time

• How do we observe an access to a page?

53 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 412: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• NFU has problems because it never forgets (cf. human brain)

• Idea: Make NFU’s memories slowly fade away

→ Let access information age over time

• How do we observe an access to a page?

53 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 413: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Global data structure for age

• Upon access to a page: Set most-significant bit to 1 (e.g. 1000)

• In a constant frequency: Age all pages by shifting value in global data structure to the

right (e.g. 1000 → 0100)

• Page replacement: Search for lowest numerical value (=highest age)

Can we implement this?

54 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 414: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Global data structure for age

• Upon access to a page: Set most-significant bit to 1 (e.g. 1000)

• In a constant frequency: Age all pages by shifting value in global data structure to the

right (e.g. 1000 → 0100)

• Page replacement: Search for lowest numerical value (=highest age)

Can we implement this?

54 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 415: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Global data structure for age

• Upon access to a page: Set most-significant bit to 1 (e.g. 1000)

• In a constant frequency: Age all pages by shifting value in global data structure to the

right (e.g. 1000 → 0100)

• Page replacement: Search for lowest numerical value (=highest age)

Can we implement this?

54 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 416: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Global data structure for age

• Upon access to a page: Set most-significant bit to 1 (e.g. 1000)

• In a constant frequency: Age all pages by shifting value in global data structure to the

right (e.g. 1000 → 0100)

• Page replacement: Search for lowest numerical value (=highest age)

Can we implement this?

54 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 417: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Global data structure for age

• Upon access to a page: Set most-significant bit to 1 (e.g. 1000)

• In a constant frequency: Age all pages by shifting value in global data structure to the

right (e.g. 1000 → 0100)

• Page replacement: Search for lowest numerical value (=highest age)

Can we implement this?

54 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 418: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Global data structure for age

• Upon access to a page: Set most-significant bit to 1 (e.g. 1000)

• In a constant frequency: Age all pages by shifting value in global data structure to the

right (e.g. 1000 → 0100)

• Page replacement: Search for lowest numerical value (=highest age)

Can we implement this?

54 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 419: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Same tricks as before:

• Poll page tables: read and reset referenced bits

• Set most-significant bit in the global data structure

• When do we do this?

• Before aging (shifting)

• Upon de-scheduling

• When do we age (shift) the values?

• Set up a dedicated periodic interrupt

• Upon every n-th timer interrupt

= Aging PRA

• Performance?

One of the most widely used PRAs in practice

55 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 420: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Same tricks as before:

• Poll page tables: read and reset referenced bits

• Set most-significant bit in the global data structure

• When do we do this?

• Before aging (shifting)

• Upon de-scheduling

• When do we age (shift) the values?

• Set up a dedicated periodic interrupt

• Upon every n-th timer interrupt

= Aging PRA

• Performance?

One of the most widely used PRAs in practice

55 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 421: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Same tricks as before:

• Poll page tables: read and reset referenced bits

• Set most-significant bit in the global data structure

• When do we do this?

• Before aging (shifting)

• Upon de-scheduling

• When do we age (shift) the values?

• Set up a dedicated periodic interrupt

• Upon every n-th timer interrupt

= Aging PRA

• Performance?

One of the most widely used PRAs in practice

55 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 422: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Same tricks as before:

• Poll page tables: read and reset referenced bits

• Set most-significant bit in the global data structure

• When do we do this?

• Before aging (shifting)

• Upon de-scheduling

• When do we age (shift) the values?

• Set up a dedicated periodic interrupt

• Upon every n-th timer interrupt

= Aging PRA

• Performance?

One of the most widely used PRAs in practice

55 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 423: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Same tricks as before:

• Poll page tables: read and reset referenced bits

• Set most-significant bit in the global data structure

• When do we do this?

• Before aging (shifting)

• Upon de-scheduling

• When do we age (shift) the values?

• Set up a dedicated periodic interrupt

• Upon every n-th timer interrupt

= Aging PRA

• Performance?

One of the most widely used PRAs in practice

55 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 424: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Same tricks as before:

• Poll page tables: read and reset referenced bits

• Set most-significant bit in the global data structure

• When do we do this?

• Before aging (shifting)

• Upon de-scheduling

• When do we age (shift) the values?

• Set up a dedicated periodic interrupt

• Upon every n-th timer interrupt

= Aging PRA

• Performance?

One of the most widely used PRAs in practice

55 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 425: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Same tricks as before:

• Poll page tables: read and reset referenced bits

• Set most-significant bit in the global data structure

• When do we do this?

• Before aging (shifting)

• Upon de-scheduling

• When do we age (shift) the values?

• Set up a dedicated periodic interrupt

• Upon every n-th timer interrupt

= Aging PRA

• Performance?

One of the most widely used PRAs in practice

55 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 426: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Same tricks as before:

• Poll page tables: read and reset referenced bits

• Set most-significant bit in the global data structure

• When do we do this?

• Before aging (shifting)

• Upon de-scheduling

• When do we age (shift) the values?

• Set up a dedicated periodic interrupt

• Upon every n-th timer interrupt

= Aging PRA

• Performance?

One of the most widely used PRAs in practice

55 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 427: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Same tricks as before:

• Poll page tables: read and reset referenced bits

• Set most-significant bit in the global data structure

• When do we do this?

• Before aging (shifting)

• Upon de-scheduling

• When do we age (shift) the values?

• Set up a dedicated periodic interrupt

• Upon every n-th timer interrupt

= Aging PRA

• Performance?

One of the most widely used PRAs in practice

55 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 428: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Same tricks as before:

• Poll page tables: read and reset referenced bits

• Set most-significant bit in the global data structure

• When do we do this?

• Before aging (shifting)

• Upon de-scheduling

• When do we age (shift) the values?

• Set up a dedicated periodic interrupt

• Upon every n-th timer interrupt

= Aging PRA

• Performance?

One of the most widely used PRAs in practice

55 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 429: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Same tricks as before:

• Poll page tables: read and reset referenced bits

• Set most-significant bit in the global data structure

• When do we do this?

• Before aging (shifting)

• Upon de-scheduling

• When do we age (shift) the values?

• Set up a dedicated periodic interrupt

• Upon every n-th timer interrupt

= Aging PRA

• Performance?

One of the most widely used PRAs in practice

55 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 430: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Same tricks as before:

• Poll page tables: read and reset referenced bits

• Set most-significant bit in the global data structure

• When do we do this?

• Before aging (shifting)

• Upon de-scheduling

• When do we age (shift) the values?

• Set up a dedicated periodic interrupt

• Upon every n-th timer interrupt

= Aging PRA

• Performance?

One of the most widely used PRAs in practice

55 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 431: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging www.tugraz.at

• Same tricks as before:

• Poll page tables: read and reset referenced bits

• Set most-significant bit in the global data structure

• When do we do this?

• Before aging (shifting)

• Upon de-scheduling

• When do we age (shift) the values?

• Set up a dedicated periodic interrupt

• Upon every n-th timer interrupt

= Aging PRA

• Performance? One of the most widely used PRAs in practice

55 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 432: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

000000

000000

000000

000000

?

?

?

?

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 433: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 55 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

100000

000000

000000

000000

?

?

?

?

5F

?

?

?

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 434: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 22 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

100000

100000

000000

000000

?

?

?

?

5F

?

?

?

5F

2C

?

?

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 435: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 00 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

010000

010000

100000

000000

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 436: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 77 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

010000

010000

100000

100000

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 437: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 66 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

001000

100000

010000

010000

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 438: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 77 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

001000

100000

010000

110000

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 439: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 33 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

100000

010000

001000

011000

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 440: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 11 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

100000

010000

100000

011000

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

3D

6G

1B

7H

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 441: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 77 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

010000

001000

010000

101100

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

3D

6G

1B

7H

3D

6G

1B

7H

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 442: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Aging PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 66 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

010000

101000

010000

101100

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

3D

6G

1B

7H

3D

6G

1B

7H

3D

6G

1B

7H

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Aging PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 22 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

100000

010100

001000

010110

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

3D

6G

1B

7H

3D

6G

1B

7H

3D

6G

1B

7H

2C

6G

1B

7H

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Aging PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 77 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

100000

010100

001000

110110

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

3D

6G

1B

7H

3D

6G

1B

7H

3D

6G

1B

7H

2C

6G

1B

7H

2C

6G

1B

7H

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Aging PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 00 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

010000

001010

100000

011011

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

3D

6G

1B

7H

3D

6G

1B

7H

3D

6G

1B

7H

2C

6G

1B

7H

2C

6G

1B

7H

2C

6G

0A

7H

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Aging PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 55 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

010000

100000

100000

011011

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

3D

6G

1B

7H

3D

6G

1B

7H

3D

6G

1B

7H

2C

6G

1B

7H

2C

6G

1B

7H

2C

6G

0A

7H

2C

5F

0A

7H

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Aging PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 44 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

100000

010000

010000

001101

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

3D

6G

1B

7H

3D

6G

1B

7H

3D

6G

1B

7H

2C

6G

1B

7H

2C

6G

1B

7H

2C

6G

0A

7H

2C

5F

0A

7H

4E

5F

0A

7H

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Aging PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 33

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

100000

010000

010000

100000

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

3D

6G

1B

7H

3D

6G

1B

7H

3D

6G

1B

7H

2C

6G

1B

7H

2C

6G

1B

7H

2C

6G

0A

7H

2C

5F

0A

7H

4E

5F

0A

7H

4E

3D

5F

0A

4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Aging PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Ages

100000

010000

010000

100000

?

?

?

?

5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

5F

6G

0A

7H

5F

6G

0A

7H

3D

6G

0A

7H

3D

6G

1B

7H

3D

6G

1B

7H

3D

6G

1B

7H

2C

6G

1B

7H

2C

6G

1B

7H

2C

6G

0A

7H

2C

5F

0A

7H

4E

5F

0A

7H

4E

3D

5F

0A

4 hits, 12 misses4 hits, 12 misses

56 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Limitations of Aging PRA www.tugraz.at

• No age difference between pages in same aging cycle

• Limited number of bits:

• if counter = 0, no difference if unused since 10 or 100 ticks

→ more bits is better (but also uses more space)

57 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Limitations of Aging PRA www.tugraz.at

• No age difference between pages in same aging cycle

• Limited number of bits:

• if counter = 0, no difference if unused since 10 or 100 ticks

→ more bits is better (but also uses more space)

57 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Limitations of Aging PRA www.tugraz.at

• No age difference between pages in same aging cycle

• Limited number of bits:

• if counter = 0, no difference if unused since 10 or 100 ticks

→ more bits is better (but also uses more space)

57 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Limitations of Aging PRA www.tugraz.at

• No age difference between pages in same aging cycle

• Limited number of bits:

• if counter = 0, no difference if unused since 10 or 100 ticks

→ more bits is better (but also uses more space)

57 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 454: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Process-aware PRAs www.tugraz.at

• So far we completely ignored processes...

• Can we measure how fair PRAs are (wrt. processes)?

• Process performance? Difficult to compare...

• Same amount of memory for every process? Tiny shell vs. 3D game

→ Same page faults per second (= page fault frequency)!

• How do we make every process have the same number of page faults per second?

58 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Process-aware PRAs www.tugraz.at

• So far we completely ignored processes...

• Can we measure how fair PRAs are (wrt. processes)?

• Process performance? Difficult to compare...

• Same amount of memory for every process? Tiny shell vs. 3D game

→ Same page faults per second (= page fault frequency)!

• How do we make every process have the same number of page faults per second?

58 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Process-aware PRAs www.tugraz.at

• So far we completely ignored processes...

• Can we measure how fair PRAs are (wrt. processes)?

• Process performance? Difficult to compare...

• Same amount of memory for every process? Tiny shell vs. 3D game

→ Same page faults per second (= page fault frequency)!

• How do we make every process have the same number of page faults per second?

58 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 457: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Process-aware PRAs www.tugraz.at

• So far we completely ignored processes...

• Can we measure how fair PRAs are (wrt. processes)?

• Process performance? Difficult to compare...

• Same amount of memory for every process? Tiny shell vs. 3D game

→ Same page faults per second (= page fault frequency)!

• How do we make every process have the same number of page faults per second?

58 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 458: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Process-aware PRAs www.tugraz.at

• So far we completely ignored processes...

• Can we measure how fair PRAs are (wrt. processes)?

• Process performance? Difficult to compare...

• Same amount of memory for every process? Tiny shell vs. 3D game

→ Same page faults per second (= page fault frequency)!

• How do we make every process have the same number of page faults per second?

58 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 459: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Process-aware PRAs www.tugraz.at

• So far we completely ignored processes...

• Can we measure how fair PRAs are (wrt. processes)?

• Process performance? Difficult to compare...

• Same amount of memory for every process? Tiny shell vs. 3D game

→ Same page faults per second (= page fault frequency)!

• How do we make every process have the same number of page faults per second?

58 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 460: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Thrashing www.tugraz.at

• Thrashing: system deals more with page faults and swapping than with work

• Processes need more RAM than exists : always too many page faults

• Page fault frequency too high?

→ not enough RAM

→ Swap out entire processes until page fault frequency decreases

→ Only schedule processes where all required pages are in RAM

59 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Thrashing www.tugraz.at

• Thrashing: system deals more with page faults and swapping than with work

• Processes need more RAM than exists : always too many page faults

• Page fault frequency too high?

→ not enough RAM

→ Swap out entire processes until page fault frequency decreases

→ Only schedule processes where all required pages are in RAM

59 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 462: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Thrashing www.tugraz.at

• Thrashing: system deals more with page faults and swapping than with work

• Processes need more RAM than exists : always too many page faults

• Page fault frequency too high?

→ not enough RAM

→ Swap out entire processes until page fault frequency decreases

→ Only schedule processes where all required pages are in RAM

59 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 463: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Thrashing www.tugraz.at

• Thrashing: system deals more with page faults and swapping than with work

• Processes need more RAM than exists : always too many page faults

• Page fault frequency too high?

→ not enough RAM

→ Swap out entire processes until page fault frequency decreases

→ Only schedule processes where all required pages are in RAM

59 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 464: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Thrashing www.tugraz.at

• Thrashing: system deals more with page faults and swapping than with work

• Processes need more RAM than exists : always too many page faults

• Page fault frequency too high? → not enough RAM

→ Swap out entire processes until page fault frequency decreases

→ Only schedule processes where all required pages are in RAM

59 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 465: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Thrashing www.tugraz.at

• Thrashing: system deals more with page faults and swapping than with work

• Processes need more RAM than exists : always too many page faults

• Page fault frequency too high? → not enough RAM

→ Swap out entire processes until page fault frequency decreases

→ Only schedule processes where all required pages are in RAM

59 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 466: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Thrashing www.tugraz.at

• Thrashing: system deals more with page faults and swapping than with work

• Processes need more RAM than exists : always too many page faults

• Page fault frequency too high? → not enough RAM

→ Swap out entire processes until page fault frequency decreases

→ Only schedule processes where all required pages are in RAM

59 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 467: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Working Set www.tugraz.at

Peter Denning, 1968, abbreviated:

We define the working set W (t, τ) of a process at time t to be the collection of information

referenced by the process during the process time interval (t − τ, t).

• τ = the working set parameter

• ω(t, τ) = number of pages in W (t, τ)

More ideas:

• Prepaging: preload all pages in the

working set before scheduling

• PRA: only swap pages which are in no

working set

• Adaptive τ !

Behavior of ω(t, τ):

60 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set www.tugraz.at

Peter Denning, 1968, abbreviated:

We define the working set W (t, τ) of a process at time t to be the collection of information

referenced by the process during the process time interval (t − τ, t).

• τ = the working set parameter

• ω(t, τ) = number of pages in W (t, τ)

More ideas:

• Prepaging: preload all pages in the

working set before scheduling

• PRA: only swap pages which are in no

working set

• Adaptive τ !

Behavior of ω(t, τ):

60 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set www.tugraz.at

Peter Denning, 1968, abbreviated:

We define the working set W (t, τ) of a process at time t to be the collection of information

referenced by the process during the process time interval (t − τ, t).

• τ = the working set parameter

• ω(t, τ) = number of pages in W (t, τ)

More ideas:

• Prepaging: preload all pages in the

working set before scheduling

• PRA: only swap pages which are in no

working set

• Adaptive τ !

Behavior of ω(t, τ):

60 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set www.tugraz.at

Peter Denning, 1968, abbreviated:

We define the working set W (t, τ) of a process at time t to be the collection of information

referenced by the process during the process time interval (t − τ, t).

• τ = the working set parameter

• ω(t, τ) = number of pages in W (t, τ)

More ideas:

• Prepaging: preload all pages in the

working set before scheduling

• PRA: only swap pages which are in no

working set

• Adaptive τ !

Behavior of ω(t, τ):

60 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set www.tugraz.at

Peter Denning, 1968, abbreviated:

We define the working set W (t, τ) of a process at time t to be the collection of information

referenced by the process during the process time interval (t − τ, t).

• τ = the working set parameter

• ω(t, τ) = number of pages in W (t, τ)

More ideas:

• Prepaging: preload all pages in the

working set before scheduling

• PRA: only swap pages which are in no

working set

• Adaptive τ !

Behavior of ω(t, τ):

60 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set www.tugraz.at

Peter Denning, 1968, abbreviated:

We define the working set W (t, τ) of a process at time t to be the collection of information

referenced by the process during the process time interval (t − τ, t).

• τ = the working set parameter

• ω(t, τ) = number of pages in W (t, τ)

More ideas:

• Prepaging: preload all pages in the

working set before scheduling

• PRA: only swap pages which are in no

working set

• Adaptive τ !

Behavior of ω(t, τ):

60 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set www.tugraz.at

Peter Denning, 1968, abbreviated:

We define the working set W (t, τ) of a process at time t to be the collection of information

referenced by the process during the process time interval (t − τ, t).

• τ = the working set parameter

• ω(t, τ) = number of pages in W (t, τ)

More ideas:

• Prepaging: preload all pages in the

working set before scheduling

• PRA: only swap pages which are in no

working set

• Adaptive τ !

Behavior of ω(t, τ):

60 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set www.tugraz.at

Peter Denning, 1968, abbreviated:

We define the working set W (t, τ) of a process at time t to be the collection of information

referenced by the process during the process time interval (t − τ, t).

• τ = the working set parameter

• ω(t, τ) = number of pages in W (t, τ)

More ideas:

• Prepaging: preload all pages in the

working set before scheduling

• PRA: only swap pages which are in no

working set

• Adaptive τ !

Behavior of ω(t, τ):

60 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set www.tugraz.at

Peter Denning, 1968, abbreviated:

We define the working set W (t, τ) of a process at time t to be the collection of information

referenced by the process during the process time interval (t − τ, t).

• τ = the working set parameter

• ω(t, τ) = number of pages in W (t, τ)

More ideas:

• Prepaging: preload all pages in the

working set before scheduling

• PRA: only swap pages which are in no

working set

• Adaptive τ !

Behavior of ω(t, τ):

60 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Adaptive Working Set Size www.tugraz.at

Define working set size by

• Time: All pages younger than τ are in the working set. (suggested by Denning)

• Huge Shift Register: shift in page number upon access. (difficult to implement)

• Page Count: The N youngest pages are in the working set.

Page fault frequency too high?

• Globally reduce τ , or the size of the shift register, or N respectively

61 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Adaptive Working Set Size www.tugraz.at

Define working set size by

• Time: All pages younger than τ are in the working set. (suggested by Denning)

• Huge Shift Register: shift in page number upon access. (difficult to implement)

• Page Count: The N youngest pages are in the working set.

Page fault frequency too high?

• Globally reduce τ , or the size of the shift register, or N respectively

61 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Adaptive Working Set Size www.tugraz.at

Define working set size by

• Time: All pages younger than τ are in the working set. (suggested by Denning)

• Huge Shift Register: shift in page number upon access. (difficult to implement)

• Page Count: The N youngest pages are in the working set.

Page fault frequency too high?

• Globally reduce τ , or the size of the shift register, or N respectively

61 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Adaptive Working Set Size www.tugraz.at

Define working set size by

• Time: All pages younger than τ are in the working set. (suggested by Denning)

• Huge Shift Register: shift in page number upon access. (difficult to implement)

• Page Count: The N youngest pages are in the working set.

Page fault frequency too high?

• Globally reduce τ , or the size of the shift register, or N respectively

61 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Adaptive Working Set Size www.tugraz.at

Define working set size by

• Time: All pages younger than τ are in the working set. (suggested by Denning)

• Huge Shift Register: shift in page number upon access. (difficult to implement)

• Page Count: The N youngest pages are in the working set.

Page fault frequency too high?

• Globally reduce τ , or the size of the shift register, or N respectively

61 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 481: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Adaptive Working Set Size www.tugraz.at

Define working set size by

• Time: All pages younger than τ are in the working set. (suggested by Denning)

• Huge Shift Register: shift in page number upon access. (difficult to implement)

• Page Count: The N youngest pages are in the working set.

Page fault frequency too high?

• Globally reduce τ , or the size of the shift register, or N respectively

61 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set Today www.tugraz.at

• Prepaging not common

• Working Set is no PRA ...

• ... but commonly used to form a process-aware PRA

• Same approximations as in other PRAs:

• polling referenced bits

• storing information in a global data structure

62 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set Today www.tugraz.at

• Prepaging not common

• Working Set is no PRA ...

• ... but commonly used to form a process-aware PRA

• Same approximations as in other PRAs:

• polling referenced bits

• storing information in a global data structure

62 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 484: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Working Set Today www.tugraz.at

• Prepaging not common

• Working Set is no PRA ...

• ... but commonly used to form a process-aware PRA

• Same approximations as in other PRAs:

• polling referenced bits

• storing information in a global data structure

62 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 485: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Working Set Today www.tugraz.at

• Prepaging not common

• Working Set is no PRA ...

• ... but commonly used to form a process-aware PRA

• Same approximations as in other PRAs:

• polling referenced bits

• storing information in a global data structure

62 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 486: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Working Set Today www.tugraz.at

• Prepaging not common

• Working Set is no PRA ...

• ... but commonly used to form a process-aware PRA

• Same approximations as in other PRAs:

• polling referenced bits

• storing information in a global data structure

62 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 487: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Working Set Today www.tugraz.at

• Prepaging not common

• Working Set is no PRA ...

• ... but commonly used to form a process-aware PRA

• Same approximations as in other PRAs:

• polling referenced bits

• storing information in a global data structure

62 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 488: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 492: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 495: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 498: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set PRAs – The Essentials (Page Count Variant) www.tugraz.at

Working Set:

• Every process has a working set size N

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: The N youngest pages

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update N upon certain occasions

• Set N = N − 1 for all processes to

reduce memory pressure

• e.g. when trying to swap a page but

none are swappable

• Set N = N + 1 for a process P to adjust

for increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

63 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Working Set PRAs – The Essentials (Time Variant) www.tugraz.at

Working Set:

• Every process has a working set parameter τ

• Every process has M mapped pages

• Each page has a timestamp

• not real time, process time, clock()

• Working Set: All pages younger than τ

Process-aware PRA:

• Any page in no working set (of any process)

is swappable

• Use global PRA on swappable pages

• e.g., Clock → WSClock

Adaptive process-aware PRA:

• Update τ upon certain occasions

• Decrease τ slightly to reduce memory

pressure

• e.g. when trying to swap a page but

none are swappable

• Increase τ slightly to adjust for

increasing memory usage

• e.g. when P experiences a pagefault

→ Page fault frequency will settle to the

same value for every process

64 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Time

RA

M

Time

Working Set

P2

P1

?

?

?

?

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 55 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

5

P1

?

?

?

?5F

?

?

?

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 22 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

2,5

P1

?

?

?

?5F

?

?

?

5F

2C

?

?

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 00 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

0,2,5

P1

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 77 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

0,2,5

P1

7

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

0,2

P1

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 66 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

0,2

P1

6

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 77 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

7,0,2

P1

6

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

7,0

P1

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 33 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

7,0

P1

3

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3D

6G

0A

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 11 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

1,7,0

P1

3

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3D

6G

0A

7H

1B

3D

0A

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

1,7

P1

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3D

6G

0A

7H

1B

3D

0A

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 77 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

7,1

P1

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3D

6G

0A

7H

1B

3D

0A

7H

1B

3D

0A

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 66 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

7,1

P1

6

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3D

6G

0A

7H

1B

3D

0A

7H

1B

3D

0A

7H

1B

6G

0A

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 22 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

7,1

P1

2,6

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3D

6G

0A

7H

1B

3D

0A

7H

1B

3D

0A

7H

1B

6G

0A

7H

1B

6G

2C

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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WSRandom PRA www.tugraz.at

HIT!

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 77 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

7,1

P1

7,2,6

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3D

6G

0A

7H

1B

3D

0A

7H

1B

3D

0A

7H

1B

6G

0A

7H

1B

6G

2C

7H

1B

6G

2C

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

7

P1

7,2

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3D

6G

0A

7H

1B

3D

0A

7H

1B

3D

0A

7H

1B

6G

0A

7H

1B

6G

2C

7H

1B

6G

2C

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 00 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

0,7

P1

7,2

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3D

6G

0A

7H

1B

3D

0A

7H

1B

3D

0A

7H

1B

6G

0A

7H

1B

6G

2C

7H

1B

6G

2C

7H

1B

0A

2C

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 55 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

5,0,7

P1

7,2

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3D

6G

0A

7H

1B

3D

0A

7H

1B

3D

0A

7H

1B

6G

0A

7H

1B

6G

2C

7H

1B

6G

2C

7H

1B

0A

2C

7H

2C

5F

0A

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

5,0

P1

7

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3D

6G

0A

7H

1B

3D

0A

7H

1B

3D

0A

7H

1B

6G

0A

7H

1B

6G

2C

7H

1B

6G

2C

7H

1B

0A

2C

7H

2C

5F

0A

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 44 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

5,0

P1

4,7

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3D

6G

0A

7H

1B

3D

0A

7H

1B

3D

0A

7H

1B

6G

0A

7H

1B

6G

2C

7H

1B

6G

2C

7H

1B

0A

2C

7H

2C

5F

0A

7H

4E

5F

0A

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

5

P1

4

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3D

6G

0A

7H

1B

3D

0A

7H

1B

3D

0A

7H

1B

6G

0A

7H

1B

6G

2C

7H

1B

6G

2C

7H

1B

0A

2C

7H

2C

5F

0A

7H

4E

5F

0A

7H

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 33

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

5

P1

3,4

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3D

6G

0A

7H

1B

3D

0A

7H

1B

3D

0A

7H

1B

6G

0A

7H

1B

6G

2C

7H

1B

6G

2C

7H

1B

0A

2C

7H

2C

5F

0A

7H

4E

5F

0A

7H

4E

5F

0A

3D

P1: 1 hits, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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WSRandom PRA www.tugraz.at

Disk

0 A1 B2 C3 D4 E5 F6 G7 H

Access Stream: 5 2 0 7 6 7 3 1 7 6 2 7 0 5 4 3

Time Step: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Time

RA

M

Time

Working Set

P2

5

P1

3,4

?

?

?

?5F

?

?

?

5F

2C

?

?

5F

2C

0A

?

5F

2C

0A

7H

6G

2C

0A

7H

6G

2C

0A

7H

3D

6G

0A

7H

1B

3D

0A

7H

1B

3D

0A

7H

1B

6G

0A

7H

1B

6G

2C

7H

1B

6G

2C

7H

1B

0A

2C

7H

2C

5F

0A

7H

4E

5F

0A

7H

4E

5F

0A

3D

P1: 1 hits, 7 misses P2: 2 hits, 6 missesP1: 1 hit, 7 misses P2: 2 hits, 6 misses

65 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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PRA Design: Local vs. Global www.tugraz.at

PRA selects page for eviction ...

• local: ... from the same process

• Is the working set size fixed or adaptive?

• global: ... from any process

Working set algorithms are inherently global

Global strategies usually perform better:

• Process needs more pages:

• Thrashing although other processes

might have spare pages

• Process needs fewer pages:

• Memory waste despite possible thrashing

in another processes

66 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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PRA Design: Local vs. Global www.tugraz.at

PRA selects page for eviction ...

• local: ... from the same process

• Is the working set size fixed or adaptive?

• global: ... from any process

Working set algorithms are inherently global

Global strategies usually perform better:

• Process needs more pages:

• Thrashing although other processes

might have spare pages

• Process needs fewer pages:

• Memory waste despite possible thrashing

in another processes

66 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 533: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

PRA Design: Local vs. Global www.tugraz.at

PRA selects page for eviction ...

• local: ... from the same process

• Is the working set size fixed or adaptive?

• global: ... from any process

Working set algorithms are inherently global

Global strategies usually perform better:

• Process needs more pages:

• Thrashing although other processes

might have spare pages

• Process needs fewer pages:

• Memory waste despite possible thrashing

in another processes

66 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 534: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

PRA Design: Local vs. Global www.tugraz.at

PRA selects page for eviction ...

• local: ... from the same process

• Is the working set size fixed or adaptive?

• global: ... from any process

Working set algorithms are inherently global

Global strategies usually perform better:

• Process needs more pages:

• Thrashing although other processes

might have spare pages

• Process needs fewer pages:

• Memory waste despite possible thrashing

in another processes

66 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 535: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

PRA Design: Local vs. Global www.tugraz.at

PRA selects page for eviction ...

• local: ... from the same process

• Is the working set size fixed or adaptive?

• global: ... from any process

Working set algorithms are inherently global

Global strategies usually perform better:

• Process needs more pages:

• Thrashing although other processes

might have spare pages

• Process needs fewer pages:

• Memory waste despite possible thrashing

in another processes

66 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 536: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

PRA Design: Local vs. Global www.tugraz.at

PRA selects page for eviction ...

• local: ... from the same process

• Is the working set size fixed or adaptive?

• global: ... from any process

Working set algorithms are inherently global

Global strategies usually perform better:

• Process needs more pages:

• Thrashing although other processes

might have spare pages

• Process needs fewer pages:

• Memory waste despite possible thrashing

in another processes

66 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 537: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

PRA Design: Local vs. Global www.tugraz.at

PRA selects page for eviction ...

• local: ... from the same process

• Is the working set size fixed or adaptive?

• global: ... from any process

Working set algorithms are inherently global

Global strategies usually perform better:

• Process needs more pages:

• Thrashing although other processes

might have spare pages

• Process needs fewer pages:

• Memory waste despite possible thrashing

in another processes

66 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 538: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

PRA Design: Local vs. Global www.tugraz.at

PRA selects page for eviction ...

• local: ... from the same process

• Is the working set size fixed or adaptive?

• global: ... from any process

Working set algorithms are inherently global

Global strategies usually perform better:

• Process needs more pages:

• Thrashing although other processes

might have spare pages

• Process needs fewer pages:

• Memory waste despite possible thrashing

in another processes

66 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 539: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

PRA Design: Local vs. Global www.tugraz.at

PRA selects page for eviction ...

• local: ... from the same process

• Is the working set size fixed or adaptive?

• global: ... from any process

Working set algorithms are inherently global

Global strategies usually perform better:

• Process needs more pages:

• Thrashing although other processes

might have spare pages

• Process needs fewer pages:

• Memory waste despite possible thrashing

in another processes

66 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 540: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

PRA Design: Local vs. Global www.tugraz.at

PRA selects page for eviction ...

• local: ... from the same process

• Is the working set size fixed or adaptive?

• global: ... from any process

Working set algorithms are inherently global

Global strategies usually perform better:

• Process needs more pages:

• Thrashing although other processes

might have spare pages

• Process needs fewer pages:

• Memory waste despite possible thrashing

in another processes

66 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 541: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

PRA Design: Local vs. Global www.tugraz.at

PRA selects page for eviction ...

• local: ... from the same process

• Is the working set size fixed or adaptive?

• global: ... from any process

Working set algorithms are inherently global

Global strategies usually perform better:

• Process needs more pages:

• Thrashing although other processes

might have spare pages

• Process needs fewer pages:

• Memory waste despite possible thrashing

in another processes

66 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 542: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

PRA Design: Local vs. Global www.tugraz.at

PRA selects page for eviction ...

• local: ... from the same process

• Is the working set size fixed or adaptive?

• global: ... from any process

Working set algorithms are inherently global

Global strategies usually perform better:

• Process needs more pages:

• Thrashing although other processes

might have spare pages

• Process needs fewer pages:

• Memory waste despite possible thrashing

in another processes

66 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 543: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

• Page allocation latency crucial for performance

• Bad Latency when going through a lot of steps:

1. No free physical page

2. No clean pages

3. Swap out page (wait for disk)

4. Return released page to user

• Better: don’t let it get this far

• How realistic is that?

67 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 544: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

• Page allocation latency crucial for performance

• Bad Latency when going through a lot of steps:

1. No free physical page

2. No clean pages

3. Swap out page (wait for disk)

4. Return released page to user

• Better: don’t let it get this far

• How realistic is that?

67 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 545: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

• Page allocation latency crucial for performance

• Bad Latency when going through a lot of steps:

1. No free physical page

2. No clean pages

3. Swap out page (wait for disk)

4. Return released page to user

• Better: don’t let it get this far

• How realistic is that?

67 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 546: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

• Page allocation latency crucial for performance

• Bad Latency when going through a lot of steps:

1. No free physical page

2. No clean pages

3. Swap out page (wait for disk)

4. Return released page to user

• Better: don’t let it get this far

• How realistic is that?

67 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 547: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

• Page allocation latency crucial for performance

• Bad Latency when going through a lot of steps:

1. No free physical page

2. No clean pages

3. Swap out page (wait for disk)

4. Return released page to user

• Better: don’t let it get this far

• How realistic is that?

67 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 548: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

• Page allocation latency crucial for performance

• Bad Latency when going through a lot of steps:

1. No free physical page

2. No clean pages

3. Swap out page (wait for disk)

4. Return released page to user

• Better: don’t let it get this far

• How realistic is that?

67 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 549: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

• Page allocation latency crucial for performance

• Bad Latency when going through a lot of steps:

1. No free physical page

2. No clean pages

3. Swap out page (wait for disk)

4. Return released page to user

• Better: don’t let it get this far

• How realistic is that?

67 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 550: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

• Page allocation latency crucial for performance

• Bad Latency when going through a lot of steps:

1. No free physical page

2. No clean pages

3. Swap out page (wait for disk)

4. Return released page to user

• Better: don’t let it get this far

• How realistic is that?

67 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 551: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

Some classes are cheaper for swapping than others:

Class Referenced Dirty Properties

0 0 0

68 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

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Pre-Swapping www.tugraz.at

Some classes are cheaper for swapping than others:

Class Referenced Dirty Properties

0 0 0 Not used in a while and not modified → just evict

68 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 553: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

A Paging Daemon doing Pre-Swapping

• Paging Daemon mostly inactive

• Checks regularly: Evictable/unused page frames below threshold?

• Swap a dirty page

• Keep it in RAM

• Set dirty-bit to 0

→ Pre-swapped pages are evictable pages

→ Evictable pages are as good as unused pages (performance-wise)

69 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 554: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

A Paging Daemon doing Pre-Swapping

• Paging Daemon mostly inactive

• Checks regularly: Evictable/unused page frames below threshold?

• Swap a dirty page

• Keep it in RAM

• Set dirty-bit to 0

→ Pre-swapped pages are evictable pages

→ Evictable pages are as good as unused pages (performance-wise)

69 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 555: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

A Paging Daemon doing Pre-Swapping

• Paging Daemon mostly inactive

• Checks regularly: Evictable/unused page frames below threshold?

• Swap a dirty page

• Keep it in RAM

• Set dirty-bit to 0

→ Pre-swapped pages are evictable pages

→ Evictable pages are as good as unused pages (performance-wise)

69 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 556: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

A Paging Daemon doing Pre-Swapping

• Paging Daemon mostly inactive

• Checks regularly: Evictable/unused page frames below threshold?

• Swap a dirty page

• Keep it in RAM

• Set dirty-bit to 0

→ Pre-swapped pages are evictable pages

→ Evictable pages are as good as unused pages (performance-wise)

69 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 557: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

A Paging Daemon doing Pre-Swapping

• Paging Daemon mostly inactive

• Checks regularly: Evictable/unused page frames below threshold?

• Swap a dirty page

• Keep it in RAM

• Set dirty-bit to 0

→ Pre-swapped pages are evictable pages

→ Evictable pages are as good as unused pages (performance-wise)

69 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 558: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

A Paging Daemon doing Pre-Swapping

• Paging Daemon mostly inactive

• Checks regularly: Evictable/unused page frames below threshold?

• Swap a dirty page

• Keep it in RAM

• Set dirty-bit to 0

→ Pre-swapped pages are evictable pages

→ Evictable pages are as good as unused pages (performance-wise)

69 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 559: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

A Paging Daemon doing Pre-Swapping

• Paging Daemon mostly inactive

• Checks regularly: Evictable/unused page frames below threshold?

• Swap a dirty page

• Keep it in RAM

• Set dirty-bit to 0

→ Pre-swapped pages are evictable pages

→ Evictable pages are as good as unused pages (performance-wise)

69 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 560: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Pre-Swapping www.tugraz.at

A Paging Daemon doing Pre-Swapping

• Paging Daemon mostly inactive

• Checks regularly: Evictable/unused page frames below threshold?

• Swap a dirty page

• Keep it in RAM

• Set dirty-bit to 0

→ Pre-swapped pages are evictable pages

→ Evictable pages are as good as unused pages (performance-wise)

69 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 561: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Pinning www.tugraz.at

Maybe a page is required to stay in RAM?

→ Pinning

Scenario:

1. A process requests I/O (e.g. read(FD,bufferm,nrBytes)) and blocks

2. Other processes raise page faults

• This might replace the destination page

→ DMA transfer would go to wrong location

Avoiding this scenario:

→ Page must be locked in memory (= excluded from PRA)

• Alternatively: use (non-evictable) kernel buffers

70 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 562: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Pinning www.tugraz.at

Maybe a page is required to stay in RAM?→ Pinning

Scenario:

1. A process requests I/O (e.g. read(FD,bufferm,nrBytes)) and blocks

2. Other processes raise page faults

• This might replace the destination page

→ DMA transfer would go to wrong location

Avoiding this scenario:

→ Page must be locked in memory (= excluded from PRA)

• Alternatively: use (non-evictable) kernel buffers

70 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 563: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Pinning www.tugraz.at

Maybe a page is required to stay in RAM?→ Pinning

Scenario:

1. A process requests I/O (e.g. read(FD,bufferm,nrBytes)) and blocks

2. Other processes raise page faults

• This might replace the destination page

→ DMA transfer would go to wrong location

Avoiding this scenario:

→ Page must be locked in memory (= excluded from PRA)

• Alternatively: use (non-evictable) kernel buffers

70 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 564: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Pinning www.tugraz.at

Maybe a page is required to stay in RAM?→ Pinning

Scenario:

1. A process requests I/O (e.g. read(FD,bufferm,nrBytes)) and blocks

2. Other processes raise page faults

• This might replace the destination page

→ DMA transfer would go to wrong location

Avoiding this scenario:

→ Page must be locked in memory (= excluded from PRA)

• Alternatively: use (non-evictable) kernel buffers

70 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 565: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Pinning www.tugraz.at

Maybe a page is required to stay in RAM?→ Pinning

Scenario:

1. A process requests I/O (e.g. read(FD,bufferm,nrBytes)) and blocks

2. Other processes raise page faults

• This might replace the destination page

→ DMA transfer would go to wrong location

Avoiding this scenario:

→ Page must be locked in memory (= excluded from PRA)

• Alternatively: use (non-evictable) kernel buffers

70 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 566: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Pinning www.tugraz.at

Maybe a page is required to stay in RAM?→ Pinning

Scenario:

1. A process requests I/O (e.g. read(FD,bufferm,nrBytes)) and blocks

2. Other processes raise page faults

• This might replace the destination page

→ DMA transfer would go to wrong location

Avoiding this scenario:

→ Page must be locked in memory (= excluded from PRA)

• Alternatively: use (non-evictable) kernel buffers

70 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 567: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Pinning www.tugraz.at

Maybe a page is required to stay in RAM?→ Pinning

Scenario:

1. A process requests I/O (e.g. read(FD,bufferm,nrBytes)) and blocks

2. Other processes raise page faults

• This might replace the destination page

→ DMA transfer would go to wrong location

Avoiding this scenario:

→ Page must be locked in memory (= excluded from PRA)

• Alternatively: use (non-evictable) kernel buffers

70 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 568: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Pinning www.tugraz.at

Maybe a page is required to stay in RAM?→ Pinning

Scenario:

1. A process requests I/O (e.g. read(FD,bufferm,nrBytes)) and blocks

2. Other processes raise page faults

• This might replace the destination page

→ DMA transfer would go to wrong location

Avoiding this scenario:

→ Page must be locked in memory (= excluded from PRA)

• Alternatively: use (non-evictable) kernel buffers

70 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 569: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Page Pinning www.tugraz.at

Maybe a page is required to stay in RAM?→ Pinning

Scenario:

1. A process requests I/O (e.g. read(FD,bufferm,nrBytes)) and blocks

2. Other processes raise page faults

• This might replace the destination page

→ DMA transfer would go to wrong location

Avoiding this scenario:

→ Page must be locked in memory (= excluded from PRA)

• Alternatively: use (non-evictable) kernel buffers

70 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 570: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Take Aways www.tugraz.at

• Page translation is efficient because of caching

• Memory layout partially defined by binary and partially by the OS

• Good page replacement algorithms are fundamental for system performance

71 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 571: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Take Aways www.tugraz.at

• Page translation is efficient because of caching

• Memory layout partially defined by binary and partially by the OS

• Good page replacement algorithms are fundamental for system performance

71 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 572: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

Take Aways www.tugraz.at

• Page translation is efficient because of caching

• Memory layout partially defined by binary and partially by the OS

• Good page replacement algorithms are fundamental for system performance

71 Peter Lipp, Daniel Gruss — www.iaik.tugraz.at

Page 573: Operating Systems - Virtual Memory and Page Replacement · PTE 0 PDE 1023 PTE 1 PTE #PTI Byte 0 Byte 1 PTE 1023 4 KiB Page #PML4I O set PML4E 511 Byte 4095 x86-32 • 1 access into

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