OpenPET User Meeting: Status and Update

Woon-Seng Choong, Jennifer Huber, William Moses, Qiyu PengOctober 31, 2013

This work is supported in part by the Director, Office of Science, Office of Biological and Environmental Research, Biological Systems Science Division of the U.S. Department of Energy under Contract No. DE-AC02-05CH1231 and in part by the National Institutes of Health under grant R01 EB016104.

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Outline

• Introduction

• Detector Boards Status

• Firmware and Software Status

• Website

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OpenPET Vision

Open Source• Hardware, Firmware, and Software• Schematics, Gerbers, BOM,…

Standardized Architecture• Compatible Alternate Hardware• Software Readily Transportable

Active User Community• Share Software and Expertise• Module, Calibration, DAQ, Display…

OpenPET is the GATE ofNuclear Medical Imaging Electronics

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OpenPET Hardware Architecture

SupportBoard

DetectorBoard

Multiplexer Coincidence

Host PCData

Control

Detectors

PP

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Small System

Detector Unit

Host PC

• 1 Support Crate, Up To 8 Detector Boards • Up to 256 Analog Inputs (64 Block Detectors)

• PC Interface Board Connects to PC

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Standard System

• Up To 8 Detector Units, 1 Coincidence Units • Up to 2048 Analog Inputs (512 Block Detectors)

• Coincidence Interface Board Connects to CU

CI-

1

MB

-1M

B-1

MB

-1M

B-1

MB

-1M

B-1

MB

-1M

B-1

CI-

1

CI-

1

… (up to eight)

CU

DU0 DU1 DU7

Host PC

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OpenPET Hardware

Power and Fans

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Detector Unit

1 2 3 4 5 6 7 8 9 10 11 12

Support Board

Complete and available

Minor revision in progress

Complete and available

Under development

First version of 16-ch Detector Board has been fabricated and tested. Minor revision in progress.

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Support Crate

FPGAsPower

Fan

96-pin VME Connectors

Host PC Interface Board

User IO Board Debugging Board Support Board

8 slots for Detector Boards

12-slot 6U VME19” Rack Mountable Crate

• VME crate is available from Elma Electronics Inc.• Electronics boards are available from Terasic Technologies

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Detector Boards

• 16-Channel Detector Board

- A scaled-down version to provide working DB to the users.

- First version has been fabricated and tested.

- Minor design improvements and fixes are in progress.

- Final version to be available to users in a few months (early 2014).

• 32-Channel Detector Board (based on conventional design)

- Design is almost complete.

- Layout and fabrication to start in a few months.

• 32-Channel Detector Board (based on DRS4)

- Design to start next year.

- Expect to be available in 1-2 years.

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16-Channel Detector Board

16-channel front-endcircuitries

IN0

IN1

.

.

.

IN14

IN15

Only negative polarity inputs

FPGA

AlteraCyclone

III

2 MBMemory

96-p

in V

ME

Bac

kpla

ne C

onne

ctor

Clock /Slice Out

Clock /Slice In

Digital I/O

Singles Events

Communication Bus (JTAG, SPI)

PowerClock and Slice

Trigger

Control Lines

Data

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16-Channel Detector Board

Filter 7MHz

FPGA

Fast Comparator

Threshold Adjust (1-2500 mV)

x16 for each 16-ch Detector Board

Slow Comparator

Threshold Adjust (1 - 4000 mV)

Fast Amp

x10

OPA2694(+/-5V)

x-2

THS4303(+/-2.5V)

LTC6605-7(+5V)

MAX9602

MAX964

PECL to LVDS

SY55855VKG

SE to LVDS

+

-

+

-

OPA4227

12-bit ADC

ADS5282

IN

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16-Channel Detector Board

Input Termination

16-channelTiming Chain

16-channel Energy Chain

Digital I/O

FPGA(Cyclone III)

Logic AnalyzerConnector

2 MB SRAM

QUSB Connector

Power Regulator

External Clock Input

JTAG Connector

DIP Switch

ADC

AS Mode Connector

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16-Ch DB Evaluation

17.0% fwhm 15.5% fwhm

With high-performance electronics, energy resolution was 15.8% and 14.4%.

R-

9800

R-

9800

6.15 x 6.15 x 25 mm3

LSO crystals Ge-68

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16-Ch DB Evaluation

7.8% fwhm 6.1% fwhm

R-

9800

R-

9800

6.15 x 6.15 x 25 mm3

LaBr3 crystals Ge-68

With high-performance electronics, energy resolution was 5.6% and 4.7%.=> 16-Ch DB has good spectroscopic performance.

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16-Ch DB EvaluationPET block detector:

12x12 array of 4x4x22 mm3 LSO crystals, 4 Hamamatsu R-9800 PMTs

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FPGA TDC

1) Low resolution (500 – 1000 ps LSB)

- Based on multi-sampling.- Inputs are sent to four registers connected to four internal clocks (400 –

500 MHz) with 90° phase difference.- Easy to implement and takes less resources.

2) High resolution (25 – 50 ps LSB)

- Based on delay chain and wave union.- Include auto calibration to compensate for temperature and power supply

variation.- More complex to implement and takes more resources.

References:1) J. Wu, S. Hansen, and Z. Shi, “ADC and TDC implemented in using FPGA,” Proc. IEEE Nucl. Sci. Symp.

Conf. Rec., Honolulu, HI, 2007, pp. 281–286.2) J. Wu and Z. Shi, “The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay,”

Proc. IEEE Nucl. Sci. Symp. Conf. Rec., Dresden, Germany, 2008, pp. 3440–3446.

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Firmware/Software

System configuration and test (scripts)

System configuration

filesSystem HW/FW

DAQ configuration and DAQ(scripts)

System HW/FW

List mode data (with a head file)

Data analysis and visualization

(GUI and scripts)

List mode data (with a header file)

Data analysis reports

System calibration and characterization

(control console and scripts)

Acceptable range

definition ?

First Release

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Firmware/Software (“Oscilloscope” Mode)

• First Release: “Oscilloscope Mode” for Small System• Two Command Line Executables to Configure System and Acquire Data

Detector Board Support Board Host PC

ADC Readout

TimeStamp

Event T

ransfer In

Event T

ransfer Out

Setup & Control

Event M

ultiplexing

Coincidence

Processing

Event T

ransfer Out

Setup & Control

Event P

rocessing

Event T

ransfer In

Setup & Control

Event T

ransfer In

Event T

ransfer Out

Event T

ransfer Out

Event T

ransfer In

Completed

ADC Readout

Setup & Control

Event M

ultiplexing

Setup & Control Setup & Control

In Development

TDC

Coincidence

Processing

Event P

rocessing

Not Needed for Oscilloscope Mode

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Data Transfer Rate Via USB 2.0

• A maximum sustained data transfer rate of ~ 43 MB/s is achieved (theoretical maximum is 60 MB/s for USB 2.0)

Data rate (Million Bytes Per Second)

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Firmware / Software First Release

• Necessary firmware on 16-Channel DB and SB to control the hardware and acquire list mode data via USB.

- System configuration files to configure system.- List mode data is “Oscilloscope” mode.

• Command line executable with arguments to control/configure the system.Ex., opet_cmd <arg1> <arg2> <arg3> …

• Command line executable to acquire data in list mode.Ex., opet_acq <arg1> <arg2> <arg3> …

• Currently under development and testing.

• A major effort will go into documenting a User’s Guide before the first release.

• Will be released when the 16-channel Detector Board is made available.

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Website (openpet.lbl.gov)

Thank you for your attention