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Chang Lin, Dong Liu, Xueguang Wu, Zhiyuan He State Grid Smart Grid Research Institute, China

Weihua Wang, and Wei Li Opal-RT Technologies Inc., Canada

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Setup and Performance of a Combined Hardware-in-loop and Software-in-loop Test for MMC-HVDC Control and Protection System

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Outline

MMC and MMC-based HVDC installation in China Hierarchical structure of MMC controller Applications of Real-time simulation for MMC HVDC Combined HIL and SIL Test Test Results

MMC-based HVDC

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SM1

SM2

SMk

SM1

SM2

SMk

Vdc+

Vdc-

Vt-a

Ia Ls

Ls

Iup-a

Ilow-a

Vup-a

Vlow-a

Iup-b

Ilow-b Ilow-c

Idc+

Idc-

Vsm1

Vsm2

Vsmk

+

+-

-

+

-

+

-

Vsmup-a

SM1

SM2

SMk

SM1

SM2

SMk

Vt-a

Ia Ls

Ls

Vup-b

Vlow-b

Iup-cSM1

SM2

SMk

SM1

SM2

SMk

Vt-a

Ia Ls

Ls

Vup-c

Vlow-c

Sub-module (SM)

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Recent MMC projects in China

MMC Project in operation

MMC Project in planing

Nanhui, 2011

Zhoushan, 2014

Nanao, 2013

Hierarchical structure of MMC controller

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System Controller

Operator Work Station

LAN

PCPA

AI DI/DO

PCPB

AI DI/DO

Valve Base Controller (VBC)

VBCA

Current controller

Arm Controller

Current Controller

Arm Controller

VBCB

Inte

rface

Enco

der

Deco

der

Sub-module Controller (SMC)

SMC1

SMC2

SMC3

SMC4

SMC n

…

Control Instructions

System A

System B

+

-

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Multi-rate MMC model for Real-time Simulation

SM 1MMCArm 1

SM n

. . .

PCIe

Arm inductor

MMCvalve

MMC arm 1

Vmmc

Iarm. . .

Rest of the system

CPU

MMC arm n

MMCArm n

Vmmc

Iarm

. . .

FPGA

gating pulse

capacitorvoltages

+

-

Vmmc from FPGA

Iarm to FPGA

T1

T2

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MMC Simulator

More than 3000 I/O signalsModel time step: 25 microseconds !

Delivered in 2011 to ABB (Switzerland) and NARI Relay (China)

Full Hardware-in-the-loop test

Hardware-in-the loop test with simulated SMC

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Combined HIL and SIL Test

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System Controller

Operator Work Station

LAN

PCPA

AI DI/DO

PCPB

AI DI/DO

FPGA 1 FPGA 2

Valve Base Controller (VBC)

VBCA

Current controller

Arm Controller

Current Controller

Arm Controller

VBCB

Inte

rface

Enco

der

Deco

der

Sub-module Controller (SMC)

SMC1

SMC2

SMC3

SMC4

SMC n

……

Control Instructions

System A

System B

+

-

Combined HIL and SIL Test

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Simulated Grid & MMC StationActual Pole Controller

SimulatedMMC Valves andLow-level Valve Controller

Parameters of the Simulated MMC-HVDC

Power Grid Parameters Station 1 Station 2

Based Power (MVA) 1000

Based Voltage (kV) 220

Short-Circuit Ratio 9.9 10.4

Transformer Connection D11/Yng

Transformer Primary Voltage (kV) 220

Transformer Secondary Voltage (kV) 330

Transformer Grounding Resistance (Ω)

20000

Charging Resistance (Ω) 10000

DC Rated Voltage (kV) ±320

DC to Ground Resistance (Ω) 3000000

DC Smoothing Reactor (mH) 50

DC Cable resistance (Ω/km) 0.0127

DC Cable Capacitance (μF/km) 0.93

DC Cable Inductance (mH/km) 12.74

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Submodule Capacitance

25.5 MF

Submodule Resistance 20000ΩArm Inductance 0.138 HArm resistance 1 Ω

number of submodules 400

Test results – Start and stop sequence

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Test results – Real-power step response

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Test results – Capacitor voltage balancing

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Conclusion

The proposed HIL and SIL platform can establish such a high-fidelity environment that the PCP can be operated as if it is installed in the real substation • PCP is tested using the HIL method• VBC is studied using the SIL approach on the multi-FPGA based real-time simulator.

The operation of starting and stopping the MMC, as well as real and reactive power step responses are fully tested on the combined HIL and SIL platform.

The test results validate that the C&P system has been designed to fulfill the specifications.

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