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OPA2171-EPSBOS735 –SEPTEMBER 2015

OPA2171-EP 36-V, Single-Supply, SOT553, General-Purpose Operational Amplifiers1 Features 2 Applications1• Supply Range: 2.7 to 36 V, ±1.35 V to ±18 V • Tracking Amplifier in Power Modules• Low Noise: 14 nV/√Hz • Merchant Power Supplies• Low Offset Drift: ±0.3 µV/°C (Typ) • Transducer Amplifiers• RFI Filtered Inputs • Bridge Amplifiers• Input Range Includes the Negative Supply • Temperature Measurements• Input Range Operates to Positive Supply • Strain Gauge Amplifiers• Rail-to-Rail Output • Precision Integrators• Gain Bandwidth: 3 MHz • Battery-Powered Instruments• Low Quiescent Current: 475 µA per Amplifier • Test Equipment• High Common-Mode Rejection: 120 dB (Typ)

3 Description• Low-Input Bias Current: 8 pAThe OPA2171-EP is a 36-V, single-supply, low-noise• microPackage: Dual in VSSOP-8 operational amplifier with the ability to operate on

• Supports Defense, Aerospace, and Medical supplies ranging from 2.7 V (±1.35 V) to 36 V (±18Applications: V). These devices are available in micro-packages

and offer low offset, drift, and bandwidth with low– Controlled Baselinequiescent current. The single, dual, and quad– One Assembly/Test Site versions all have identical specifications for maximum

– One Fabrication Site design flexibility.– Available in Extended (–55°C to 125°C) Unlike most operational amplifiers, which are

Temperature Range specified at only one supply voltage, the OPA2171-– Extended Product Life Cycle EP is specified from 2.7 to 36 V. Input signals beyond

the supply rails do not cause phase reversal. The– Extended Product-Change NotificationOPA2171-EP is stable with capacitive loads up to– Product Traceability 300 pF. The input can operate 100 mV below thenegative rail and within 2 V of the top rail duringUnity-Gain Buffer With RISO Stability normal operation. Note that these devices canCompensation operate with full rail-to-rail input 100 mV beyond thetop rail, but with reduced performance within 2 V ofthe top rail.

The OPA2171-EP operational amplifier is specifiedfrom –55°C to 125°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)OPA2171-EP VSSOP (8) 2.30 mm × 2.00 mm

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

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OPA2171-EPSBOS735 –SEPTEMBER 2015 www.ti.com

Table of Contents7.3 Feature Description................................................. 141 Features .................................................................. 17.4 Device Functional Modes........................................ 152 Applications ........................................................... 1

8 Application and Implementation ........................ 163 Description ............................................................. 18.1 Application Information............................................ 164 Revision History..................................................... 28.2 Typical Application ................................................. 175 Pin Configuration and Functions ......................... 3

9 Power Supply Recommendations ...................... 196 Specifications......................................................... 410 Layout................................................................... 206.1 Absolute Maximum Ratings ...................................... 4

10.1 Layout Guidelines ................................................ 206.2 ESD Ratings.............................................................. 410.2 Layout Example .................................................... 206.3 Recommended Operating Conditions....................... 4

11 Device and Documentation Support ................. 216.4 Thermal Information .................................................. 411.1 Community Resources.......................................... 216.5 Electrical Characteristics........................................... 511.2 Trademarks ........................................................... 216.6 Typical Characteristics .............................................. 711.3 Electrostatic Discharge Caution............................ 217 Detailed Description ............................................ 1411.4 Glossary ................................................................ 217.1 Overview ................................................................. 14

12 Mechanical, Packaging, and Orderable7.2 Functional Block Diagram ....................................... 14Information ........................................................... 21

4 Revision History

DATE REVISION NOTESSeptember 2015 * Initial release.

2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: OPA2171-EP


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1

2

3

4

8

7

6

5

V+

OUT B

-IN B

+IN B

OUT A

-IN A

+IN A

V-

OPA2171-EPwww.ti.com SBOS735 –SEPTEMBER 2015

5 Pin Configuration and Functions

DCU Package8-Pin VSSOP

Top View

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.+IN A 3 I Noninverting input, channel A+IN B 5 I Noninverting input, channel B–IN A 2 I Inverting input, channel A–IN B 6 I Inverting input, channel BOUT A 1 O Output, channel AOUT B 7 O Output, channel BV+ 7 — Positive (highest) power supplyV– 4 — Negative (lowest) power supply

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3



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6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range, unless otherwise noted (1)

MIN MAX UNITSupply voltage ±20 V

Voltage (V–) – 0.5 (V+) + 0.5 VSignal input pins

Current –10 10 mAOutput short circuit (2) ContinuousJunction temperature 150 °CStorage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Short-circuit to ground, one amplifier per package.

6.2 ESD RatingsVALUE UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000ElectrostaticV(ESD) Vdischarge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNITSupply voltage (V+ – V–) 4.5 (±2.25) 36 (±18) VOperating temperature, TJ –55 125 °C

6.4 Thermal InformationOPA2171-EP

THERMAL METRIC (1) DCU (VSSOP) UNIT

8 PINS

RθJA Junction-to-ambient thermal resistance 175.2 °C/W

RθJC(top) Junction-to-case(top) thermal resistance 74.9 °C/W

RθJB Junction-to-board thermal resistance 22.2 °C/W

ψJT Junction-to-top characterization parameter 1.6 °C/W

ψJB Junction-to-board characterization parameter 22.8 °C/W

RθJC(bot) Junction-to-case(bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.




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6.5 Electrical Characteristicsat TJ = 25°C, VS = 2.7 to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITOFFSET VOLTAGEInput offset voltage VOS 0.25 ±1.8 mV

Over temperature TJ = –55°C to 125°C 0.3 ±2 mVDrift dVOS/dT TJ = –55°C to 125°C 0.3 µV/°Cvs power supply PSRR VS = 4 to 36 V, TA = –55°C to 125°C 1 ±5 µV/V

Channel separation, dc dc 5 µV/VINPUT BIAS CURRENTInput bias current IB ±8 ±15 pA

Over temperature TJ = –55°C to 125°C ±4 nAInput offset current IOS ±4 pA

Over temperature TJ = –55°C to 125°C ±4 nANOISEInput voltage noise ƒ = 0.1 to 10 Hz 3 µVPP

ƒ = 100 Hz 25 nV/√HzInput voltage noise density en ƒ = 1 kHz 14 nV/√HzINPUT VOLTAGECommon-mode voltage VCM (V–) – 0.1 V (V+) – 2 V Vrange (1)

VS = ±2 V, (V–) – 0.1 V < VCM < (V+) – 2 V, 87 104 dBTJ = –55°C to 125°CCommon-mode rejection CMRRratio VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V, 104 120 dBTJ = –55°C to 125°CINPUT IMPEDANCE

MΩ ||Differential 100 || 3 pF1012Ω ||Common-mode 6 || 3 pF

OPEN-LOOP GAINVS = 4 to 36 V, (V–) + 0.35 V < VO < (V+) –Open-loop voltage gain AOL 110 130 dB0.35 V, TJ = –55°C to 125°C

FREQUENCY RESPONSEGain bandwidth product GBP 3.0 MHzSlew rate SR G = +1 1.5 V/µs

To 0.1%, VS = ±18 V, G = +1, 10-V step 6 µsSettling time tS To 0.01% (12 bit), VS = ±18 V, G = +1, 10-V 10 µsstepOverload recovery time VIN × Gain > VS 2 µsTotal harmonic distortion + THD+N G = +1, ƒ = 1kHz, VO = 3VRMS 0.0002%noiseOUTPUTVoltage output swing from VO VS = 5 V, RL = 10 kΩ 30 mVrail

RL = 10 kΩ, AOL ≥ 110 dB,Over temperature (V–) + 0.35 (V+) – 0.35 VTJ = –55°C to 125°CShort-circuit current ISC +25/–35 mACapacitive load drive CLOAD See Typical Characteristics pFOpen-loop output resistance RO ƒ = 1 MHz, IO = 0 A 150 Ω

(1) The input range can be extended beyond (V+) – 2 V up to V+. See Typical Characteristics and Application and Implementation foradditional information.




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Electrical Characteristics (continued)at TJ = 25°C, VS = 2.7 to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITPOWER SUPPLYSpecified voltage range VS 2.7 36 VQuiescent current per IQ IO = 0 A 475 595 µAamplifier

Over temperature IO = 0 A, TJ = –55°C to 125°C 650 µATEMPERATUREOperating temperature TJ –55 125 °C




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6.6 Typical CharacteristicsTable 1. Characteristic Performance Measurements

DESCRIPTION FIGUREOffset Voltage Production Distribution Figure 1Offset Voltage Drift Distribution Figure 2Offset Voltage vs Temperature Figure 3Offset Voltage vs Common-Mode Voltage Figure 4Offset Voltage vs Common-Mode Voltage (Upper Stage) Figure 5Offset Voltage vs Power Supply Figure 6IB and IOS vs Common-Mode Voltage Figure 7Input Bias Current vs Temperature Figure 8Output Voltage Swing vs Output Current (Maximum Supply) Figure 9CMRR and PSRR vs Frequency (Referred-to Input) Figure 10CMRR vs Temperature Figure 11PSRR vs Temperature Figure 120.1-Hz to 10-Hz Noise Figure 13Input Voltage Noise Spectral Density vs Frequency Figure 14THD+N Ratio vs Frequency Figure 15THD+N vs Output Amplitude Figure 16Quiescent Current vs Temperature Figure 17Quiescent Current vs Supply Voltage Figure 18Open-Loop Gain and Phase vs Frequency Figure 19Closed-Loop Gain vs Frequency Figure 20Open-Loop Gain vs Temperature Figure 21Open-Loop Output Impedance vs Frequency Figure 22Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 23, Figure 24No Phase Reversal Figure 25Positive Overload Recovery Figure 26Negative Overload Recovery Figure 27Small-Signal Step Response (100 mV) Figure 28, Figure 29Large-Signal Step Response Figure 30, Figure 31Large-Signal Settling Time (10-V Positive Step) Figure 32Large-Signal Settling Time (10-V Negative Step) Figure 33Short-Circuit Current vs Temperature Figure 34Maximum Output Voltage vs Frequency Figure 35Channel Separation vs Frequency Figure 36




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10000

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10 Typical Units Shown

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OperationV = +18.1VCM

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VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.

Figure 2. Offset Voltage Drift DistributionFigure 1. Offset Voltage Production Distribution

Figure 3. Offset Voltage vs Temperature Figure 4. Offset Voltage vs Common-Mode Voltage

Figure 5. Offset Voltage vs Common-Mode Voltage (Upper Figure 6. Offset Voltage vs Power SupplyStage)




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30

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de

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atio

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V = 4V to 36VS

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IB

IOS



Figure 7. IB and IOS vs Common-Mode Voltage Figure 8. Input Bias Current vs Temperature

Figure 9. Output Voltage Swing vs Output Current Figure 10. CMRR and PSRR vs Frequency (Referred-to(Maximum Supply) Input)

Figure 11. CMRR vs Temperature Figure 12. PSRR vs Temperature




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0.65

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32282420

Specified Supply-Voltage Range

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Figure 13. 0.1-Hz to 10-Hz Noise Figure 14. Input Voltage Noise Spectral Density vsFrequency

Figure 15. THD+N Ratio vs Frequency Figure 16. THD+N vs Output Amplitude

Figure 17. Quiescent Current vs Temperature Figure 18. Quiescent Current vs Supply Voltage




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50

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ROUT

CL

OPA171

RL

G = +1R = 0WOUT

R = 25WOUT

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Figure 19. Open-Loop Gain and Phase vs Frequency Figure 20. Closed-Loop Gain vs Frequency

Figure 21. Open-Loop Gain vs Temperature Figure 22. Open-Loop Output Impedance vs Frequency

Figure 23. Small-Signal Overshoot vs Capacitive Load (100- Figure 24. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) mV Output Step)




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Time (20 s/div)m

20

mV

/div

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R 2kWF =R 2kWI =

CL

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L

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VOUT

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VOUTOPA171

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WL

L

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Output

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/div

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-18V

37VPP

Sine Wave

( 18.5V)±

OPA171

Time (5 s/div)m

5V

/div VIN

VOUT

2kW

20kW

VIN

VOUTOPA171

G = 10-

+18V

-18V



Figure 25. No Phase Reversal Figure 26. Positive Overload Recovery

Figure 27. Negative Overload Recovery Figure 28. Small-Signal Step Response (100 mV)

Figure 29. Small-Signal Step Response (100 mV) Figure 30. Large-Signal Step Response




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15

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V = 5V±S

V = 1.35V±S

Maximum output voltage without

slew-rate induced distortion.

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84 28 3224201612

12-Bit Settling

( 1/2LSB = 0.024%)± ±

G = 1-50

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( 1/2LSB = 0.024%)± ±

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2V

/div

G = 1

R = 10k

C = 100pF

-

WL

L



Figure 31. Large-Signal Step Response Figure 32. Large-Signal Settling Time (10-V Positive Step)

Figure 33. Large-Signal Settling Time (10-V Negative Step) Figure 34. Short-Circuit Current vs Temperature

Figure 35. Maximum Output Voltage vs Frequency Figure 36. Channel Separation vs Frequency




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NCHInput Stage

PCHInput Stage

2nd Stage OutputStage

+IN

±IN

Ca

Cb

PCHFF Stage

OUT

+

±

+

±

+

±

+

±

+

±


7 Detailed Description

7.1 OverviewThe OPA2171-EP operational amplifier provides high overall performance, making it ideal for many general-purpose applications. The excellent offset drift of only 2 µV/°C provides excellent stability over the entiretemperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, andAOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decouplingcapacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Operating CharacteristicsThe OPA2171-EP amplifier is specified for operation from 2.7 to 36 V (±1.35 to ±18 V). Many of thespecifications apply from –55°C to 125°C. Parameters that can exhibit significant variance with regard tooperating voltage or temperature are presented in Typical Characteristics.

7.3.2 Phase-Reversal ProtectionThe OPA2171-EP has an internal phase-reversal protection. Many operational amplifiers exhibit a phase reversalwhen the input is driven beyond its linear common-mode range. This condition is most often encountered innoninverting circuits when the input is driven beyond the specified common-mode voltage range, causing theoutput to reverse into the opposite rail. The input of the OPA2171-EP prevents phase reversal with excessivecommon-mode voltage. Instead, the output limits into the appropriate rail. Figure 37 shows this performance.




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Output

Output

Time (100 s/div)m

5V

/div

+18V

-18V

37VPP

Sine Wave

( 18.5V)±

OPA171


Feature Description (continued)

Figure 37. No Phase Reversal

7.4 Device Functional Modes

7.4.1 Common-Mode Voltage RangeThe input common-mode voltage range of the OPA2171-EP extends 100 mV below the negative rail and within 2V of the top rail for normal operation.

This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within2 V of the top rail. Table 2 summarizes the typical performance in this range.

Table 2. Typical Performance RangePARAMETER MIN TYP MAX UNIT

Input Common-Mode Voltage (V+) – 2 (V+) + 0.1 VOffset voltage 7 mV

vs Temperature 12 µV/°CCommon-mode rejection 65 dBOpen-loop gain 60 dBGBW 0.7 MHzSlew rate 0.7 V/µsNoise at ƒ = 1kHz 30 nV/√Hz




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5kW

OPA17110mA max

V+

VIN

VOUT

IOVERLOAD


8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Electrical OverstressDesigners often ask about the capability of an operational amplifier to withstand electrical overstress. Thesequestions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin.Each of these different pin functions have electrical stress limits determined by the voltage breakdowncharacteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them fromaccidental ESD events both before and during product assembly.

These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to10 mA as stated in Absolute Maximum Ratings. Figure 38 shows how a series input resistor may be added to thedriven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and itsvalue should be kept to a minimum in noise-sensitive applications.

Figure 38. Input Current Protection

An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed toprovide a current path around the operational amplifier core to prevent it from being damaged. The energyabsorbed by the protection circuitry is then dissipated as heat.

When the operational amplifier connects into a circuit, the ESD protection components are intended to remaininactive and not become involved in the application circuit operation. However, circumstances may arise wherean applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a risk thatsome of the internal ESD protection circuits may be biased on, and conduct current. Any such current flowoccurs through ESD cells and rarely involves the absorption device.

If there is uncertainty about the ability of the supply to absorb this current, external Zener diodes may be addedto the supply pins. Select the Zener voltage such that the diode does not turn on during normal operation.

However, its Zener voltage should be low enough so that the Zener diode conducts if the supply pin begins torise above the safe operating supply voltage level.




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Gai

n (d

B)

0

AOL

1/��20

40

60

80

10 100 1k 10k 100k 1M

100

120

10M 100M

Frequency (Hz)

20 dBROC

dec

40 dB

1 dec

z

ISO LOAD

1f

2 R C�

u u u

� �p

ISO o LOAD

1f

2 R R C�

u u � u

� �LOAD ISO

o ISO LOAD

1 + C × R × sT(s) =

1 + R + R × C × s

+

CLOAD+±

VIN

VOUT+VS

RISO

-VS


8.2 Typical ApplicationFigure 39 shows a capacitive load drive solution using an isolation resistor. The OPA2171-EP device can beused capacitive loads such as cable shields, reference buffers, MOSFET gates, and diodes. The circuit uses anisolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the open loop gain of the system toensure the circuit has sufficient phase margin.

Figure 39. Unity-Gain Buffer with RISO Stability Compensation

8.2.1 Design RequirementsThe design requirements are:• Supply voltage: 30 V (±15 V)• Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF• Phase margin: 45° and 60°

8.2.2 Detailed Design ProcedureFigure 39 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for thecircuit in Figure 39. Not shown in Figure 39 is the open-loop output resistance of the op amp, Ro.

(1)

The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro +RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system isobtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20dB/decade. Figure 40 depicts the concept. The 1/β curve for a unity-gain buffer is 0 dB.

Figure 40. Unity-Gain Amplifier with RISO Compensation




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50

45

40

35

30

25

20

15

10

5

0

Ove

rsh

oo

t (%

)

0 100 200 300 400 500 600 700 800 900 1000


+18V

-18V

ROUT

CL

OPA171

RL

G = +1R = 0WOUT

R = 25WOUT

R = 50WOUT

R = 10kWL

50

45

40

35

30

25

20

15

10

5

0

Ove

rsh

oo

t (%

)

0 100 200 300 400 500 600 700 800 900 1000


OPA171

R =I 10kW

ROUT

CL

RF = 10kW

+18V

-18V

G = 1-

R = 0WOUT

R = 25WOUT

R = 50WOUT


Typical Application (continued)ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especiallythe accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes ameasurement of overshoot percentage and AC gain peaking of the circuit using a function generator,oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 3shows the overshoot percentage and AC gain peaking that correspond to phase margins of 45° and 60°. Formore details on this design and other alternative devices that can be used in place of the OPA171, refer to thePrecision Design, Capacitive Load Drive Solution using an Isolation Resistor (TIPD128).

Table 3. Phase Margin versus Overshoot and AC GainPeaking

PHASE MARGIN OVERSHOOT AC GAIN PEAKING45° 23.3% 2.35 dB60° 8.8% 0.28 dB

8.2.2.1 Capacitive Load and StabilityThe dynamic characteristics of the OPA2171-EP have been optimized for commonly encountered operatingconditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin ofthe amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolatedfrom the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to50 Ω) in series with the output. Figure 41 and Figure 42 illustrate graphs of small-signal overshoot versuscapacitive load for several values of ROUT. Also, refer to Applications Bulletin AB-028 (SBOA015), available fordownload from www.ti.com for details of analysis techniques and application circuits.

Figure 41. Small-Signal Overshoot vs Capacitive Load Figure 42. Small-Signal Overshoot vs Capacitive Load(100-mV Output Step) (100-mV Output Step)




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Capacitive Load (nF)

Isol

atio

n R

esis

tor,

RIS

O (:

)

0.01 0.1 1 10 100 10001

10

100

1000

10000

D001

45q Phase Margin60q Phase Margin


8.2.3 Application CurveThe OPA2171-EP device meets the supply voltage requirements of 30 V. The OPA2171-EP device was testedfor various capacitive loads and RISO was adjusted to achieve an overshoot corresponding to Table 3. Figure 43shows the test results.

Figure 43. RISO vs CLOAD

9 Power Supply RecommendationsThe OPA2171-EP is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications applyfrom –40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage ortemperature are presented in the Typical Characteristics section.

CAUTIONSupply voltages larger than 40 V can permanently damage the device; see theAbsolute Maximum Ratings table.

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For detailed information on bypass capacitor placement, see the Layout section.




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Place components close to device and to each other to reduce parasitic errors

GND

GND

VIN

VOUT

VS+

GND VS ±

Run the input traces as far away from the supply lines as possible

V+

OUT B

±IN B

+IN B

OUT A

±IN A

+IN A

V±

Use low-ESR, ceramic bypass capacitor

Ground (GND) plane on another layer(or GND for single supply)

Only needed for dual-supply operation


10 Layout

10.1 Layout GuidelinesFor best operational performance of the device, TI recommends good printed circuit board (PCB) layoutpractices. Low-loss, 0.1-µF bypass capacitors should be connected between each supply pin and ground, placedas close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supplyapplications.

10.2 Layout Example

Figure 44. Operational Amplifier Board Layout for Noninverting Configuration




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11 Device and Documentation Support

11.1 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

11.2 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

11.3 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

11.4 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.




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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

OPA2171MDCUTEP ACTIVE VSSOP DCU 8 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -55 to 125 ZGAA

V62/15605-01XE ACTIVE VSSOP DCU 8 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -55 to 125 ZGAA

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

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PACKAGE OPTION ADDENDUM

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Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF OPA2171-EP :

• Catalog: OPA2171

• Automotive: OPA2171-Q1

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

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TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

OPA2171MDCUTEP VSSOP DCU 8 250 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

OPA2171MDCUTEP VSSOP DCU 8 250 202.0 201.0 28.0

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 2

IMPORTANT NOTICE

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