Abstract

Introduction

Materials and Procedures

Results

Conclusions

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EE 177 Logic Circuits and Digital Electronics

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One-way Road Intersection Traffic Light

A Simple Logic Design

Mindanao State University

College of Engineering

Geraldine T. Casas, 2007-0057 Gayzel P. Dolor, 2008-0056

Mojahid A. Manapa-at, 2008-0296 Mary Rose G. Tabao, 2007-0015

EE 177 Logic Circuits and Digital Electronics MTh 2:30-4:00

1stSemester, AY 2010-2011

August 28, 2011

Engr. Edilberto C. Vergara

Instructor III

i

Table of Contents

Abstract 1

Introduction 1

Design Specification 3

Design Procedure 5

Results 11

Conclusion 12

Appendices

Appendix A. Clock Design Procedure I

Appendix B. Multisim™ Simulations Screenshots V

References VIII

1

Abstract

One of the vital inventions of mankind is the traffic lights which up to the present are

continuously still being modified for a more satisfactory result. Traffic lights are used to control

competing flows of traffic and serve as road signals to cars for a smooth and convenient travel. With the

aid of the obtained knowledge in logic circuits and digital electronics, a one-way traffic light design was

established.

The design was initiated by a definite goal which is to make a one-way traffic light mounted to

the road intersection with sensors used to detect the presence of vehicles leading to light transitions. After

which is the execution of logical operations of the design with the used of Moore model showing how and

when the network changes state. The now well established design was then tested on a MULTISIM where

the obtained result was analyzed. Modifications were done until the desired output, conforming to the

design specifications were attained. Armed with sufficient and efficient technical know-how, the Simple

Traffic Light Design was accomplished.

Introduction

During the horse and buggy days, traffic in big cities was often heavy. With the coming of

automobiles, the situation got even worse. Precisely, traffic on roads take place when a number of

pedestrians, ridden or herded animals, vehicles, streetcars and other conveyances occurs either singly or

simultaneously while using the public way for purposes of travel.

Traffics are hindrance to those who are in a hurry and may also cause accidents. To avoid such

occurrence, traffic lights are adapted for street use. These are signaling devices positioned at road

intersections and other locations to control competing flows of traffic. They alternate the right-of-way of

road users by displaying lights of a standard color. They make use of three colors, each provides distinct

signal that a car must follow. There’s a green light allowing a car to proceed in the direction denoted, a

yellow light denoting prepare to stop short of the intersection, and a red light prohibiting it to proceed.

2

Time-controlled and sensor-controlled traffic lights have been implemented nowadays on

different types of road intersections such as cross intersections, T intersections and Y intersections. The

former operates on a timing mechanism that changes the lights after a given interval while the latter

senses the presence and absence of vehicles, and reacts accordingly. Sensor-controlled system reacts to

motion to trigger light changes. Putting it into operation in a one-way road intersection, sensors are

positioned on each lane at the cross-section to detect that a volume of cars has pulled up. These detectors

are driven by switches that cause light transitions.

To govern the actions of the traffic system, algorithms will be used. Specifically, Boolean logic

will be employed. It consists of binary variables and a set of logical operations. The said variables will be

used to represent state transitions. The logical operations will be executed using a Moore model.

Herewith, is a sequential circuit that will be composed of a state register driven by an input combinational

logic. It will also consist of an output combinational logic which is a function of state registers.

Aided with the right concepts and principles with the well-defined design parameters, the

researchers eagerly hope to come up with the desired output which on this particular case is the own

proposed one-way traffic light design.

3

G1 Y1

R1

G2 Y2 R2

X

Y

Ro

ad 1

R

oad

1

Road 2 Road 2

TL2

TL

1

Design Specification

The main goal in this project is to design a one-way road intersection as shown in figure 1. That

is, a car from road 1 can go straight or turn left but is unable to turn right. Also, a car from road 2 can go

straight or turn right but is unable to turn left. Sensors (i.e., x and y) are placed on each side to determine

if a car is present at either road. These are used as inputs to the circuit being designed. Also, traffic lights

are positioned as shown (i.e., TL1 and TL2). Individual colors of the traffic lights are designated with

certain letter-number combination as shown. A third input to the circuit is a fifteen-second timer which

goes high if 15-seconds had passed and resets after such.

Figure 1. Road Layout

4

For a clear understanding of its behavior, refer to the diagram of Figure 2. As shown, there can

only be four states for which transitions occur. It follows a cyclical path and is unidirectional. Considering

G1R2 as the initial state, shifting to the next state Y1R2 is possible as long as the timer is high regardless

of the presence or absence of cars on road 1 and 2. Another case is when a car is present on road 2 and not

on road 1, transition happens. Otherwise, it will remain on this state.

For the Y1R2 state, all conditions lead to the next state R1G2 after a certain time. Again,

transition from state R1G2 into R1Y2 occurs when the timer is high or when a car is present in road 1 and

not in road 2. After which, the state R1Y2 goes back to G1R2 state. These four states continue

transitioning for as long as the circuit runs.

Figure 2. State diagram

TL1 TL2

TL1 TL2

TL1 TL2

TL1 TL2

5

Design Procedure

The design was started by designating a representation of each state as shown in Table 1. It is

comprised of four states. In the first state, green light of TL1 is ON together with the red light of TL2. For

the second state, green light of TL1 switches yellow and TL2 holds on to red. Next, for the third state, the

conditions of state 1 are reversed. Now R1 and G2 are ON. R1 Then holds on while G2 switches to Y2

for the fourth state. After which, it will go back to state 1. Binary representation of the said states with

corresponding outputs is shown in Table 2.

States Outputs

A B R1 Y1 G1 R2 Y2 G2

0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0

1 0 1 0 0 0 0 1

1 1 1 0 0 0 1 0

The circuit has three inputs: , , and . These represent the road1 sensor, road2 sensor, and the

fifteen seconds timer, respectively. It was driven by a clock source with an interval of 3 seconds. This

clock source also drives a network in the circuit that performs 15 seconds time count which will control

the time interval of a green light in the ON state. Such network is a Negative Edge Triggered Four Bit

Binary Counter (sn74ls93). The binary counter was configured to count from binary 000 to 111. This was

done by using only the outputs , , and with the least significant bit. It is desired to have , the

15 seconds timer, be high (one) for binary counter value of 101. Truth table of which is shown in Table 3.

It is seen in the table that there are don’t care conditions for 110 and 111. It is because these values are

States

1 G1 R2

2 Y1 R2

3 R1 G2

4 R1 Y2

Table 1. Representation of States

Table 2. Binary Representation of States and Outputs

6

not needed in the timer. The timer will count from 000 to 101 and then go back to 000 by resetting the

counter. How will the counter reset will be discussed shortly.

Qd Qc Qb t

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 X

1 1 1 X

The truth table of table 3 was mapped in a three-variable map shown in Table 4 and the

corresponding Boolean function was obtained.

Qc

0 0 0 0

Qd 0 1 X X

Qb

The Boolean function for t is:

Eq. 1

Block diagram of the 15 seconds timer connected to the clock output is shown in Figure 2. Design

procedure for the LM555 and its operation are discussed in Appendix A. The output of the LM555 was

set as input B to the counter. This was necessary to generate an 8-bit count. Here, the reset inputs of the

counter were grounded for the circuit to be operational. The outputs B and D of the counter were ANDed

as based on Boolean function obtained in Eq. 1. The output of this AND is the input .

Table 3. Timer Truth Table

Table 4. Timer Map

7

The traffic light was designed using Moore model. Positive Edge Triggered D Flip-flops

(sn74ls74) were chosen as state registers. Figure 4 shows the Moore model design.

The design for the next state combinational logic that will drive the state registers was then made.

Taking into account the transition conditions discussed in the Design Specification, a state table is

obtained as shown in Table 5. Present states A and B and inputs X, Y and t were mapped on a five

variable map and corresponding Boolean functions for A’ and B’ were obtained. Since D Flip-flops were

used, the inputs to the flip-flops are A’ and B’ themselves. Boolean function for A’ was simplified to a

single XOR operation while B’ was simplified so as to be implemented with all NAND.

Figure 3. Clock and Fifteen-second Timer Diagram

Figure 4. Moore model design

Next State

Combination

al Logic

Output

Combination

al Logic

State

Registers

Clk

Inputs Outputs

8

Present States Inputs Next States Flip-flop inputs

A B X Y t A’ B’ Da Db

0 0 0 0 0 0 0 0 0

0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 1 0 1

0 0 0 1 1 0 1 0 1

0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1

0 0 1 1 0 0 0 0 0

0 0 1 1 1 0 1 0 1

0 1 X X X 1 0 1 0 1 0 0 0 0 1 0 1 0

1 0 0 0 1 1 1 1 1

1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 1 1

1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 1 1 1 1 0 1 1 0 1 0 1 0

1 0 1 1 1 1 1 1 1

1 1 X X X 0 0 0 0

Map of A’ and B’ are shown in the figure below.

BC\Yt Y Y

0 0 0 0 1 1 1 1

0 0 0 0 X

1 1 1 1 X

B 1 1 1 1

B 0 0 0 0

1 1 1 1 0 0 0 0

t t A=0(A’) A=1(A)

a)

BC\Yt Y Y

0 1 1 1 0 1 1 0

0 1 1 0 X

1 1 1 0 X

B 0 0 0 0

B 0 0 0 0

0 0 0 0 0 0 0 0

t t

A=0(A’) A=1(A)

b)

Table 5. State Table with D Flip-flops

Table 6. Maps for a) A’ and b) B’

9

Obtained Boolean functions for A’ and B’ are:

Eq. 2

*( ) * ,( ) ( ) - + + Eq. 3

Next is the design for the Output Combinational Logic. It was done by mapping truth tables of

R1, O1, G1, R2, O2, and G2 from Table 2 on two-variable maps as shown in Table 7.

B

0 0

A 1 1

Map for R1

B

0 1

A 0 0

Map for Y1

B

1 0

A 0 0

Map for G1

B

1 1

A 0 0

Map for R2

B

0 0

A 0 1

Map for Y2

B

0 0

A 1 0

Map for G2

The outputs are functions of only the present states A and B. Output Boolean functions are:

Eq. 5

Eq. 6

Eq. 7

Eq. 8

Eq. 9

Eq. 10

Table 7. Maps for Output Combinational Logic

10

Now that each networks for the individual part of the design are established, putting them into a

single diagram follows. Figure 5 shows the interconnection of the clock, fifteen seconds timer, next state

combinational logic circuit, state registers and finally, the output circuit. In addition to the afore-

mentioned task of each part, note that the outputs of the flip-flops A and B were set as inputs to the input

combinational logic. X and Y inputs are connected into switches 1 and 2. Here, X and Y are high if

individual switches are closed, that is a car is present on the road. The output of the fifteen seconds timer

was connected to the input. It was desired that the Four Bit Binary Counter will reset if either Y1 or Y2

is high which was achieved by ORing them and connecting the output to the reset input of the counter.

Figure 4. Final Circuit (One-way Road Intersection Traffic Light)

11

Results

The final design was implemented in a simulation program NI Multisim™ where the behavior of

the circuit was then observed. Example simulation images are presented in Appendix B. The simulation

timing diagram is shown in Figure 10. By the moment the circuit runs, the fifteen seconds timer starts

automatically. Y1 and Y2 control the state of the timer by the way of resetting it. Since the timer is

negative edge-triggered, it changes state during the negative edge of the clock. States of inputs X and Y

are arbitrarily chosen all over the trace. These in turn determines the next state of the state registers A and

B which are considered initially reset. Considering every positive edge of the clock, the next states of the

registers are determined by taking into account the states of the registers and inputs at a time just before

←3sec→

C

t

(timer)

X

Y

A

B

R1

Y1

G1

R2

Y2

G2

Figure 5. Simulation Timing Diagram

12

the clock changes state. Note that the positive edges of the clock are considered because the registers used

are positive edge-triggered.

For the first positive edge, both registers and the three inputs are all reset. Thus referring to the

state table of Table 5, the registers remain in its state. At the second positive edge, inputs X, Y and t has

its values as 0, 1 and 0, respectively. Thus again referring to Table 5, registers A and B changes states to 0

and 1, respectively. Here, set states are Y1 and R2. Corresponding to that, the fifteen-second timer is

reset for the whole interval of the present state. It starts counting when the orange light in the previous

state goes low. The above mentioned process will continue following the states of X and Y as indicated.

CONCLUSION

The one-way traffic system was designed and developed successfully. The circuit’s behavior

affirms to the designers’ specification thus clearly implying that the sensors are synchronized with the

whole process of the traffic design and that the light transitions respond well with the sensors. The time of

occurrence of each state transition has met the expected time.

Minor discrepancies were encountered during the process which can be avoided by taking into

consideration every minute detail of the design specifically the interconnections of various networks.

The one-way traffic system is still subject to essential improvement since it was only

implemented for design purposes only and to stress out one of the vital applications of logic circuit and

digital electronics in the real world. It is not opt to be carried out for actual use considering that advanced

technologies are much preferred to use such as microcontrollers which operate more satisfactorily,

nowadays.

I

Clock Design

Procedure

Appendix

A

II

IC type lm555 is a precision timer circuit whose internal logic is shown in Figure A1. This is an

IC timer unit that produces clock pulses at a given frequency. The circuit requires a connection of two

external resistors and two external capacitors. Figure A1 shows the external connections for astable

operation of the circuit. Capacitor charges through resistors and when the transistor is forward

biased and conducting. When the charging voltage across capacitor reaches 3.3 V, the threshold input at

pin 6 causes the flip-flop to reset and transistor turns on. When the discharging voltage reaches 1.7 V, the

trigger input at pin 2 causes the flip-flop to set and transistor turns off. Thus, the output continually

alternates between two voltage levels at the output of the flip-flop. The output remains high for a duration

equal to the charge time. This duration is determined from the equation:

( ) Eq. A1

Figure A1. IC type LM555 timer connected as a clock pulse generator

III

The Output remains low for a duration equal to the discharge time. This duration is determined

from the equation:

Eq. A2

It was desired to generate a square wave with a period of 3s. The frequency corresponding to that

is 0.333Hz. Also, the duty of the square wave was chosen to be 66.67%. That is the signal is high for two-

thirds a period and is low for one-thirds a period. Desired waveform is shown in Figure A2.

Letting C be and using Eq. A2,

( )

Using this obtained value and Eq. A1,

( )( )

1s

3s

Figure A2. Output waveform for clock generator

IV

The final circuit is constructed as shown Figure A3.

This circuit was used in the design as an input clock source to the state registers and binary

counter.

Figure A3. Astable oscillator operating at a period of 3 seconds

V

Multisim™ Simulations

Screenshots

Appendix

B

VI

Figure B1. Oscilloscope connected to the output of the clock and output of the fifteen-second timer

Figure B2. Example trace for the oscilloscope of Figure B1

VII

Figure B3. Probes are used in deriving the states of Figure 5

VIII

Figure B4. Traffic lights and switch sensors configured forming road intersection

IX

References

Digital Design (4th Edition) - M. Morris Mano and Michael D. Ciletti

Design and Development of Sensor Based Traffic Light System - A. Albagul, M. Hrairi, Wahyudi and

M.F. Hidayathullah

Lecture 10: A Design Example - Traffic Lights Department of Computing, Imperial College London

DOC 112 Computer Hardware

http://en.wikipedia.org/w/index.php?title=Special:RecentChanges&feed=atom

http://auto.howstuffworks.com/car-driving-safety/safety-regulatory-devices/question234.htm