on-wafer probing best practices for power electronics...test system probing system discharge circuit...

16
On-Wafer Probing Best Practices for Power Electronics Michael Lyman Market Development Manager August 2014 GSA Working Group

Upload: others

Post on 02-Aug-2020

1 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

On-Wafer Probing Best Practices for Power Electronics

Michael Lyman Market Development Manager August 2014 GSA Working Group

Page 2: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

Agenda

Market drivers & trends MOSFET vs. IGBT device test & yield challenges Differing substrate materials Thinned/warped wafers & handling Arcing prevention for high-voltage testing Wafer interface options Chuck contact resistance minimization Safety (system, device, operator) Test-cell integration.

August 22, 2014

Page 3: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

Power device production wafer-level test Much faster than individual package test

Save time and $ by not testing bad die

Save $$ by not packaging bad die

Identify process excursions real-time. Potential to save $$$!

Use to sort/bin while at the wafer level

Wafer–Level Test Advantages

August 22, 2014

Page 4: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

Market Drivers & Trends

August 22, 2014

https://www.furukawa.co.jp/english/museum/floor3/04/10.htm

(USD 9.8B) (USD 3.9B) (USD 2.0B)

Time-to-Market Cost Customer quality demands (automotive, grid, etc.)

Page 5: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

MOSFET vs. IGBT Device Test & Yield Challenges

Yield – MOSFET:

Relatively low-power Small die = many die on wafer Volume yield absorption Thorough & “easy” package test

– IGBT High-power Large die = few die on wafer Greater performance therefore test

sensitivity Greater yield sensitivity

August 22, 2014

Page 6: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

Power Electronics Substrate Challenges

Si, GaN, GaN on Si(?), SiC

August 22, 2014

• 3yr: GaN $$ < Si • In production for low-voltage

applications now

High-End Solutions

Mid-Range Solutions

Low-End Solutions

600V 1,000V 1,800V+

Page 7: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

Thinned & Warped Wafers

Some magic is required: – Handling – Vision – Vacuum/Cres/release

August 22, 2014

Page 8: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

Arcing

Dft – Die size, pad distance, scribe line pathways,

passivation, neighbor die potential System

– System-level arcing prevention Design considerations Shielding Grounding

August 22, 2014

Page 9: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

Wafer Interface

Probe-based – Fluid-based anti-arcing

Works, but messy on many levels

Probe-Card-based – Pressure-based anti-arcing

Pressure chamber covers entire DUT die and high electric field area

Increase pressure inside chamber, increase air breakdown voltage from DUT to adjacent dies

Additional pressure also decreases chuck/wafer resistivity

August 22, 2014

V= voltage d=distance a/b = environmental p= pressure

Paschen’s Law:

Air bearing

Air chamber

Page 10: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

Chuck Interface Resistance

August 22, 2014

MicroVac™ High-Power Chuck 10.5 kV DC(coax mode), 400 A

(pulse) Typical is 5 mΩ resistance 500 vacuum holes with 100 - 300

µm diameter for thin-wafer handling down to ≤ 50 µm

Independently-controlled vacuum lines for 3”,4”,6” and 8” wafers; conventional and Taiko wafer support

Some more magic is needed…

Page 11: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

Safety

Operator Safety Device Safety Integrated Test Cell

Safety

August 22, 2014

HV moduleSW

LV module

LV module

Test instrumentBreeder resistor

Discharge Switch

High voltage chuck

Test system Discharge circuitProbing system

< 5 msec discharge time

Applicable standards: – CAN/CSA C22.2 No 61010

- 1/R: 2009 – UL 61010 - 1/R: 2008-10 – EN 61010 - 1: 2001 – EN 61326:2006 – EN61000 - 3 - 3: 2008 – FCC 15.109(g): 2012 – CISPR 22:1997 Class A – FCC 15.107: 2012 Class A – SEMI S2 - 0703 – SEMI S8 - 0701

Die to die

Time

N+2th die

N+1th dieNth die N+4th

dieN+3th die

Test complete

Die sequence

ON Discharge

OFF

Dis

-cha

rge

Dis

-cha

rge

Dis

-cha

rge

Dis

-cha

rge

Dis

-cha

rge

Page 12: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

Test Cell Integration

#1 request – it’s painful! – Somewhat “greenfield” application space & solutions

Complex & often unique interfaces – Cabling, connectors, etc. – Application-specific testers

Safety integration Test Executive

– Prober as Master or Slave? – Facility integration

Host, other databases, etc.

August 22, 2014

Page 13: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

TESLA Product Family Overview (Blatant Advertising)

Power

150 mm 200 mm

300 mm

ENGINEERING Probes

APS200 TESLA

PRODUCTION

August 22, 2014

Page 14: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

THANK YOU!

Additional questions, please contact: Michael Lyman [email protected] 503-601-1501

August 22, 2014

Page 15: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

Extending system capabilities to 600 A / 10 kV

TESLA200 / 300 Update

• UHP probe for Ultra High Power capability

• New chucks with advanced current handling capability

Available June ‘14

August 22, 2014

Page 16: On-Wafer Probing Best Practices for Power Electronics...Test system Probing system Discharge circuit < 5 msec discharge time Applicable standards: – CAN/CSA C22.2 No 61010 - 1/R:

Unique probe to allow testing High Voltage (10 kV) and High Current (300 A) all in one

Allows parallel configuration for 600 A

1 - 12 tines comb to address different pad sizes and test currents

Durable comb design for >100,000 touchdowns

Field replaceable comb

<2 mΩ low contact resistance, >10 TΩ insulation resistance

Ultra High Power Probe

August 22, 2014