On the Relation On the Relation Between Between

Simulation-based Simulation-based and SAT-based and SAT-based

DiagnosisDiagnosisCMPE 58QCMPE 58Q

Giray KömürcüGiray Kömürcü

Boğaziçi UniversityBoğaziçi University

Is it Possible to Design a Circuit with thousands, Is it Possible to Design a Circuit with thousands, millions, billions of transistors without even a millions, billions of transistors without even a

Single Error? Single Error?

Where is the error within the whole Design?Where is the error within the whole Design?

OutlineOutline What is Error Diagnosis?What is Error Diagnosis? Diagnosis ApproachesDiagnosis Approaches Simulation Based DiagnosisSimulation Based Diagnosis SAT-based DiagnosisSAT-based Diagnosis Relation Between the ApproachesRelation Between the Approaches Comparison of the ApproachesComparison of the Approaches Case StudyCase Study ConclusionConclusion

Error Diagnosis is...Error Diagnosis is...

Locating the source of an error or faultLocating the source of an error or fault If an Error exists, it should be diagnosed and If an Error exists, it should be diagnosed and

corrected!corrected! Several Automated ApproachesSeveral Automated Approaches

Diagnosis ApproachesDiagnosis Approaches Manual Error Diagnosis is very time consuming Manual Error Diagnosis is very time consuming

and challenging with increasing complexity of and challenging with increasing complexity of designsdesigns

Structural ApproachesStructural Approaches Rely on similarities between the specification and the Rely on similarities between the specification and the

implementationimplementation Fails with optimizations in the synthesisFails with optimizations in the synthesis

Binary Decision Diagram-based Approaches Binary Decision Diagram-based Approaches Defines circuit as graphsDefines circuit as graphs Suffer from space complexity issuesSuffer from space complexity issues

Test-Vector Based ApproachesTest-Vector Based Approaches Simulation basedSimulation based Boolean Satisfiability (SAT) basedBoolean Satisfiability (SAT) based

Basic DefinitionsBasic Definitions•Error is Functional mismathes Error is Functional mismathes between the specification and the between the specification and the implementationimplementation

•Manual design ErrorManual design Error

•Complex Circuits + CAD tools Complex Circuits + CAD tools Error Error

Basic DefinitionsBasic Definitions

Test Vector Let the circuit I be a faulty implementation of

a specification. A test T is a triple (t,o,v), where

t= test vector in terms of primary input values of I and causes erroneous value at the primary output

o= erroneous output value at the primary output

v= correct output value for primary output t=[1,0,1]; o=1; v=0

Basic DefinitionsBasic Definitions

Diagnosis problem Let the circuit I be a faulty implementation of

a specification and let T be a test-set of m tests.

Diagnosis problem is to determine a set of candidate gates C={g1,..,gc} where a correction can be applied to rectify the tests in T

Simulation and SAT based Simulation and SAT based ApproachesApproaches

Use a set of Test VectorsUse a set of Test Vectors Can be applied to both Combinational and Can be applied to both Combinational and

Sequential CircuitsSequential Circuits Robust with large designsRobust with large designs

Simulation Based Simulation Based DiagnosisDiagnosis

Definition: “Controlling Value” A ‘Value’ at an input of

a logic function is ‘Controlling’ if the output value of the logic changes when that input value complemented

E.g: Both inputs of an XOR gate is controlling value since any change at the inputs complements the output

IN 1 IN 2 OUT

0 0 0

0 1 1

1 0 1

1 1 0

Simulation Based Simulation Based Diagnosis (2)Diagnosis (2)

Path Trace AlgorithmPath Trace Algorithm For all vector set:For all vector set:

Simulate t to establish values of internal Simulate t to establish values of internal signalssignals

Mark the gate with the erroneous primary Mark the gate with the erroneous primary outputoutput

For each marked gateFor each marked gate Mark the inputs with controlling valueMark the inputs with controlling value Mark all inputs if no controlling valueMark all inputs if no controlling value

Each marked net is a candidate setEach marked net is a candidate set

Simulation Based Simulation Based Diagnosis (3)Diagnosis (3)

Interpretation of the diagnosis result depends on Interpretation of the diagnosis result depends on the number of errorsthe number of errors

Single error is diagnosed via the intersection of Single error is diagnosed via the intersection of candidate setscandidate sets

For Multiple errors number of errors are For Multiple errors number of errors are consideredconsidered

After correcting each error re calculate the test After correcting each error re calculate the test setset

There is no guarantee that the decisions are There is no guarantee that the decisions are definitely correctdefinitely correct

Back track ability is requiredBack track ability is required For basic approach solution is not guaranteedFor basic approach solution is not guaranteed

SAT-Based DiagnosisSAT-Based Diagnosis SAT instance is generatedSAT instance is generated

A copy of circuit is created for each test in the A copy of circuit is created for each test in the SAT instanceSAT instance

Circuit with multiplexers at gates to allow Circuit with multiplexers at gates to allow correctionscorrections

A correction to the gate output is applied if the A correction to the gate output is applied if the select line of the multiplexer is set to 1select line of the multiplexer is set to 1

SAT-Based Diagnosis (2)SAT-Based Diagnosis (2) BasicSATDiagnose Algorithm:BasicSATDiagnose Algorithm:

For each triple of TFor each triple of T Create an instance i of I in the SAT-instanceCreate an instance i of I in the SAT-instance Constrain o to assume the correct value vConstrain o to assume the correct value v Constrain inputs to the values of tConstrain inputs to the values of t Insert Multiplexers at gates that are Insert Multiplexers at gates that are

considered for correctionconsidered for correction For i=1 to kFor i=1 to k

Constrain the number of select-inputs with Constrain the number of select-inputs with value 1 to be at most ivalue 1 to be at most i

Enumerate all solutions and add a blocking Enumerate all solutions and add a blocking clause for each solutionclause for each solution

SAT-Based Diagnosis (3)SAT-Based Diagnosis (3) SAT solver is used to solve the SAT instanceSAT solver is used to solve the SAT instance Select lines of MUXes are the free variablesSelect lines of MUXes are the free variables Each solution set of free variables is a solution to Each solution set of free variables is a solution to

diagnosis problemdiagnosis problem Number of error limit is increased iteratively to Number of error limit is increased iteratively to

get the minimum number of correctionsget the minimum number of corrections This is called Basic SAT approach (BSAT)This is called Basic SAT approach (BSAT)

Advanced SAT-Based Advanced SAT-Based DiagnosisDiagnosis

Applies several heuristics to improve the Applies several heuristics to improve the performance of BSATperformance of BSAT

Algorithms to reduce the search spaceAlgorithms to reduce the search space Test sets are split into smaller ones to reduce the Test sets are split into smaller ones to reduce the

size of the SAT instancesize of the SAT instance Techniques do not change the solution space but Techniques do not change the solution space but

reduces the run timereduces the run time

Comparison of the Comparison of the ApproachesApproaches

Number of candidate Error Sites: Large in BSIM, Number of candidate Error Sites: Large in BSIM, k candidates in BSATk candidates in BSAT

Ability to return valid corrections:Ability to return valid corrections: BSAT, Advanced BSIM and Advanced BSAT BSAT, Advanced BSIM and Advanced BSAT

approaches return valid correctionsapproaches return valid corrections BSIM does not guarantee to find the valid BSIM does not guarantee to find the valid

correctionscorrections BSIM guide the designer to locate the errorBSIM guide the designer to locate the error

Comparison of the Comparison of the ApproachesApproaches

Effect AnalysisEffect Analysis Done inherently by the BSAT diagnosisDone inherently by the BSAT diagnosis Advanced Simulation techniques carry out via Advanced Simulation techniques carry out via

re-simulationre-simulation Structural InformationStructural Information

May be used by simulation techniquesMay be used by simulation techniques Advanced BSAT techniques use to prune the Advanced BSAT techniques use to prune the

search spacesearch space

Comparison of the Comparison of the ApproachesApproaches

|I|=Size of the Circuit m= number of Tests k= number of Errors Simulation engine is a crucial issue due to large Simulation engine is a crucial issue due to large

number of tests and complex circuitsnumber of tests and complex circuits BSIM has a linear time complexity O(|I|*m) BSAT has exponential complexity of O(2|I|*m*2+|I|+l)

Comparison of the Comparison of the ApproachesApproaches

Space complexity of BSIM is smallest, Space complexity of BSIM is smallest, Each test can be applied independently Each test can be applied independently O(|I| + m)

For BSAT circuit is stored for each test up For BSAT circuit is stored for each test up to depth of k search level to depth of k search level O(k*|I|*m)

Runtime of the Basic Runtime of the Basic ApproachesApproaches

*BSAT guarantees a valid correction

Quality of Basic Quality of Basic ApproachesApproaches

BSAT is slower but returns by far the best results

Even simple approaches have good quality and helps the designer

CASE STUDY: CASE STUDY: Error Diagnosis in Equivalence

Checking ofHigh Performance Microprocessors

Equivalence checking of RTL and transistor level models of high performance microprocessors

Error Diagnosis via Simulation Based Techniques

CASE STUDYCASE STUDY Gate level models are used rather than transistor level

models in error diagnosis of microprocessors by the previous approaches

Due to performance constraints custom logic is used (Self timed components, dynamic logic vs.)

Boolean model extraction tools can not be used The model described captures transistor level

dynamic behavior Counts bidirectional transistors, charge sharing and

different transistor strengths Signal timing and transistor strengths may also cause

errors error diagnosis becomes even more challenging

CASE STUDYCASE STUDY Equivalence Checking is done by Symbolic

Trajectory Evaluation (STE) between RTL and transistor level models

Formal verifcation technique Combines symbolic simulation with ternary

simulation. 0, 1, X values are used0, 1, X values are used Verification is done via assertions as Verification is done via assertions as “antecedent

implies consequent” Generated Automatically from the RTL Model

CASE STUDYCASE STUDY Counter Examples are generated for assertions

that fail Characteristics of Error Diagnosis

Small Number of Error Locations Fast Contains Actual Error Locations

CASE STUDYCASE STUDY PathBacktrace(nd):Input: Comparison node, counter example, implementationOutput: Diagnosis nodes in Controlling list

If nd is input or is already processed then returnCompute excitation function F for nd from transistor levelfor every node x in support of F

if x is controlling then add x to Controlling list L, if not already added

end forif L=[ ] then PathBacktrace(y) for all nodes y in support of Felse choose a node y in L and PathBacktrace(y)

Path Trace Example

a

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Specification

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Controlling= [b; g; d; a; e; f; h]

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ControllingNode

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Controlling= [b; c; g; e; f; h]

[b]e[c]g[g]h[e]f [f; h]out

ControllingNode

PathBacktrace = [b; e; g; h; f]

CASE STUDYCASE STUDY Complemention is appliedComplemention is applied

Scalar forward simulation of design Applied to nodes generated by Path Backtrace Checks if changing the value of the node is

observable at the output Reduces the number of error locations Reduces the debugging and verification time

Complementation Examplea

b

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Complement out Changed?f =0 no h=0 nog=0 noe=0 yesb=1 yes

PathBacktrace = [b; e; g; h; f] Complementation= [b; e]

01

0

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00

0

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1

CONCLUSIONCONCLUSION Error Diagnosis is a major step in the design Error Diagnosis is a major step in the design

process of Microelectronic Circuitsprocess of Microelectronic Circuits Automated Diagnosis Approaches are usedAutomated Diagnosis Approaches are used Simulation based approaches are faster and Simulation based approaches are faster and

needs less resources but has limited help to needs less resources but has limited help to the designerthe designer

SAT-Based approaches are slower but SAT-Based approaches are slower but guarantees the solution guarantees the solution

An application of Simulation based techniques An application of Simulation based techniques is presentedis presented

We presented automated techniques to find We presented automated techniques to find errors in the circuit designs that will reduce errors in the circuit designs that will reduce the design cyclethe design cycle

REFERENCESREFERENCES - On the relation between simulation-based and - On the relation between simulation-based and

sat-based diagnosis, G. Roy, S. Safarpour sat-based diagnosis, G. Roy, S. Safarpour - Error Diagnosis in Equivalence Checking of - Error Diagnosis in Equivalence Checking of

High Performance Microprocessors, Alper Sen High Performance Microprocessors, Alper Sen - Design Error Diagnosis and Correction via test - Design Error Diagnosis and Correction via test

Vector Simulation, A. Veneris et al. Vector Simulation, A. Veneris et al.

QUESTIONS?QUESTIONS?