on the punchthrough phenomenon in submicron mos transistors

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 5, MAY 1997 847

On the Punchthrough Phenomenonin Submicron MOS Transistors

Kuan-Yu Fu and Yuk L. Tsang

Abstract—As the channel length of MOS transistors reducesto the submicron dimension, the punchthrough becomes moreof a surface-initiated and gate-controlled phenomenon. A sur-face diffusion current (Isdif) originates from the injection ofminority carriers from the source junction due to the combinedeffect of drain-induced-barrier-lowering (DIBL) and surface-band-bending (��so). The DIBL effect increases rapidly withdecreasing channel length. In addition, the extracted��so fromthe punchthrough current indicates that surface space chargesat the source edge shift from the accumulation/depletion modefor long submicron devices (� 0.62 �m) to the strong-inversionmode for deep submicron devices (� 0.12�m). In general, Isdifdominates over the low drain bias range and eventually convertsto the bulk space-charge-limited current (Iscl) as the drain biasincreases and the source/drain depletion regions connect. Thedrain bias for this conversion to occur strongly depends on thechannel dimension. Only intermediate submicron devices (� 0.37�m) in this study clearly show both the surface and bulk (space-charge-limited) punchthrough components. For long submicrondevices, Isdif essentially dominates, while for deep submicrondevices, it converts rapidly to Iscl over the drain bias rangeinvestigated. A semi-empirical closed form equation is proposedto describe bothIsdif and Iscl and their merging over the entirerange of drain bias. The punchthrough current simulated fromthis equation shows an excellent agreement with the experimentaldata.

I. INTRODUCTION

T HE WELL-KNOWN punchthrough phenomenon in MOStransistors has been a major obstacle for microelectronics

miniaturization scaling. The phenomenon is generally consid-ered a bulk-dominated effect [1]–[9]. Technologies and devicemodeling proposed to suppress or understand this phenomenonhave been mostly based on this concept [10]–[14]. Troutman[15] and Greenfield [16] have considered the possibility of asurface mechanism for the punchthrough. For short-channeltransistors ( 1 m in the channel length), it has beenshown by Eitan and Frohman–Bentchkowsky [17] that thepunchthrough phenomenon can indeed be initiated at thesurface as a diffusion current from minority carriers at lowdrain biases (Region I in Fig. 1). The minority carriers areinjected due to the barrier lowering at the source junctionby the drain field and the band-bending under the effect ofthe gate-induced surface space charges. At high drain biases,the punchthrough current becomes leveled due to bulk space-charge limitation (Region III in Fig. 1). Between these two

Manuscript received August 19, 1996; revised December 19, 1996. Thereview of this paper was arranged by Editor G. W. Neudeck.

K.-Y. Fu is with the AMCU Memory and Technology Group, Semiconduc-tor Products Sector, Motorola, Inc., Austin, TX 78735 USA.

Y. L. Tsang is with APRDL, Motorola, Inc., Austin, TX 78721 USA.Publisher Item Identifier S 0018-9383(97)03010-4.

Fig. 1. A typical I�V characteristic of short-channel(� 1 �m) MOStransistor.

extreme regions, it is reported that there is a steep increase ofthe current (Region II in Fig. 1) which corresponds to a bulk-dominated component. The onset of a surface punchthroughoccurring at a lower drain bias than the bulk componentcan be explained in terms of an energy band diagram asillustrated in Fig. 2. In the bulk, the incremental drain biasincreases the width of the drain depletion region and themaximum lateral electric field. However, the minority carrierinjection can occur only when the source barrier is loweredafter the drain/source depletion regions connect [Curve (2)in Fig. 2(a)]. On the other hand, at the surface, loweringof the source barrier is possible due to the extension ofthe lateral field toward the source junction through the gate-induced surface depletion region. This effect is enhanced by ashorter physical dimension between the source and drain anda lower impurity concentration at the surface. The low-levelinjection thus starts at lower drain biases [Curves (1) and (2) inFig. 2(b)], lower than required for joining the bulk depletionregions. According to [17], the surface and bulk punchthroughcurrent components can be experimentally differentiated bytheir different sensitivities to gate and substrate biases (and ; see, for example, the different sensitivities of thepunchthrough current to in Regions I and II in Fig. 1).

To the best of our knowledge, there has been no studyreported on how these different punchthrough current com-ponents behave in submicron 1 m MOS devices. Inorder to obtain a better understanding of the surface and

0018–9383/97$10.00 1997 IEEE

848 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 5, MAY 1997

(a)

(b)

Fig. 2. A schematic band diagram in a cross section between the source anddrain for a PMOS transistor (a) in the bulk region, and (b) in the surfacedepletion region.

bulk punchthrough effects for submicron MOS transistors, thepunchthrough current in devices with the effective channellength less than 1 m, down to 0.12 m, is measured notonly for various gate and substrate biases but also for varioustemperatures. A preliminary and brief report based on thisstudy has been published [18]. The present paper is a moredetailed and extensive report of the work.

In Section II, a brief theoretical review of the surfacediffusion current and the bulk space-charge-limited current ispresented. The bulk punchthrough current as reported in [17] isnot considered in this review because it will be shown that itscontribution to the punchthrough in submicron devices underthis study is almost negligible. In Section III, the experimentand result from this study are discussed. The section is di-vided into subsections in which different experimental aspectsare presented. The dependency of the punchthrough currenton the channel dimension, temperature, gate and substratebiases are discussed in detail. Parameters which characterizethe drain-induced-barrier-lowering (DIBL) and surface-band-bending effects are extracted based on experimental data byapplying the theoretical equations described in Section II. Ingeneral, it is found that the punchthrough becomes more of asurface-initiated and gate-controlled phenomenon as the devicedimension reduces to the deep submicron regime. A semi-empirical closed form equation is proposed in Section IVto accurately predict the punchthrough current for submicrondevices, which is essentially combined from a surface diffu-sion component and a bulk space-charge-limited component.Finally, the paper is concluded with a summary in Section V.

II. THEORETICAL REVIEW

The subthreshold surface diffusion current for a givenchannel length at its saturation level V)can be theoretically expressed as [19]

(1)

where most notations have their usual meanings,is thesurface diffusion constant of minority carriers and isthe intrinsic carrier concentration. According to [20], theparameter can be decomposed into

(2)

where , a function of and , is the surface-band-bending and , a dimensionless constant with strongdependency on the device geometry, characterizes the degreeof the DIBL effect. Equation (1) can be rewritten in thefollowing simple form:

(3)

where is basically a drain-bias-independent coefficientwhich is itself proportional to exp with

representing the Si energy band gap.The space-charge-limited current density in theory can

be solved numerically for devices of a given channel length[21] with the effect of field-dependent drift velocity beingincluded. For the case where the cross section of depletionregions is fixed, a typical characteristic for shouldfollow a power law of , with a power index changing from 2(for unsaturated drift velocity) to 1 (for saturated drift velocitywhich leads to a current density of where isthe saturated drift velocity [21]). It will be shown that thispower index range cannot account for the behavior of allsubmicron MOSFET’s.

III. EXPERIMENT, RESULT, AND DISCUSSION

The devices used in this study are surface-channel PMOStransistors with submicron channel length of 0.62m, 0.37

m, and 0.12 m (hereinafter referred to as long, intermediate,and deep submicron, respectively, in this paper) and withLightly-Doped Drain (LDD) having a gate oxide thicknessof 150 A. The source/drain junction depth is 0.3 m witha doping concentration in the order of cm andthe LDD is 0.25 m deep with a doping concentration of

cm The average bulk doping concentration isapproximately cm For long, intermediate, anddeep submicron transistors, the threshold voltages are0.82V, 0.72 V, and 0.34 V, respectively. The subthresholdsource currents versus the drain bias are measured forvarious gate V V and substrate V

V biases in a temperature range varying from 25C to150 C with an increment of 25 C In order to minimizepossible charge injection into the oxide which may affect thesubsequent measurement, the drain bias is limited to 10 V,8 V, and 3.5 V for long, intermediate, and deep sub-microndevices, respectively. The measured result will be summarizedand discussed below.

FU AND TSANG: PUNCHTHROUGH PHENOMENON IN SUBMICRON MOS TRANSISTORS 849

A. An Overview of Typical DevicePunchthrough I–V Characteristic

Typical characteristic of source current versus drain biasmeasured at V and V for different

temperatures are shown in Figs. 3–5 for long, intermediate,and deep submicron devices, respectively. For long submicrondevices (Fig. 3), the source current exponentially depends on

and its magnitude increases with the temperature overthe drain bias range investigated. For intermediate submicrondevices (Fig. 4), the exponential dependency occurs over asmaller drain bias range (from 0 V to3 V), when comparedto that for long submicron devices. At higher drain biases,the current no longer follows an exponential law but convertsmore closely to a power law dependency on Note thatthe transition between these two regions is in general smoothand the steep increase of the current (corresponding to theonset of bulk punchthrough) in between as reported in [17] ismissing here. The reason for the disappearance of this bulk-initiated punch-through region will be explained in SectionIII-D). The dependency of the characteristic on thetemperature as shown in Fig. 4 is less sensitive than those forlong submicron devices as shown in Fig. 3. This, as will beshown later, is essentially due to a larger surface-band-bendingfor shorter channel devices. Actually, the characteristicof different temperatures for intermediate submicron devicestend to converge together at a certain drain bias7 V).For deep submicron devices (Fig. 5), both the exponentialdependency as well as the temperature sensitivity of the sourcecurrent at low drain biases become almost un-noticeable as thecurrent magnitude is increased to an even higher level. Thisprobably is a direct result of the low bulk doping concentration

cm in the devices used in this study. If a heavierbulk concentration is used, a more noticeable exponential

dependency and temperature sensitivity in the sourcecurrent is expected to exist. Over most of the drain bias rangeinvestigated as shown in Fig. 5, the characteristicessentially follows a power law. Note that the power lawindices for deep submicron devices as shown in Fig. 5 are ingeneral much smaller than those for intermediate submicrondevices as shown in Fig. 4.

B. The Surface Diffusion Current,

As mentioned in Section III-A, the characteristicfollows an exponential dependency over most of the drainbias range investigated for long submicron devices and overthe low drain bias range (0–3 V) for intermediate submicrondevices at V. Since it is believed that thisexponential dependency is represented by a surface diffusioncurrent as described in Section II, the experimentaldata are thus fit to a functional form of (3) over most of thedrain bias range investigated for the long submicron device andover the low drain bias range for the intermediate submicrondevice for each temperature. It is expected that the resulting

is proportional to exp as shownin (3).

The extracted parameter for each temperature as indicatedin Figs. 3 and 4 using (3) is shown in Table I. As one can

Fig. 3. The punchthroughI�V characteristic of LDD P-channel MOStransistor forVgs = 0 V andVbs = 0 V with the temperature varying from25 �C to 150�C: The effective channel length is 0.62�m (long submicron).

Fig. 4. The punchthroughI�V characteristic of LDD P-channel MOStransistor forVgs = 0 V and Vbs = 0 V with the temperature varyingfrom 25�C to 150�C: The effective channel length is 0.37�m (intermediatesubmicron). The prediction by using (4) is also shown for comparison.

see that it increases roughly by a factor of 3–4 from longto intermediate submicron devices, indicating a rapid increaseof DIBL effect with decreasing channel length for submicrondevices. There is a slight decrease of(smaller slope of the

characteristic in Figs. 3 and 4) whenincreases from25 C to 150 C for a given channel length. The reason forthis will be explained in the Section III-C.

The parameter extracted from data is indeed found toexponentially depend on as suggested by theory. Theslope of versus is thus determined as shownin Fig. 6 which yields a value of at 0.08 eV for the longsubmicron device and 0.38 eV for the intermediate submicrondevice at V and V. This result is summarizedin Fig. 7, together with other extractable result from otherbias combinations. Note that a larger surface-band-bending notonly implies a higher injection of minority carriers but alsoa less sensitivity, or less spread out, of curves versus


TABLE ITHE EXPERIMENTALLY EXTRACTED PARAMETERS m AND n VERSUS THE GATE AND

SUBSTRATE BIASES FOR DEVICES OF THREE DIFFERENT EFFECTIVE CHANNEL LENGTHS

Fig. 5. The punchthroughI�V characteristic of LDD P-channel MOStransistor forVgs = 0 V andVbs = 0 V with the temperature varying from25 �C to 150�C: The effective channel length is 0.12�m (deep submicron).

the temperature. For comparison, the theoretical prediction ofversus at is also shown in Fig. 7 by using a

constant doping of cm and assuming no flat bandshift and no short-channel effect. Note that the experimentallyextracted result, as supplemented by the theoretical curve inFig. 7, imply that the surface space charges near the sourceedge is in the depletion mode for long submicron devicesand in the weak-inversion mode for intermediate submicrondevices. For deep submicron devices, as mentioned in SectionIII-A, the exponential dependency of on is almost un-noticeable. It is believed that in fact it occurs over the firstfew tenth volts of due to a much higher injected minoritycarrier density. The parameters and are thereforenot extracted from the experimental data (data are obtainedwith a 0.1 V increment in ) in this case. However, it

Fig. 6. An Arrehnius plot forIsdifo versus 1=kT to extract the sur-face-band-bending potentials,��so, for long and intermediate submicrondevices atVgs = Vbs = 0 V.

is obvious that their values should further increase and thecorresponding surface space charges should most likely shiftinto the strong-inversion mode.

C. The Bulk Space-Charge-Limited Current,

As mentioned in Section III-A, the characteristicfollows a power law dependency over the high drain bias

3 V) for intermediate submicron devices and over mostof the drain bias range investigated for deep submicron devicesat V. Their characteristic are thereforefit to a functional form of over the correspondingdrain bias ranges. The extractedvalue at high drain biasesfor intermediate submicron devices is found to vary from 6.85to 3.52 as increases from 25C to 150 C This is beyondthe theoretical range of 1 to 2 for of a fixed cross section


Fig. 7. The surface band-bending potentials,��so, extracted from theIs � Vds data with hollow symbols for various gate biases atVbs = 0 Vand solid symbols for various substrate biases atVgs = 0 V. The theoreticalcurve is obtained for long-channel devices assuming no flat band shift.

as mentioned in Section II. This large discrepancy is believedto be due to the following. As the drain bias increases, thesource/drain depletion regions become joined (when2–3 V) which allows carriers to move away from the surfaceand spread into the bulk depletion region. However, as thedrain bias keeps increasing the two depletion regions continueto join “harder” and the connecting cross section expands.Thus, the punchthrough current increases at a much higherrate than that of the theoretical power law that assumes afixed cross section. The exact dynamics of this process cannotbe fully quantified in this simple picture, but the depth of thespace charge region is estimated to expand from a surfacelayer of less than 100A down to a depth deeper than thejunction depth 0.25 m In switching from surface to bulktransport, the higher bulk carrier mobility and the expandingcross section coupled with the increasing drain bias couldaccount for the increase of by approximately three ordersof magnitude. Note that the configuration of depletion regionis most likely to be independent of temperature. Therefore itseems that the punchthrough currents at different temperaturestend to converge to the same point7 V from Fig. 4). Thisrequires the current to increase faster, and thus higher powerindices for lower temperatures. The carrier mobility, however,is higher for lower temperatures. As a result the punchthroughcurrent at lower temperatures will eventually overtake thoseat higher temperatures for higher drain biases. The conversionprocess from to takes place in the first few tenthVolts of drain bias for deep sub-micron devices. This not onlyreduces the power index for to 1–2 which is well withinthe theoretically predicted range (as the expansion of bulkdepletion region quickly saturates with the increasing drainbias) but also causes the punchthrough currents to becomeless temperature dependent over most of the drain bias rangeinvestigated. An explanation for the decrease of the extracted

values with the increasing temperature, as mentioned inthe previous subsection, will be in order here. Note thatthe injected minority carrier density is higher at a higher

temperature, in which case the carriers initially flow nearthe surface can reach a higher value such that the currentmay become limited by the space charge effect before thebulk depletion region expands. This effectively decrease the

value extracted from a higher temperature. Thevaluein general increases with and the channel length for thereason that the surface punchthrough effect is weaker forhigher and longer channel length.

D. The Gate Bias Dependency

The characteristic are also obtained forV and 1 V at V for devices with three differentchannel lengths in this study in order to see the gate bias effecton the punchthrough phenomenon for submicron devices. Asexamples, the characteristic measured atV and V for different temperatures are shown inFigs. 8–10 for long, intermediate, and deep submicron devices,respectively. For long submicron devices as shown in Fig. 8,the current at low drain biases is in general lower thanthose for the zero gate bias. Those for 25C, 50 C, and75 C are even below the noise limits of the test system. Theslopes of versus are also smaller indicating a muchreduced DIBL effect, which is reflected in the much smallervalues as shown in Table I. This, of course, is due to the factthat a more positive gate bias tends to shift the surface spacecharges into the accumulation mode which in turn weakens theinfluence of the drain bias on the source potential barrier. Theextracted versus the gate bias as shown in Fig. 7, trackswell with the theoretical prediction for long-channel devices,indicating that the corresponding surface layers indeed shiftto the accumulation mode. This consistency provides a directvalidity of the assumption that the exponential dependency of

on can indeed be represented by the surface diffusioncurrent. It is interesting to note that even though the surfacecharges are in the accumulation mode, the injection andsurface diffusion of minority carriers are still possible for longsubmicron devices. In Fig. 8, one can see that as the drainbias increases beyond7 V, the punchthrough current startsto deviate to a higher exponential dependency. This is believedto be due to the emergence of the bulk punchthrough currentwhich eventually leads to , as observed and reported byEitan and Frohman–Bentchkowsky [17] for longer channel

1 m devices. The reason that this bulk punchthroughcomponent is not observed (or less distinguishable; actually,the deviation to the bulk punchthrough also exists at7 V inFig. 3) for the case of V in long submicrondevices is probably due to the stronger surface DIBL effectand the employment of LDD and higher bulk doping.

The same gate bias effect is also seen in the punchthroughphenomenon for intermediate and deep submicron devices asshown in Figs. 9 and 10. The current at low drain biases ingeneral shifts to a lower value while the characteristicbecome more spread apart for different temperatures (lower

) as the gate bias becomes more positive. The extractedversus the gate bias for intermediate submicron devices

as shown in Fig. 7 indicates that the surface space charges, asexpected, shift from the weak inversion mode to the depletion



Fig. 9. The punchthroughI�V characteristic of LDD P-channel MOStransistor forVgs = 1 V and Vbs = 0 V with the temperature varyingfrom 25�C to 150�C: The effective channel length is 0.37�m (intermediatesubmicron).

mode. The degree of change in current as a function of thegate bias actually decreases with the channel length as thedevice becomes more controlled by the gate. This can beseen in Table I by a decrease of 15–22% in thevalue forintermediate submicron devices, as compared to 62–65% forlong submicron devices as increases from 0 to 1 V. For thesame increase, the value is increased by 30–43% for deepsubmicron devices, as compared to 90–100% for intermediatesubmicron devices.

E. The Substrate Bias Dependency

The characteristic are also obtained forV and 1 V at V in order to see the substratebias effect on the punchthrough phenomenon for submicrondevices. As examples, the characteristic measured at

V and V for different temperatures are shownin Figs. 11–13 for long, intermediate, and deep submicron



devices, respectively. For long submicron devices, the currentat low drain biases, , disappears, evidently due to a largersource barrier as shown in Fig. 11. The bulk punchthroughcurrent, as mentioned in Section III-D, starts to arise at a drainbias of 7 V. This shows that although the punchthrough canbe initiated at the surface at this level of channel dimension,the bulk has yet a better control of this phenomenon.

The substrate bias effect on intermediate and deep sub-micron devices behaves quite differently from that on longsubmicron devices, as shown in Figs. 12 and 13. The currentin general shift slightly lower from the cases for V and

V shown in Figs. 4 and 5. This can also be seen fromthe extracted and values, as shown in Table I, and theextracted , as shown in Fig. 7, versus the substrate biasfor intermediate submicron devices. This clearly indicates thatas the device dimension reduces to the deep submicron regimethe punchthrough phenomenon becomes essentially initiated at


Fig. 12. The punchthroughI�V characteristic of LDD P-channel MOStransistor forVgs = 0 V and Vbs = 1 V with the temperature varyingfrom 25�C to 150�C: The effective channel length is 0.37�m (intermediatesubmicron).


the surface and less controlled by the bulk. In contrast to itsgate dependency, however, the extractedvalue for positivesubstrate biases from intermediate submicron devices remainsalmost constant versus the temperature (unchanging slope forthe curves in Fig. 12). This is believed to be due toa combined effect of the lower injected carrier density andtheir smaller temperature sensitivity (smaller ) at a morepositive substrate bias. The possible modulation by the spacecharge effect before the bulk depletion region expands as afunction of the temperature is thus curtailed and therefore the

value does not vary much.

IV. A SEMI-EMPIRICAL EQUATION FOR

THE PUNCHTHROUGH CURRENT

From the above discussion, it can be seen that thepunchthrough current at the extreme low and high drain biasesfor submicron devices is in the form of the low level surface

(a)

(b)

Fig. 14. A brief sketch ofIsdif (a) andIscl (b) in submicron transistors.

Fig. 15. The punchthrouhI�V characteristic as simulated by (4) and itsdecomposition intoIsdif (5) andIscl components.

diffusion current, and the high level space-charge-limitedcurrent, , respectively. The only exception is when thereis a good electrical isolation along the surface between thesource and drain junctions in the case of positive substratebiases for long submicron devices (Fig. 11). The two extremecases of the punchthrough current for submicron devices arebriefly illustrated in Fig. 14 (a) and (b). The combination ofthese two currents to form the total punchthrough current,

can be mathematically represented by a semi-empiricalanalytical formula

(4)


where is expressed by (3) and is given by

(5)

where is a constant current at which the punchthroughcurrent starts to deviate from the surface diffusion current.It is employed to assure a proper conversion to the surfacediffusion component at low drain biases. Equation (4) welldescribes the merger of the surface and bulk components ofthe punchthrough characteristic as illustrated in Fig. 15.The space-charge-limited current of a fixed cross section, asrepresented by Curve (2) in Fig. 15, is obtained by a theoreticalnumerical analysis with the effect of field-dependent driftvelocity included following the methodology as described in[21]. Note that Curve (2) follows a power law with a powerindex of 2 at low drain biases and a power index of 1 at highdrain biases. Curve (3) in Fig. 15 represents by using (5),with and being extracted from the experimental data,in which the modulation effect due to the expanding bulkdepletion region and the increasing mobility as carriers driftingdeep into the bulk is automatically included. As an example,the application of (4) to predict the punchthrough current forintermediate submicron devices is compared with experimentaldata in Fig. 4 which shows an excellent agreement. A simpleclosed form equation, such as (4), could be very usefulin simulating the punchthrough current for submicron MOSdevices.

V. SUMMARY

The punchthrough phenomenon in submicron MOS tran-sistors has been thoroughly studied. It is found that thepunchthrough current for submicron devices is initiated atthe surface near the edge of source junction due to thecombined effect of DIBL and , both of which increasewith decreasing channel length. This causes the punchthroughto become more of a surface-dominating phenomenon as thedevice dimension reduces into the deep submicron regime.Therefore, the currently popular design trend of using aretrograde channel profile to obtain a low threshold voltage,reduce the impurity scattering in the channel and suppressthe bulk punchthrough effect may not neccessarily be a gooddesign strategy for deep submicron devices. In general, atlow drain biases the punchthrough current is in the formof a surface diffusion while at high drain biases it becomesbulk-space-charge-limited. The drain bias for this conver-sion to occur decreases drastically with decreasing submicronchannel length. Therefore, only devices with an intermediatesubmicron channel length 0.37 m show clearly bothcurrent regions in this study. The higher bulk mobility coupledwith the expanding depletion cross section in the bulk asthe drain bias increases accounts for a power index higherthan the theoretical prediction for the space-charge-limitedcurrent of a fixed bulk cross section. Over the range of drainbias investigated, the region essentially dominates forlong submicron devices 0.62 m while the regiondominates for deep submicron devices 0.12 m For thelatter, since the punchthrough is deep into the region overmost of the drain bias range investigated, the power index

for is well within the theoretically predicted range (1–2).A semi-empirical closed form equation, [see (4)], has beenproposed to represent both and over the differentdrain bias ranges, and their merging in between. This simpleformula could be very useful in simulating the punchthroughcurrent for submicron MOS devices.

ACKNOWLEDGMENT

The authors wish to thank C. Cavins of SemiconductorTechnology Laboratory (STL) of Motorola, Inc. for providingthe samples.

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Kuan-Yu Fu received the B.S. degree in physicsfrom the National Taiwan University, Taipei, Tai-wan, R.O.C., and the Ph.D. degree in physics fromthe University of Chicago, Chicago, IL, in 1967 and1972, respectively.

From 1972 to 1976, he was an Associate Profes-sor at the Department of Physics, National TaiwanUniversity. In 1976, he was promoted to the pro-fessorship at the same school. In the academic year1977–1978, he was with the Department of Electri-cal Engineering and Computer Science, University

of Massachusetts, Amherst, as a Visiting Research Associate. From 1979 to1980, he was with the Calspan Corporation, Buffalo, NY. He began workingin the field of semiconductor devices in 1980 after joining Texas Instruments,Inc. Since 1984, he has been with Motorola, Inc., Austin, TX, and becamea Member of Technical Staff in 1990. His recent work is in the area ofFLASH memory device and its associated technologies. He has authored andcoauthored more than 50 papers in various scientific and engineering journals.

Yuk L. Tsang received the B.S. degree from theUniversity of California, Berkeley, in 1974, and theM.S. degree from San Jose State University, SanJose, CA, in 1976, both in electrical engineering.He has accumulated credits for the Ph.D. degree inelectrical engineering from Rensselaer PolytechnicInstitute, Troy, NY, under the IBM Graduate WorkStudy program.

From 1975 to 1977, he was with Synertek Cor-poration, Santa Clara, CA, where he was engagedin MOSFET device characterization. From 1977 to

1978, he was with Motorola Semiconductor, Inc., Austin, TX, where he wasengaged in polysilicon-gate DRAM yield enhancement and characterization.From 1978 to 1993, he was with IBM Corporation, NY, first in the Kingstonfacility and then the East Fishkill facility, where he was an AdvisoryEngineer engaged in FET and bipolar silicon technlogy yield enhancement,device characterization, diagnostics, chip burn-in C4 reflow and flip-chipsocket contact development, and advanced bipolar process integration at theAdvanced Silicon Technology Center. Since 1993, he has been with Motorola,Inc., Austin, TX. He is presently a Member of the Motorola Technical Ladderinvolved in failure analysis for yield enhancement at the Advanced ProductsResearch and Development Laboratory. He has authored or coauthored severaltechnical papers and has 19 invention disclosures published including U.S.patents.

on the punchthrough phenomenon in submicron mos transistors

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