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AbstractOn-chip isolation is a function of many interde-

pendent variables. This paper uses industry exam-ples to highlight isolation impacts of technology −substrate doping levels and triple wells, grounding /guard rings, shielding, capacitive decoupling, andpackage inductance.

IntroductionOn-chip isolation is becoming increasingly

important due to higher integration levels, higherfrequencies, and tighter specifications for next gen-eration products. Higher integration not only resultsin more transistors switching, and thus, more noisecreation, but it also puts noisy and sensitive compo-nents together on the same chip that were on sepa-rate chips in the past. At higher frequencies noisenow couples more easily from place to place. Isola-tion provided by wells is reduced, and packageinductance becomes critical. The package imped-ance at GHz frequencies may cause on-chip ACgrounds to appear to float. When the tighter specifi-cations of next generation products, such as 3G cel-lular, are added to the picture, the RF designer mustbe both knowledgeable and creative to find an effec-tive solution. An understanding of the impact of theprocess technology, grounding effects, guard rings,shielding, decoupling, and package inductance isnecessary to optimize isolation. This paper reviewssome of the issues and presents industry examplesof current techniques that affect on-chip isolation.The challenge in addressing this topic is that mostof the effects are interdependent.

Technology ImpactsMost silicon-based RF chips are fabricated in

bipolar, BiCMOS, SiGe, or CMOS processes usinga lightly-doped bulk, p-type substrate. Heavilydoped substrates, most commonly used for largedigital designs, like microprocessors, where

latch-up concerns dominate isolation and the extrawafer cost can be justified, will not be covered inthis paper. See [1] for a basic review of heavilydoped substrates. A lightly doped substrate is highlyresistive, which typically means a resistivity ofaround 12 Ohm-cm or a doping concentrationaround 4x1014 cm-3 for a p-type substrate. Experi-enced designers will often be able to achieve a fewmore dB of isolation using a lightly doped substratethan a heavily doped substrate.

Figure 1 shows the cross-section of a BiCMOSprocess [2]. The channel stop region at the surfaceof the chip is approximately three orders of magni-tude less resistive than the substrate, so breaking thechannel stop between two points will increase theisolation between them. The buried layers and

sinker are roughly four orders of magnitude moreconductive than the bulk substrate. If the sinker andburied layer are connected to a low impedance ACground, they may form a shield and draw carriersaway from devices located inside the region. How-ever, buried layers may also provide a low imped-ance path for noise to travel into a sensitive area. Inthis case the buried layer must be broken to increasethe isolation. Takeshita of Sony presented an exam-

Figure 1: BiCMOS cross-section with relative resistivities.

On-chip RF Isolation TechniquesTallis Blalack1, Youri Leclercq2, C. Patrick Yue3

1Cadence Design Systems, San Jose, California, USA2Cadence Design Systems, Voiron, France

3Atheros Communications, Inc., Sunnyvale, California, USA

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ple of this at ISSCC’02 [3] as illustrated in Figure 2.The break in the buried layer combined with theaddition of a double guard ring provided a 20ximprovement in the isolation.

Triple wells, sometimes referred to as “deepnwells”, are now common options in most CMOSprocesses at 0.18 µm and below. Figure 3 shows the

cross-section of a triple well along with measuredisolation results as presented by Redmond ofMotorola at ISSCC’02 [4]. Although not shown inthe figure, the nwell containing the isolated pwell isfabricated with a greater depth than the standardnwell. Some less common process options mayinclude an n-type sinker and a heavily-doped n-typeburied layer at the bottom of the nwell. The triplewell provides a means to isolate the n-type devicesthat would normally exist in the p substrate. Theeffectiveness of triple-well isolation depends on thesignal frequencies, the doping levels, the groundingschemes, and the package.

One data point for the isolation added by using atriple well is the roughly 20 dB of isolation shownin the graph in Figure 3. Three curves exist in theplot. The top curve represents the intrinsic substrateisolation of the heavily doped substrate. The middlecurve is for a guard ring, and the lower curve is forthe triple well. Since the process used a heavilydoped substrate, the guard ring would not beexpected to show the same level of isolation as in alightly doped substrate. Additional simulation datapoints are found in Figure 4 for a lightly doped sub-

Figure 2: Sony ISSCC’02 example of breaking the buried layer to reduce coupling through the ISO(P+) region.

Figure 3: Motorola ISSCC’02 triple-well example showing approximately 20 dB additional isolation. The top curve is with no triple well or guard ring. The middle curve shows the isolation added by a guard ring, while the bottom curve is the triple well isolation.

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strate. These data points and the ones in the graphsto follow were obtained using SubstrateStormTM [5]to generate the substrate model for simulation. Thefive lines in Figure 4 represent the isolation betweena noise source and two different receiver structures,with and without modeling for package inductance.The noise source, located 1000 µm away from thereceiver, is an inverter core connected to Vcc andideal ground. The first receiver has a guard ringaround it, while the second receiver is containedinside a triple well. If Vdd and Vss of the receiverare connected to ideal ground, the triple well pro-vides approximately 13 dB more isolation than theguard ring. However, if 500 pH of inductance isadded to Vdd and Vss, the additional isolation dueto the triple well varies from 10 dB to no difference.The top line in the figure uses the supply connectedto the noise source to bias the nwell portion of thetriple well. In this case the Vcc connection shortsnoise between the two regions and degrades the iso-lation. This example highlights the complexity ofthe designers challenge to optimize isolation. Thecorrect solution for one technology and design maynot be the right choice for different design con-straints. Recent work indicates that interconnectcoupling may also reduce the achievable triple-wellisolation, but little has been published to this date.

Grounding EffectsIt is common practice among analog designers

to have separate supplies for analog and digital sec-

tions of the chip to isolate the analog circuitry fromthe switching noise introduced on the digital sup-plies. The same technique is useful to isolate differ-ent RF blocks. Dividing a chip into sections withdifferent substrate grounds will attenuate noise cou-pling from area of a chip to another. Cathelin ofSTMicroelectronics showed an example of this atDATE’02 [6]. The surface noise distributions inFigure 5 were generated using SubstrateStorm and

represent the same design with two differentgrounding schemes. The first layout of theLNA+mixer circuit used one substrate ground forthe chip. By adding a second substrate ground sothat the LNA (low noise amplifier) and mixer wereon separate supplies, additional isolation wasobtained and less noise coupled from the mixer tothe LNA. For a black and white printout, the darkregions in the layout on the right in Figure 5 repre-sent regions with the most isolation as compared tothe lighter regions in both layouts. In the color ver-sion red is noisy, representing the noise injectionlocation or no isolation, and blue is quiet, represent-ing the maximum isolation achieved. The same iso-lation levels or color mapping has been used forboth layouts.

Although a seal ring is not typically groundedand is therefore not a grounding effect, it candecrease the isolation achieved by separating sup-plies. In some fabrication processes, a metallizedring contacting the substrate is placed around theoutside of the chip to seal the edge from alkali ionsthat may enter the field oxide and affect the yield.

Figure 4: Comparison of guard ring and triple-well isolation versus frequency with and without 500 pH of bond wire inductance.

Guard Ring and Triple Well Isolation vs. Frequency

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Figure 5: STMicroelectronics DATE’02 example of grounding strategy. Separating the LNA and mixer grounds increased isolation.

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This ring may act as a low impedance path for noisecoupling between different regions on the chip. Ifdesign guidelines allow the edge seal to be broken,the ring should be severed where it provides a cou-pling path between different supply regions.

Guard RingsIn a lightly doped substrate, as contrasted with a

heavily doped substrate, guard rings typically pro-vide effective isolation. (This is assuming that carehas been taken to ensure that the guard ring is con-nected to a quiet supply.) Guard rings around a sen-sitive circuit help to decouple noise from the circuitand ensure that noise will couple equally into bothsides of a differential design. Guard rings around anoise source provide a low resistance path to ACground for the noise and help minimize the amountof noise injected into the substrate. The efficiencyof guard rings depends on the noise frequency andthe package inductance. Figure 6 illustrates thechange in isolation as a function of frequencybetween a noise source and a sensitive node with0.5 nH, 0.3 nH, and 0.1 nH inductors between a10 µm wide guard ring and ideal ground. The topline in the graph plots the isolation with no guardring for comparison. For the inductance valuesshown, the lines start to diverge above 1 GHz. Inthis example the inductance value of 0.5 nH actu-ally decreases isolation at 10 GHz because theinductive impedance causes the guard ring to“float” and become a low impedance conductor fornoise.

Backside connections to the substrate can beviewed, in a very simplistic manner, as a type ofguard ring. The effectiveness of the backside con-nection will depend on the inductance valuebetween the backside and ideal ground, and on thefrequency of the noise. Certain packages provide avery low inductance path from the backside of thechip to the board ground. In these cases a conduc-tive connection to the backside of the chip can addconsiderable isolation. However, if the package issuch that a backside connection is grounded throughdown-bonds to the paddle and significant induc-tance exists in the package, the backside connectionmay make matters worse. At higher frequencies thebackside connection will then act as a floating con-ductor to spread noise across the chip.

Guard ring width also affects isolation. van Zeijlof Ericsson presented a single-chip Bluetoothdesign at ISSCC’02, as shown in Figure 7, that useda 300 µm wide guard band to isolate the radio por-tion of the chip [7]. In this case the width of the

guard ring is similar to the depth of the substrate,and the package provides a very low impedance toground. Figure 8 shows simulation results of theattenuation provided by various widths of guardrings. With a 0.3 nH inductor in series with theguard ring, the larger guard rings provide better iso-

Figure 6: Guard ring isolation as a function of frequency for 0.5, 0.3, and 0.1 nH inductance values versus no guard ring.

Inductance Effects on Guard Ring Isolation (W = 10 um)

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Figure 7: Ericsson single-chip Bluetooth with a 300 µm-wide, guard band isolation.

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lation at lower frequencies but lose their advantageat higher frequencies. The appropriate guard ringwidth will depend on the frequency of noise to beattenuated, the space available, and the attenuationneeded. These simulations were run with the guardrings modeled as ideal conductors.

ShieldingProper shielding for sensitive signal lines and

passive components is an integral part of effectiveanalog/RF IC layout. The challenge is to determinethe appropriate shield layer, bias potential, and lay-out pattern. Sensitive signal buses are often laid outwith alternating signal and shield lines to preventcrosstalk through lateral and fringing electric fields.To isolate the signal lines from the substrate, nwellor diffusion layers can be placed under the lines toprevent noise coupling. In general, shieldingincreases parasitic capacitance since the field linesfrom the signal wires terminate at a closer distanceon the shielding before they reach another signalline or the substrate. The bias potential of the shieldshould be tied to the reference of the signals. Theeffectiveness of shielding also depends on the signaloperating frequency. In general, there is a trade-offbetween a lower shield parasitic capacitance and ahigher series resistance. As frequency increases, alarge series resistance causes the shield to be inef-fective.

Passive components such as inductors andcapacitors occupy substantial die area and thus are

susceptible to coupling through the substrate. In ap-type substrate, nwell can be placed under capaci-tors, inductors or bond pads to provide a low-capac-itance shield. However, the well resistance,typically on the order of 1 KOhm/sq., may be toolarge to be effective at high frequencies. To lowershield resistance, a diffusion or polysilicon layermay be used. Inductors are a special case, since themagnetic field will induce eddy current in a conduc-tive shield beneath the inductor. Inserting a patternof slots in the shield perpendicular to the inductortraces, as shown in Figure 9, will prohibit the eddycurrent by creating a “patterned ground shield” [8].

The effectiveness of a patterned ground shield toprovide isolation was measured in terms ofcrosstalk between two inductors using the test struc-ture shown in Figure 10. Each of the inductors aresurrounded with ground paths that act as guardrings. Therefore, the inductors are electrically iso-lated except that they reside on the same substrate.Substrate coupling between two adjacent inductorswas measured by the transmission coefficient, S21.The S-parameters were measured using a networkanalyzer and Cascade coplanar ground-sig-nal-ground probes. Figure 11 shows that the moreconductive substrate results in stronger couplingdue to its higher admittance. The peaks in |S21| forthe no ground shield (NGS) cases correspond to theonset of significant penetration of the electric fieldinto the silicon. This also implies that coupling isdominated by parasitic capacitance to the substrate,and that the magnetic coupling is weak. If magneticcoupling was the dominant coupling mechanism,

Figure 8: Guard ring isolation versus frequency as a function of width.

Guard Ring Width Effects on Isolation (L = 0.3 nH)

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Figure 9: Close-up photo of the patterned ground shield.

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increasing the resistance of the substrate would notchange the isolation between the inductors. In con-trast to no shielding, the inductors with polysiliconpatterned ground shields show improved isolationup to 25 dB at GHz frequencies. Figure 12 shows a5 GHz, 0.25 µm CMOS transceiver incorporatingmore than 40 on-chip inductors [9]. The patternedground shields are placed beneath each inductor tosuppress noise coupling through the substrate.

On-chip DecouplingDecoupling capacitance is not always thought of

as something that increases the isolation betweentwo points, but it serves the same role. Isolation isdesirable to attenuate noise coupling from one por-tion of a chip to another. If decoupling capacitancecan reduce the amount of noise created by supply-ing local charge for nearby switching and thus low-ering the peak current drawn across the packageinductance, careful use of it essentially isolates asensitive circuit that no longer sees the same supplyand substrate noise levels. An excellent example ofthis was presented by Connell of Motorola atISSCC’02 [10] as illustrated in Figure 13. A broad-band tuner was implemented with a digital synthe-sizer that generated large switching currents. Aninitial simulation with a 100 pF bypass capacitorshowed 82 mV of substrate noise created by theswitching. Increasing the bypass capacitor to1400 pF reduced the noise to 9 mV. Adding anon-chip voltage regulator with 5 pF of input capaci-

Figure 10: Two-port test structure to measure substrate coupling between adjacent inductors. Each inductor has one end grounded. The ground rings surrounding the inductors are not connected.

Figure 11: Effect of polysilicon patterned ground shield (PGS) on substrate coupling between two adjacent inductors. NGS denotes no ground shield placed under the inductors. The “Probes up” data represents the intrinsic noise floor of the testing setup.

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Figure 12: 5 GHz, 0.25 µm CMOS transceiver incorporating more than 40 on-chip inductors. Patterned ground shields are placed beneath each inductor to suppress noise coupling through the substrate.

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tance and 1100 pF of output capacitance decreasedthe noise to 1.5 mV. The fabricated design used300 pF of decoupling capacitance at the input of thevoltage regulator and 1100 pF of decoupling capaci-tance at the output of the voltage regulator toachieve a substrate noise level of 98 µV. Care wastaken to minimize the inductive connection to thesubstrate to reduce the amount of supply noise.

SummaryMeeting the specifications of the next genera-

tion RF products requires an experienced designerwho understands a variety of isolation techniques.This paper has detailed several commonly used iso-lation techniques while trying to emphasize theirinterdependent nature. Process technology options,grounding strategies, guard rings, shielding, decou-pling capacitance, and package parasitics all play animportant role in isolation. However, it is the com-bination of them that ultimately determines whetherthe final design will meet the product specifications.

References[1] T. Blalack, “Design Techniques to Reduce Substrate Noise”, Analog

Circuit Design: Volt Electronics; Mixed-Mode Systems;Low-Noise and RF Power Amplifiers for Telecommunication,pp. 193-217, J. Huijsing – Editor, Kluwer, 1999.

[2] F.J.R. Clement, “Technology Impacts on Substrate Noise”, AnalogCircuit Design: Volt Electronics; Mixed-Mode Systems;Low-Noise and RF Power Amplifiers for Telecommunication,pp. 173-192, J. Huijsing – Editor, Kluwer, 1999.

[3] T. Takeshita, T. Nishimura “A 622Mb/s Fully-Integrated Optical ICwith a Wide Range Input”, IEEE International Solid-State Cir-cuits Conference, vol. 45, pp. 258-259, February 2002.

[4] D. Redmond, M. Fitzgibbon, A. Bannon, D. Hobbs, Zhao Chunhe, K.Kase, J. Chan, M. Priel, K. Traylor, K. Tilley, “A GSM/GPRSMixed-Signal Baseband IC”, IEEE International Solid-StateCircuits Conference, vol. 45, pp. 62-63, February 2002.

[5] SubstrateStorm from Cadence Design Systems, Inc.,www.cadence.com

[6] A. Cathelin, D. Saias, D. Belot, Y. Leclercq, F.J.R. Clement, “Sub-strate Parasitic Extraction for RF Integrated Circuits”, Design,Automation & Test in Europe, poster 4C-2, March 2002.

[7] P.T.M. van Zeijl, J. Eikenbroek, P.-P. Vervoort, S. Setty, J. Tangen-berg, G. Shipton, E. Kooistra, I. Keekstra, D. Belot, “A Blue-tooth Radio in 0.18µm CMOS”, IEEE InternationalSolid-State Circuits Conference, vol. 45, pp. 86-87, February2002.

[8] C.P. Yue and S.S. Wong, “On-chip spiral inductors with patternedground shields for Si-based RF IC’s,” IEEE Journal ofSolid-State Circuits, vol. 33, no. 5, pp. 743−752, May 1998.

[9] D. Su, M. Zargari, C.P. Yue, S. Rabii, D. Weber, B. Kaczynski,S. Mehta, K. Singh, S. Mendis, and B. Wooley, “A 5-GHzCMOS Transceiver for IEEE 802.11a Wireless LAN”, IEEEInternational Solid-State Circuits Conference, vol. 45,pp. 92−93, February 2002.

[10] L. Connell, N. Hollenbeck, M. Bushman, D. McCarthy, S. Bergst-edt, R. Cieslak, J. Caldwell, “A CMOS Broadband Tuner IC”,IEEE International Solid-State Circuits Conference, vol. 45,pp. 400-401, February 2002.

Figure 13: Motorola ISSCC’02 use of decoupling capacitance to decrease noise.