omap3525_usermanual

OMAPOMAP35x Applications ProcessorTexas Instruments OMAP Family of Products

Technical Reference Manual

Literature Number: SPRUF98B September 2008

2

SPRUF98B September 2008 Submit Documentation Feedback

Contents11.1 1.2 1.3

Introduction

........................................................................................................... 181

Overview ................................................................................................................... 182 Environment ............................................................................................................... 184 Description ................................................................................................................. 185 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 MPU Subsystem ................................................................................................. 185 IVA2.2 Subsystem ............................................................................................... 186 On-Chip Memory ................................................................................................. 187 External Memory Interfaces .................................................................................... 187 DMA Controllers 188 188 189 189 189 191 193 193 195 197 199 Multimedia Accelerators

1.4 1.5

1.6

................................................................................................. ........................................................................................ 1.3.7 Security (HS Devices Only) .................................................................................... 1.3.8 Comprehensive Power Management ......................................................................... 1.3.9 Peripherals ........................................................................................................ Package-On-Package Concept ......................................................................................... OMAP35x Family ......................................................................................................... 1.5.1 Device Features.................................................................................................. 1.5.2 Device Identification ............................................................................................. 1.5.3 General Recommendations Relative to Unavailable Features/Modules ................................. Revision History ...........................................................................................................Memory Mapping

22.1 2.2 2.3

.................................................................................................... 201

Introduction ................................................................................................................ 202 Global Memory Space Mapping ........................................................................................ 204 L3 and L4 Memory Space Mapping .................................................................................... 207 2.3.1 2.3.2 L3 Memory Space Mapping .................................................................................... 207 L4 Memory Space Mapping .................................................................................... 208 L4-Core Memory Space Mapping ....................................................................... 208 L4-Wakeup Memory Space Mapping ................................................................... 211 L4-Peripheral Memory Space Mapping ................................................................. 212 L4-Emulation Memory Space Mapping ................................................................. 213

2.3.2.1 2.3.2.2 2.3.2.3 2.3.2.4 2.3.3 2.4 2.4.1

Register Access Restrictions ................................................................................... 215 IVA2.2 Subsystem Internal Memories and Cache Allocation .............................................. 216 IVA2.2 Subsystem Memory Hierarchy .................................................................. 216 IVA2.2 Cache Allocation .................................................................................. 217 DSP Access to L2 ROM .................................................................................. 218 DSP Access to L2 RAM .................................................................................. 218

IVA2.2 Subsystem Memory Space Mapping .......................................................................... 216 2.4.1.1 2.4.1.2 2.4.2 2.4.2.1 2.4.2.2 2.4.3 2.4.4 2.4.5 2.4.6

DSP Access to L2 Memories ................................................................................... 218

DSP and EDMA Access to Memories and Peripherals ..................................................... 218 L3 Interconnect View of the IVA2.2 Subsystem Memory Space .......................................... 219 DSP View of the IVA2.2 Subsystem Memory Space

.......................................................

219

EDMA View of the IVA2.2 Subsystem Memory Space ..................................................... 221Contents 3


www.ti.com

2.5

Revision History ........................................................................................................... 222

33.1

MPU Subsystem3.1.1 3.1.2

..................................................................................................... 223

MPU Subsystem Overview .............................................................................................. 224 Introduction ....................................................................................................... 224 Features ........................................................................................................... 225 MPU Subsystem Clock and Reset Distribution .............................................................. 228 Clock Distribution .......................................................................................... 228 Reset Distribution .......................................................................................... 229 ARM Overview ............................................................................................. 230 ARM Description ........................................................................................... 231 ARM Cortex-A8 Instruction, Data, and Private Peripheral Port............................. 231 MPU Subsystem Features........................................................................... 231 Clocks .................................................................................................. 232 Reset ................................................................................................... 232 Power Management .................................................................................. 232

3.2

MPU Subsystem Integration............................................................................................. 226 3.2.1 3.2.1.1 3.2.1.2 3.2.2 3.2.2.1 3.2.2.2

ARM Subchip ..................................................................................................... 230

3.2.2.2.1 3.2.2.2.2 3.2.2.3 3.2.2.3.1 3.2.2.3.2 3.2.2.3.3 3.2.3 3.2.3.1 3.2.3.2 3.2.3.3 3.2.3.4

Clock, Reset, and Power Management................................................................. 232

AXI2OCP and I2Async Bridges ................................................................................ 232 Bridges Overview .......................................................................................... 232 AXI2OCP Description ..................................................................................... 233 AXI Tag to OCP Thread Remapping

...................................................................

234

Clocks, Reset, and Power Management ............................................................... 234 Clocks .................................................................................................. 235 Reset ................................................................................................... 235 Power Management .................................................................................. 235

3.2.3.4.1 3.2.3.4.2 3.2.3.4.3 3.2.4 3.2.4.1 3.2.4.2 3.2.4.3 3.3 3.3.1 3.3.2

Interrupt Controller ............................................................................................... 235 Clocks ....................................................................................................... 235 Reset ........................................................................................................ 235 Power Management ....................................................................................... 235

MPU Subsystem Functional Description............................................................................... 236 Interrupts .......................................................................................................... 236 Power Management ............................................................................................. 236 Power Domains ............................................................................................ 236 Power States ............................................................................................... 237 Power Modes 237 241 242 242 242 242 242 242 242 243 243 244

3.3.2.1 3.3.2.2 3.3.2.3

3.4

3.5

.............................................................................................. 3.3.2.4 Transitions .................................................................................................. MPU Subsystem Basic Programming Model.......................................................................... 3.4.1 Clock Control ..................................................................................................... 3.4.2 MPU Power Mode Transitions ................................................................................. 3.4.2.1 Basic Power-On Reset.................................................................................... 3.4.2.2 MPU Into Standby Mode ................................................................................. 3.4.2.3 MPU Out of Standby Mode............................................................................... 3.4.2.4 MPU Power-On from a Powered-Off State ............................................................ 3.4.3 NEON Power Mode Transition ................................................................................. 3.4.4 ARM Programming Model ...................................................................................... Revision History ...........................................................................................................Power, Reset, and Clock Management

44

....................................................................... 245SPRUF98B September 2008 Submit Documentation Feedback

Contents

www.ti.com

4.1

PRCM Introduction to Power Management 4.1.1 4.1.2

...........................................................................

246

Goal of Power Management.................................................................................... 246 Power-Management Techniques .............................................................................. 246 Dynamic Voltage and Frequency Scaling .............................................................. 246 SmartReflex Adaptive Voltage Control Standby Leakage Management

4.1.2.1 4.1.2.2 4.1.2.3 4.1.2.4

.................................................................

247 249 249 250 251 251 252 253 253 255 255 256 257 258 259 259 261 262 263 264 265 266 269 269 269 270 271 271 271 272 272 272 273 273 274 275 276 276 277 277 277 278 278 2785

Dynamic Power Switching ................................................................................ 248

4.2

4.3

4.4

4.5

......................................................................... 4.1.2.5 DPS Versus SLM .......................................................................................... 4.1.2.6 Combining Power-Management Techniques .......................................................... 4.1.3 Architectural Blocks for Power Management................................................................. 4.1.3.1 Clock Domain .............................................................................................. 4.1.3.2 Power Domain ............................................................................................. 4.1.3.3 Voltage Domain ............................................................................................ 4.1.4 Device Power-Management Architecture ..................................................................... 4.1.4.1 Module Interface and Functional Clocks ............................................................... 4.1.4.2 Autoidle Clock Control .................................................................................... 4.1.5 SmartReflex Voltage-Control Overview ....................................................................... 4.1.5.1 Manual SmartReflex Voltage Control ................................................................... 4.1.5.2 Automatic SmartReflex Voltage Control ................................................................ PRCM Overview .......................................................................................................... 4.2.1 Introduction ....................................................................................................... 4.2.2 PRCM Features .................................................................................................. PRCM Environment ...................................................................................................... 4.3.1 External Clock Signals .......................................................................................... 4.3.2 External Reset Signals .......................................................................................... 4.3.3 External Power Signals ......................................................................................... PRCM Integration ......................................................................................................... 4.4.1 Power-Management Scheme, Reset, and Interrupt Requests............................................. 4.4.1.1 Power Domain ............................................................................................. 4.4.1.2 Resets....................................................................................................... 4.4.1.3 Interrupt Requests ......................................................................................... PRCM Reset Manager Functional Description ....................................................................... 4.5.1 Overview .......................................................................................................... 4.5.2 General Characteristics of Reset Signals .................................................................... 4.5.2.1 Scope ....................................................................................................... 4.5.2.2 Occurrence ................................................................................................. 4.5.2.3 Source Type ................................................................................................ 4.5.3 Reset Sources.................................................................................................... 4.5.3.1 Global Reset Sources ..................................................................................... 4.5.3.2 Local Reset Sources ...................................................................................... 4.5.4 Reset Distribution ................................................................................................ 4.5.5 Power Domain Reset Descriptions ............................................................................ 4.5.5.1 MPU Power Domain ...................................................................................... 4.5.5.2 NEON Power Domain ..................................................................................... 4.5.5.3 IVA2 Power Domain....................................................................................... 4.5.5.4 CORE Power Domain ..................................................................................... 4.5.5.5 DSS Power Domain ....................................................................................... 4.5.5.6 CAM Power Domain ...................................................................................... 4.5.5.7 USBHOST Power Domain ...............................................................................Contents


www.ti.com

4.5.5.8 4.5.5.9

SGX Power Domain ....................................................................................... 278 WKUP Power Domain 279 279 279 279 280 280 280 281 281 281 281 286 290 290 292 294 296 298 300 302 303 303 303 304 306 307 307 308 308 308 308 310 310 310 311 311 311 312 312 313 313 313 313 313 314 314 314

4.6

4.7

.................................................................................... 4.5.5.10 PER Power Domain ....................................................................................... 4.5.5.11 SmartReflex Power Domain.............................................................................. 4.5.5.12 DPLL Power Domains .................................................................................... 4.5.5.13 EFUSE Power Domain ................................................................................... 4.5.5.14 BANDGAP Logic........................................................................................... 4.5.5.15 External Warm Reset Assertion ......................................................................... 4.5.6 Reset Logging .................................................................................................... 4.5.6.1 PRCM Reset Logging Mechanism ...................................................................... 4.5.6.2 SCM Reset Logging ....................................................................................... 4.5.7 Reset Management Overview .................................................................................. 4.5.8 Reset Summary .................................................................................................. 4.5.9 Reset Sequences ................................................................................................ 4.5.9.1 Power-Up Sequence ...................................................................................... 4.5.9.2 Global Warm Reset Sequence .......................................................................... 4.5.9.3 IVA2.2 Subsystem Power-Up Sequence ............................................................... 4.5.9.4 IVA2 Software Reset Sequence ......................................................................... 4.5.9.5 IVA2 Global Warm Reset Sequence .................................................................... 4.5.9.6 IVA2 Power Domain Wake-Up Cold Reset Sequence ............................................... 4.5.9.7 CPEFUSE Reset Sequence ............................................................................. PRCM Power Manager Functional Description ....................................................................... 4.6.1 Overview .......................................................................................................... 4.6.1.1 Introduction ................................................................................................. 4.6.1.2 Device Partitioning ........................................................................................ 4.6.1.3 Memory and Logic Power Management ................................................................ 4.6.1.4 Power Domain States ..................................................................................... 4.6.1.5 Power State Transitions .................................................................................. 4.6.1.6 Device Power Modes ..................................................................................... 4.6.1.7 Isolation Between Power Domains ...................................................................... 4.6.2 Power Domain Implementation ................................................................................ 4.6.2.1 Device Power Domains ................................................................................... 4.6.2.2 Power Domain Memory Status .......................................................................... 4.6.2.3 Power Domain State Transition Rules .................................................................. 4.6.2.4 Power Domain Dependencies ........................................................................... 4.6.2.5 Power Domain Controls .................................................................................. 4.6.2.5.1 Power Domain Hardware Control .................................................................. 4.6.2.5.2 Power Domain Software Controls .................................................................. PRCM Clock Manager Functional Description ........................................................................ 4.7.1 Overview .......................................................................................................... 4.7.1.1 Interface and Functional Clocks ......................................................................... 4.7.2 External Clock I/Os .............................................................................................. 4.7.2.1 External Clock Inputs ..................................................................................... 4.7.2.1.1 32-kHz Always-On Clock ............................................................................ 4.7.2.1.2 High-Frequency System Clock...................................................................... 4.7.2.1.3 Alternate Clock ........................................................................................ 4.7.2.2 External Clock Outputs ................................................................................... 4.7.2.3 Summary ...................................................................................................

6

Contents


www.ti.com

4.7.3

Internal Clock Generation....................................................................................... 315 PRM ......................................................................................................... 317 CM ........................................................................................................... 319 DPLLs ....................................................................................................... 321 DPLL1 (MPU) and DPLL2 (IVA2) DPLL3 (CORE) 322 323 324 325 326 326 326 327 327 327 327 328 329 333 333 334 336 337 338 339 340 341 341 343 344 344 345 347 348 348 348 348 349 349 351 351 352 352 354 354 355 357 358 359 3607

4.7.3.1 4.7.3.2 4.7.3.3

.................................................................. ....................................................................................... 4.7.3.3.3 DPLL4 (Peripherals) .................................................................................. 4.7.3.3.4 DPLL5 (Peripherals) .................................................................................. 4.7.3.3.5 DPLL Clock Summary ............................................................................... 4.7.3.4 32-kHz Oscillator .......................................................................................... 4.7.3.5 Summary ................................................................................................... 4.7.4 Clock Distribution ................................................................................................ 4.7.4.1 Power Domain Clock Distribution ....................................................................... 4.7.4.1.1 MPU Power Domain.................................................................................. 4.7.4.1.2 IVA2 Power Domain .................................................................................. 4.7.4.1.3 SGX Power Domain .................................................................................. 4.7.4.1.4 CORE Power Domain ................................................................................ 4.7.4.1.5 EFUSE Power Domain............................................................................... 4.7.4.1.6 DSS Power Domain .................................................................................. 4.7.4.1.7 CAM Power Domain.................................................................................. 4.7.4.1.8 USBHOST Power Domain........................................................................... 4.7.4.1.9 WKUP Power Domain ............................................................................... 4.7.4.1.10 PER Power Domain .................................................................................. 4.7.4.1.11 SMARTREFLEX Power Domain ................................................................... 4.7.4.1.12 DPLL Domains ........................................................................................ 4.7.4.2 Clock Distribution Summary.............................................................................. 4.7.4.2.1 Power Domain Source Clocks ...................................................................... 4.7.4.2.2 Peripheral Module Clocks ........................................................................... 4.7.5 External Clock Controls ......................................................................................... 4.7.5.1 Clock Request (sys_clkreq) Control..................................................................... 4.7.5.2 System Clock Oscillator Control ......................................................................... 4.7.5.3 External Output Clock1 (sys_clkout1) Control ......................................................... 4.7.5.4 External Output Clock2 (sys_clkout2) Control ......................................................... 4.7.6 DPLL Control ..................................................................................................... 4.7.6.1 DPLL Multiplier and Divider Factors .................................................................... 4.7.6.2 DPLL Jitter Correction .................................................................................... 4.7.6.3 DPLL Frequency Ramp-Up Delay ....................................................................... 4.7.6.4 DPLL Modes ............................................................................................... 4.7.6.5 DPLL Low-Power Mode .................................................................................. 4.7.6.6 DPLL Clock Path Power Down .......................................................................... 4.7.6.7 Latencies ................................................................................................... 4.7.6.8 Recalibration ............................................................................................... 4.7.6.9 DPLL Programming Sequence .......................................................................... 4.7.7 Internal Clock Controls .......................................................................................... 4.7.7.1 PRM Source-Clock Controls ............................................................................. 4.7.7.2 CM Source-Clock Controls ............................................................................... 4.7.7.3 Common Interface Clock Controls ...................................................................... 4.7.7.4 DPLL Source-Clock Controls ............................................................................ 4.7.7.5 SGX Power Domain Clock Controls ....................................................................4.7.3.3.1 4.7.3.3.2SPRUF98B September 2008 Submit Documentation Feedback Contents

www.ti.com

4.7.7.6 4.7.7.7 4.7.7.8 4.7.7.9 4.7.7.10 4.7.7.11 4.7.7.12

CORE Power Domain Clock Controls .................................................................. 361 EFUSE Power Domain Clock Controls ................................................................. 364 DSS Power Domain Clock Controls

....................................................................

364

CAM Power Domain Clock Controls .................................................................... 365 USBHOST Power Domain Clock Controls ............................................................. 366 WKUP Power Domain Clock Controls .................................................................. 367 PER Power Domain Clock Controls 368 370 371 371 372 374 374 376 376 377 382 382 384 386 388 388 388 388 388 388 389 391 391 394 395 396 398 398 399 399 399 400 400 400 401 402 402 402 403 403 404 404

4.8

4.9 4.10

4.11

.................................................................... 4.7.7.13 SMARTREFLEX Power Domain Clock Controls ...................................................... 4.7.8 Clock Configurations ............................................................................................ 4.7.8.1 Processor Clock Configurations ......................................................................... 4.7.8.2 Interface and Peripheral Functional Clock Configurations ........................................... PRCM Idle and Wake-Up Management ............................................................................... 4.8.1 Overview .......................................................................................................... 4.8.2 Sleep Transition .................................................................................................. 4.8.3 Wakeup ........................................................................................................... 4.8.4 Device Wake-Up Events ........................................................................................ 4.8.5 Sleep and Wake-Up Dependencies ........................................................................... 4.8.5.1 Sleep Dependencies ...................................................................................... 4.8.5.2 Wake-Up Dependencies .................................................................................. 4.8.6 USBHOST/USBTLL Save-and-Restore Management ...................................................... 4.8.6.1 USBHOST SAR Sequences ............................................................................. 4.8.6.1.1 Save Sequence on Sleep Transition ............................................................... 4.8.6.1.2 Restore Sequence on Wake-Up Transition ....................................................... 4.8.6.2 USB TLL SAR Sequences ............................................................................... 4.8.6.2.1 Save Sequence on Sleep Transition ............................................................... 4.8.6.2.2 Restore Sequence on Wake-Up Transition ....................................................... PRCM Interrupts .......................................................................................................... PRCM Voltage Management Functional Description ................................................................ 4.10.1 Overview ......................................................................................................... 4.10.2 Voltage Domains ................................................................................................ 4.10.3 Voltage Domains Dependencies.............................................................................. 4.10.4 Voltage-Control Architecture .................................................................................. 4.10.5 VDD1 and VDD2 Control ...................................................................................... 4.10.5.1 Direct Control with VMODE Signals .................................................................... 4.10.5.2 Direct Voltage Control with I2C Interface ............................................................... 4.10.5.3 Voltage Controller and Dedicated SmartReflex I2C Interface ........................................ 4.10.5.4 SmartReflex Voltage Control ............................................................................. 4.10.5.4.1 SmartReflex in the Device........................................................................... 4.10.6 Analog Cells, LDOs, and Level Shifter Controls ............................................................ 4.10.6.1 SRAM Voltage Control .................................................................................... 4.10.6.2 Wake-Up and Emulation Voltage Control .............................................................. PRCM Off-Mode Management .......................................................................................... 4.11.1 Overview ......................................................................................................... 4.11.2 Device Off-Mode Configuration ............................................................................... 4.11.3 CORE Power Domain OFF-Mode Sequences .............................................................. 4.11.3.1 Sleep Sequences (Transition From ON to RETENTION/OFF) ...................................... 4.11.3.2 Wake-Up Sequences (Transition from RETENTION/OFF to ON) .................................. 4.11.4 Device Off-Mode Sequences..................................................................................

8

Contents


www.ti.com

4.11.4.1

Sleep Sequences .......................................................................................... 405

4.11.4.1.1 Device Off-Mode Transition without Using the OFF_MODE Signal ........................... 405 4.11.4.1.2 Device Off-Mode Transition Using Only the OFF_MODE Signal .............................. 405

4.12

..................................................................................... 4.11.4.2.1 Device Wakeup from Off Mode without Using the OFF_MODE Signal ....................... 4.11.4.2.2 Device Wakeup from Off Mode Using Only the OFF_MODE Signal .......................... PRCM Basic Programming Model ...................................................................................... 4.12.1 Global Registers ................................................................................................ 4.12.1.1 Revision Information Registers .......................................................................... 4.12.1.2 PRCM Configuration Registers .......................................................................... 4.12.1.3 Interrupt Configuration Registers ........................................................................ 4.12.1.3.1 MPU Interrupt Event Sources ....................................................................... 4.12.1.3.2 MPU Interrupt Registers ............................................................................. 4.12.1.3.3 IVA2.2 Interrupt Event Sources..................................................................... 4.12.1.3.4 IVA2 Interrupt Registers ............................................................................. 4.12.1.4 Event Generator Control Registers ..................................................................... 4.12.1.5 Output Signal Polarity Control Registers ............................................................... 4.12.1.5.1 CM_POLCTRL (CM Polarity Control Register) ................................................... 4.12.1.5.2 PRM_POLCTRL (PRM Polarity Control Register) ............................................... 4.12.1.6 SRAM Precharge Time Control Register ............................................................... 4.12.1.6.1 PRM_SRAM_PCHARGE (Voltage SRAM Precharge Counter Register) ..................... 4.12.2 Clock Management Registers ................................................................................. 4.12.2.1 System Clock Control Registers ......................................................................... 4.12.2.1.1 PRM_CLKSRC_CTRL (Clock Source Control Register) ........................................ 4.12.2.1.2 PRM_CLKSETUP (Source-Clock Setup Register) ............................................... 4.12.2.1.3 PRM_CLKSEL (Source-Clock Selection Register)............................................... 4.12.2.2 External Clock Output Control Registers ............................................................... 4.12.2.2.1 PRM_CLKOUT_CTRL (Clock Out Control Register) ............................................ 4.12.2.2.2 CM_CLKOUT_CTRL (Clock Out Control Register) .............................................. 4.12.2.3 DPLL Clock Control Registers ........................................................................... 4.12.2.3.1 CM_CLKSELn_PLL_ (Processor DPLL Clock Selection Register) ..... 4.12.2.3.2 CM_CLKSELn_PLL (DPLL Clock Selection Register) .......................................... 4.12.2.3.3 CM_CLKEN_PLL_ (Processor DPLL Clock Enable Register) .......... 4.12.2.3.4 CM_CLKEN_PLL (DPLL Enable Register)........................................................ 4.12.2.3.5 CM_AUTOIDLE_PLL_ (Processor DPLL Autoidle Register) ............ 4.12.2.3.6 CM_AUTOIDLE_PLL (DPLL Autoidle Register) .................................................. 4.12.2.3.7 CM_AUTOIDLE1_PLL (DPLL5 Autoidle Register) ............................................... 4.12.2.3.8 CM_IDLEST_CKGEN (Source-Clock Idle-Status Register) .................................... 4.12.2.3.9 CM_IDLEST2_CKGEN (DPLL5 Source-Clock Idle-Status Register) .......................... 4.12.2.3.10 CM_IDLEST_PLL_ (Processor DPLL Idle-Status Register) ........... 4.12.2.4 Power-Domain Clock Control Registers ................................................................ 4.12.2.4.1 CM_CLKSEL_ (Clock Select Register) ........................................ 4.12.2.4.2 CM_FCLKEN_ (Functional Clock Enable Register) ......................... 4.12.2.4.3 CM_ICLKEN_ (Interface Clock Enable Register) ............................ 4.12.2.4.4 CM_AUTOIDLE_ (Autoidle Register) .......................................... 4.12.2.4.5 CM_IDLEST_ (Idle-Status Register) ........................................... 4.12.2.4.6 CM_CLKSTCTRL_(Clock State Control Register) ........................... 4.12.2.4.7 CM_CLKSTST_ (Clock State Status Register)............................... 4.12.2.4.8 CM_SLEEPDEP_ (Sleep Dependency Control Register) ..................4.11.4.2 Wake-Up SequencesContents

406 406 406 407 407 407 407 407 407 408 409 409 409 409 409 411 411 411 411 411 411 411 411 412 412 412 412 412 412 413 413 414 414 414 414 415 415 415 415 416 416 417 417 418 419 4209


www.ti.com

4.12.2.5

Domain Wake-Up Control Registers .................................................................... 420

4.12.2.5.1 PM_WKEN_ (Wake-Up Enable Register) ..................................... 421 4.12.2.5.2 PM_WKST_ (Wake-Up Status Register) ...................................... 421 4.12.2.5.3 PM_WKDEP_ (Wake-Up Dependency Register) ............................ 421 4.12.2.5.4 PM_GRPSEL_ (Processor Group Selection Register) ............................................................................................... 423

................................................................................ 4.12.3.1 Reset Control .............................................................................................. 4.12.3.1.1 PRM_RSTTIME (Reset Time Register) ........................................................... 4.12.3.1.2 RM_RSTCTRL_ (Reset Control Register) .................................... 4.12.3.1.3 RM_RSTST_ (Reset Status Register) ......................................... 4.12.4 Power Management Registers ................................................................................ 4.12.4.1 PM_PWSTCTRL_ (Power State Control Register) ............................... 4.12.4.2 PM_PWSTST_ (Power State Status Register) .................................... 4.12.4.3 PM_PREPWSTST_ (Previous Power State Status Register) ................... 4.12.5 Voltage Management Registers .............................................................................. 4.12.5.1 External Voltage Control Register Descriptions ....................................................... 4.12.5.1.1 PRM_VOLTSETUP (Voltage Setup Time Register) ............................................. 4.12.5.1.3 PRM_VOLTOFFSET (Voltage Offset Register) .................................................. 4.12.5.1.4 PRM_VOLTCTRL (Voltage Source Control Register) ........................................... 4.12.5.2 Voltage Controller Registers ............................................................................. 4.12.5.2.1 PRM_VC_SMPS_SA (Voltage Controller SMPS Slave Address Register) ...................4.12.3 Reset Management Registers

423 423 423 423 424 425 425 427 428 428 428 429 429 430 430 431

4.12.5.2.2 PRM_VC_SMPS_VOL_RA (Voltage Controller SMPS Voltage Register Address Register) ............................................................................................... 431 4.12.5.2.3 PRM_VC_SMPS_CMD_RA (Voltage Controller SMPS Command Register Address Register) ............................................................................................... 431 4.12.5.2.4 PRM_VC_CMD_VAL_0 and PRM_VC_CMD_VAL_1 (Voltage Controller Command and Voltage Value Register 0 and 1).................................................................... 431 4.12.5.2.5 PRM_VC_CH_CONF (Voltage Controller Channel Configuration Register) ................. 431 4.12.5.2.6 PRM_VC_I2C_CFG (Voltage Controller I2C Interface Configuration Register) .............. 431 4.12.5.2.7 PRM_VC_BYPASS_VAL (Voltage Controller Bypass Command Register) .................. 431 4.12.6 Generic Programming Examples ............................................................................. 432 4.12.6.1 Clock Control ............................................................................................... 432 4.12.6.1.1 Enabling and Disabling the Functional Clocks.................................................... 432 4.12.6.1.2 Enabling and Disabling the Interface Clocks

.....................................................

434

4.12.6.1.3 Enabling and Disabling the INACTIVE State ..................................................... 435 4.12.6.1.4 Processor Clock Control ............................................................................. 436

4.13

4.14

....................................................................................... 4.12.6.3 Wake-Up Control .......................................................................................... 4.12.6.4 Voltage Controller Initialization Basic Programming Model .......................................... 4.12.6.5 Event Generator Programming Examples ............................................................. PRCM Use Cases and Tips ............................................................................................. 4.13.1 Voltage Control Using VMODE ............................................................................... 4.13.1.1 Introduction ................................................................................................. 4.13.1.2 Programming Sequence .................................................................................. 4.13.1.2.1 Initialization Procedure............................................................................... 4.13.1.2.2 VMODE Signals Toggling ........................................................................... 4.13.1.2.3 Summary Flow Chart ................................................................................ PRCM Registers .......................................................................................................... 4.14.1 CM Module Registers ..........................................................................................4.12.6.2 Reset Management

439 439 441 443 444 444 444 444 444 445 446 447 447

10

Contents


www.ti.com

4.14.1.1 4.14.1.2

CM Module Registers Mapping Summary

.............................................................

447

IVA2_CM Register Descriptions ......................................................................... 451

4.14.1.2.1 CM_FCLKEN_IVA2 .................................................................................. 451 4.14.1.2.2 CM_CLKEN_PLL_IVA2 .............................................................................. 451 4.14.1.2.3 CM_IDLEST_IVA2

...................................................................................

453

4.14.1.2.4 CM_IDLEST_PLL_IVA2 ............................................................................. 453 4.14.1.2.5 CM_AUTOIDLE_PLL_IVA2 ......................................................................... 454 4.14.1.2.6 CM_CLKSEL1_PLL_IVA2 ........................................................................... 454 4.14.1.2.7 CM_CLKSEL2_PLL_IVA2 ........................................................................... 455 4.14.1.2.8 CM_CLKSTCTRL_IVA2 ............................................................................. 456 4.14.1.2.9 CM_CLKSTST_IVA2 ................................................................................. 457 4.14.1.3 OCP_System_Reg_CM Register Descriptions ........................................................ 459 459 459 461 461 462 462 463 464 464 465 466 468 468 469 470 472 473 474 477 478 478 481 482 483 484 484 486 486 486 487 487 488 488 489 491 491

....................................................................................... .................................................................................... 4.14.1.4 MPU_CM Register Descriptions ......................................................................... 15.7.3.28 CM_CLKEN_PLL_MPU .............................................................................. 4.14.1.4.2 CM_IDLEST_MPU ................................................................................... 4.14.1.4.3 CM_IDLEST_PLL_MPU ............................................................................. 4.14.1.4.4 CM_AUTOIDLE_PLL_MPU ......................................................................... 4.14.1.4.5 CM_CLKSEL1_PLL_MPU ........................................................................... 4.14.1.4.6 CM_CLKSEL2_PLL_MPU ........................................................................... 4.14.1.4.7 CM_CLKSTCTRL_MPU ............................................................................. 4.14.1.4.8 CM_CLKSTST_MPU ................................................................................. 4.14.1.5 CORE_CM Register Descriptions ....................................................................... 4.14.1.5.1 CM_FCLKEN1_CORE ............................................................................... 4.14.1.5.2 CM_FCLKEN3_CORE ............................................................................... 4.14.1.5.3 CM_ICLKEN1_CORE ................................................................................ 4.14.1.5.4 CM_ICLKEN2_CORE ................................................................................ 4.14.1.5.5 CM_ICLKEN3_CORE ................................................................................ 4.14.1.5.6 CM_IDLEST1_CORE ................................................................................ 4.14.1.5.7 CM_IDLEST2_CORE ................................................................................ 4.14.1.5.8 CM_IDLEST3_CORE ................................................................................ 4.14.1.5.9 CM_AUTOIDLE1_CORE ............................................................................ 4.14.1.5.10 CM_AUTOIDLE2_CORE .......................................................................... 4.14.1.5.11 CM_AUTOIDLE3_CORE .......................................................................... 4.14.1.5.12 CM_CLKSEL_CORE ............................................................................... 4.14.1.5.13 CM_CLKSTCTRL_CORE .......................................................................... 18.7.2.6 CM_CLKSTST_CORE ............................................................................... 4.14.1.6 SGX_CM Register Descriptions ......................................................................... 4.14.1.6.1 CM_FCLKEN_SGX .................................................................................. 4.14.1.6.2 CM_ICLKEN_SGX ................................................................................... 4.14.1.6.3 CM_IDLEST_SGX .................................................................................... 23.2.6.6.12 CM_CLKSEL_SGX ................................................................................. 15.7.2.5 CM_SLEEPDEP_SGX ............................................................................... 4.14.1.6.6 CM_CLKSTCTRL_SGX ............................................................................. 4.14.1.6.7 CM_CLKSTST_SGX ................................................................................. 4.14.1.7 WKUP_CM Register Descriptions ....................................................................... 4.14.1.7.1 CM_FCLKEN_WKUP ................................................................................4.14.1.3.1 CM_REVISION 4.14.1.3.2 CM_SYSCONFIGSPRUF98B September 2008 Submit Documentation Feedback Contents

11

www.ti.com

4.14.1.7.2 CM_ICLKEN_WKUP ................................................................................. 492 4.14.1.7.3 CM_IDLEST_WKUP ................................................................................. 493 4.14.1.7.4 CM_AUTOIDLE_WKUP ............................................................................. 494 4.14.1.7.5 CM_CLKSEL_WKUP ................................................................................ 495 4.14.1.8 Clock_Control_Reg_CM Register Descriptions

.......................................................

497 499 501 502 503 504 505 507 507 508 509 510 511 511 511 512 512 513 514 515 516 517 517 517 518 518 519 520 520 521 523 523 524 526 528 530 531 531 532 534 534 536 536 537

15.7.7.3

CM_CLKEN_PLL ..................................................................................... 497

................................................................................... 4.14.1.8.3 CM_IDLEST_CKGEN ................................................................................ 4.14.1.8.4 CM_IDLEST2_CKGEN .............................................................................. 4.14.1.8.5 CM_AUTOIDLE_PLL ................................................................................ 4.14.1.8.6 CM_AUTOIDLE2_PLL ............................................................................... 4.14.1.8.7 CM_CLKSEL1_PLL .................................................................................. 4.14.1.8.8 CM_CLKSEL2_PLL .................................................................................. 4.14.1.8.9 CM_CLKSEL3_PLL .................................................................................. 4.14.1.8.10 CM_CLKSEL4_PLL ................................................................................. 15.7.2.1 CM_CLKSEL5_PLL .................................................................................. 12.6.9.1 CM_CLKOUT_CTRL ................................................................................. 4.14.1.9 DSS_CM Register Descriptions ......................................................................... 4.14.1.9.1 CM_FCLKEN_DSS................................................................................... 4.14.1.9.2 CM_ICLKEN_DSS ................................................................................... 4.14.1.9.3 CM_IDLEST_DSS .................................................................................... 4.14.1.9.4 CM_AUTOIDLE_DSS ................................................................................ 4.14.1.9.5 CM_CLKSEL_DSS ................................................................................... 4.14.1.9.6 CM_SLEEPDEP_DSS ............................................................................... 14.5.10.1 CM_CLKSTCTRL_DSS .............................................................................. 4.14.1.9.8 CM_CLKSTST_DSS ................................................................................. 4.14.1.10 CAM_CM Register Descriptions........................................................................ 4.14.1.10.1 CM_FCLKEN_CAM ................................................................................. 4.14.1.10.2 CM_ICLKEN_CAM.................................................................................. 4.14.1.10.3 CM_IDLEST_CAM .................................................................................. 4.14.1.10.4 CM_AUTOIDLE_CAM .............................................................................. 4.14.1.10.5 CM_CLKSEL_CAM ................................................................................. 4.14.1.10.6 CM_SLEEPDEP_CAM ............................................................................. 4.14.1.10.7 CM_CLKSTCTRL_CAM............................................................................ 4.14.1.10.8 CM_CLKSTST_CAM ............................................................................... 4.14.1.11 PER_CM Register Descriptions ........................................................................ 4.14.1.11.1 CM_FCLKEN_PER ................................................................................. 16.3.2.10 CM_ICLKEN_PER .................................................................................... 4.14.1.11.3 CM_IDLEST_PER .................................................................................. 4.14.1.11.4 CM_AUTOIDLE_PER .............................................................................. 4.14.1.11.5 CM_CLKSEL_PER ................................................................................. 4.14.1.11.6 CM_SLEEPDEP_PER ............................................................................. 4.14.1.11.7 CM_CLKSTCTRL_PER ............................................................................ 4.14.1.11.8 CM_CLKSTST_PER................................................................................ 4.14.1.12 EMU_CM Register Descriptions........................................................................ 4.14.1.12.1 CM_CLKSEL1_EMU ............................................................................... 4.14.1.12.2 CM_CLKSTCTRL_EMU............................................................................ 6.6.2.1 CM_CLKSTST_EMU ................................................................................. 14.5.7.13 CM_CLKSEL2_EMU .................................................................................4.14.1.8.2 CM_CLKEN2_PLL12 Contents


www.ti.com

4.14.1.12.5 CM_CLKSEL3_EMU

...............................................................................

538

4.14.1.13 Global_Reg_CM Register Descriptions ............................................................... 539 4.14.1.13.1 CM_POLCTRL ...................................................................................... 539 4.14.1.14 NEON_CM Register Descriptions ...................................................................... 540 4.14.1.14.1 CM_IDLEST_NEON ................................................................................ 540 4.14.1.14.2 CM_CLKSTCTRL_NEON .......................................................................... 540 4.14.1.15 USBHOST_CM Register Descriptions................................................................. 542 4.14.1.15.1 CM_FCLKEN_USBHOST.......................................................................... 542 14.5.9.10 18.7.2.16 CM_ICLKEN_USBHOST ............................................................................ 542 CM_AUTOIDLE_USBHOST 4.14.1.15.3 CM_IDLEST_USBHOST ........................................................................... 543

........................................................................ ....................................................................

544 545 547

4.14.1.15.5 CM_SLEEPDEP_USBHOST ...................................................................... 544 4.14.1.15.6 CM_CLKSTCTRL_USBHOST 4.14.2 PRM Module Registers 4.14.2.1 4.14.2.2 4.14.1.15.7 CM_CLKSTST_USBHOST ........................................................................ 546

........................................................................................ ................................................................................

PRM Module Registers Mapping Summary ............................................................ 547 IVA2_PRM Register Descriptions ....................................................................... 549 549

4.14.2.2.1 RM_RSTCTRL_IVA2

4.14.2.2.2 RM_RSTST_IVA2 .................................................................................... 549 4.14.2.2.3 PM_WKDEP_IVA2 ................................................................................... 551 4.14.2.2.4 PM_PWSTCTRL_IVA2 .............................................................................. 552 4.14.2.2.5 PM_PWSTST_IVA2 .................................................................................. 554 4.14.2.2.6 PM_PREPWSTST_IVA2 ............................................................................ 556 4.14.2.2.7 PRM_IRQSTATUS_IVA2 ............................................................................ 557 4.14.2.2.8 PRM_IRQENABLE_IVA2 ............................................................................ 558 4.14.2.3 OCP_System_Reg_PRM Register Descriptions ...................................................... 560 PRM_REVISION ...................................................................................... 560 15.7.3.15

4.14.2.3.2 PRM_SYSCONFIG................................................................................... 560 4.14.2.3.3 PRM_IRQSTATUS_MPU............................................................................ 561 4.14.2.3.4 PRM_IRQENABLE_MPU............................................................................ 565 4.14.2.4 MPU_PRM Register Descriptions ....................................................................... 569 RM_RSTST_MPU .................................................................................... 569 571 571 572 572 574 574 576 576 576 578 580 582 584 585 586 14.5.6.19

4.14.2.4.2 PM_WKDEP_MPU ................................................................................... 570

............................................................................ 4.14.2.4.4 PM_EVGENONTIM_MPU ........................................................................... 11.2.7.2.1 PM_EVGENOFFTIM_MPU ......................................................................... 4.14.2.4.6 PM_PWSTCTRL_MPU .............................................................................. 4.14.2.4.7 PM_PWSTST_MPU .................................................................................. 4.14.2.4.8 PM_PREPWSTST_MPU ............................................................................ 4.14.2.5 CORE_PRM Register Descriptions ..................................................................... 4.14.2.5.1 RM_RSTST_CORE .................................................................................. 4.14.2.5.2 PM_WKEN1_CORE.................................................................................. 4.14.2.5.3 PM_MPUGRPSEL1_CORE ......................................................................... 4.14.2.5.4 PM_IVA2GRPSEL1_CORE ......................................................................... 4.14.2.5.5 PM_WKST1_CORE .................................................................................. 4.14.2.5.6 PM_WKST3_CORE .................................................................................. 4.14.2.5.7 PM_WKST3_CORE .................................................................................. 4.14.2.5.8 PM_PWSTST_CORE ................................................................................4.14.2.4.3 PM_EVGENCTRL_MPUSPRUF98B September 2008 Submit Documentation Feedback Contents

13

www.ti.com

4.14.2.5.9 PM_PREPWSTST_CORE .......................................................................... 587 4.14.2.5.10 PM_WKEN3_CORE ................................................................................ 588 4.14.2.5.11 PM_IVA2GRPSEL3_CORE ....................................................................... 589 4.14.2.5.12 PM_MPUGRPSEL3_CORE ....................................................................... 590 4.14.2.6 SGX_PRM Register Descriptions ....................................................................... 591 4.14.2.6.1 RM_RSTST_SGX .................................................................................... 591 4.14.2.6.2 PM_WKDEP_SGX ................................................................................... 592 4.14.2.6.3 PM_PWSTCTRL_SGX

.............................................................................. ............................................................................

592 594

4.14.2.6.4 PM_PWSTST_SGX .................................................................................. 593 4.14.2.6.5 PM_PREPWSTST_SGX 4.14.2.7 WKUP_PRM Register Descriptions ..................................................................... 596

4.14.2.7.1 PM_WKEN_WKUP ................................................................................... 596 4.14.2.7.2 PM_MPUGRPSEL_WKUP .......................................................................... 597 4.14.2.7.3 PM_IVA2GRPSEL_WKUP .......................................................................... 598 4.14.2.7.4 PM_WKST_WKUP ................................................................................... 599 4.14.2.8 4.14.2.9 Clock_Control_Reg_PRM Registers .................................................................... 600 DSS_PRM Registers ...................................................................................... 602 602 606 607 611 611 623 623 625 626 640 640 644 645 652 4.14.2.8.1 Register Descriptions for Clock_Control_Reg_PRM ............................................. 600

4.15

.............................................................. 4.14.2.10 CAM_PRM Registers .................................................................................... 4.14.2.10.1 Register Descriptions for CAM_PRM ............................................................ 4.14.2.11 PER_PRM Registers..................................................................................... 4.14.2.11.1 Register Descriptions for PER_PRM ............................................................. 4.14.2.12 EMU_PRM Registers .................................................................................... 15.7.6.8 Register Descriptions for EMU_PRM .............................................................. 4.14.2.13 Global_Reg_PRM Registers ............................................................................ 4.14.2.13.1 Register Descriptions for Global_Reg_PRM .................................................... 4.14.2.14 NEON_PRM Registers .................................................................................. 4.14.2.14.1 Register Descriptions for NEON_PRM ........................................................... 4.14.2.15 USBHOST_PRM Registers ............................................................................. 4.14.2.15.1 Register Descriptions for USBHOST_PRM ..................................................... Revision History ...........................................................................................................4.14.2.9.1 Register Descriptions for DSS_PRM

55.1

5.2 5.3

........................................................................................................... 655 ................................................................................................... 656 5.1.1 Terminology ...................................................................................................... 656 5.1.2 Architecture Overview ........................................................................................... 658 5.1.3 Module Distribution .............................................................................................. 660 5.1.3.1 L3 Interconnect Agents ................................................................................... 660 5.1.3.2 L4-Core Agents ............................................................................................ 661 5.1.3.3 L4-Per Agents .............................................................................................. 662 5.1.3.4 L4-Emu Agents ............................................................................................ 662 5.1.3.5 L4-Wakeup Agents ........................................................................................ 663 5.1.4 Connectivity Matrix .............................................................................................. 663 L3 Interconnect ............................................................................................................ 665 5.2.1 Overview .......................................................................................................... 665 L3 Interconnect Integration .............................................................................................. 666 5.3.1 Clocking, Reset, and Power-Management Scheme ........................................................ 666 5.3.1.1 Clocks ....................................................................................................... 666InterconnectInterconnect OverviewSPRUF98B September 2008 Submit Documentation Feedback

14

Contents

www.ti.com

5.3.1.2 5.3.1.3 5.3.1.4 5.3.2

Resets....................................................................................................... 666 Power Domain ............................................................................................. 666 Power Management ....................................................................................... 666 667 667 668 668 668 668 670 671 671 672 674 674 675 677 677 679 679 681 682 683 688 688 688 688 689 691 691 695 696 698 698 699 700 701 703 705 705 706 707 708 709 710 710 710 711 71215

5.4

5.5

5.6

............................................................................................. 5.3.2.1 Interrupt Requests ......................................................................................... L3 Interconnect Functional Description ................................................................................ 5.4.1 Initiator Identification ............................................................................................ 5.4.2 Register Target ................................................................................................... 5.4.3 L3 Security and Firewalls ....................................................................................... 5.4.3.1 Protection Region ......................................................................................... 5.4.3.1.1 Default Region/Region0 ............................................................................. 5.4.3.1.2 Normal Regions ....................................................................................... 5.4.3.2 Priority Level Overview ................................................................................... 5.4.3.3 Read and Write Permission .............................................................................. 5.4.3.4 REQ_INFO_PERMISSION Configuration .............................................................. 5.4.3.5 L3 Firewall Registers Overview .......................................................................... 5.4.3.6 L3 Firewall Error-Logging Registers .................................................................... 5.4.3.7 L3 Firewall and System Control Module ................................................................ 5.4.4 Error Handling .................................................................................................... 5.4.4.1 Error Detection and Logging ............................................................................. 5.4.4.2 Time-Out .................................................................................................... 5.4.4.3 Error Steering .............................................................................................. 5.4.4.4 Global Error Reporting .................................................................................... L3 Interconnect Basic Programming Model ........................................................................... 5.5.1 General Recommendation ...................................................................................... 5.5.2 Initialization ....................................................................................................... 5.5.3 Error Analysis .................................................................................................... 5.5.3.1 Time-out Handling ......................................................................................... 5.5.3.2 Acknowledging Errors ..................................................................................... 5.5.4 Typical Example of Firewall Programming Example ........................................................ L3 Interconnect Registers ............................................................................................... 5.6.1 L3 Initiator Agent (L3 IA) Register Mapping Summary ..................................................... 5.6.2 L3 Initiator Agent (L3 IA) Register Descriptions ............................................................. 5.6.2.1 L3_IA_AGENT_CONTROL .............................................................................. 5.6.2.2 L3_IA_AGENT_STATUS ................................................................................. 5.6.2.3 L3_IA_ERROR_LOG ..................................................................................... 5.6.2.4 L3_IA_ERROR_LOG_ADDR ............................................................................ 5.6.3 L3 Target Agent (L3 TA) Register Mapping Summary...................................................... 5.6.4 L3 Target Agent (L3 TA) Register Descriptions ............................................................. 5.6.4.1 L3_TA_AGENT_CONTROL.............................................................................. 5.6.4.2 L3_TA_AGENT_STATUS ................................................................................ 5.6.4.3 L3_TA_ERROR_LOG..................................................................................... 5.6.4.4 L3_TA_ERROR_LOG_ADDR ........................................................................... 5.6.5 Register Target (RT) Register Mapping Summary .......................................................... 5.6.6 Register Target (RT) Register Descriptions .................................................................. 5.6.6.1 L3_RT_NETWORK ........................................................................................ 5.6.6.2 L3_RT_INITID_READBACK ............................................................................. 5.6.6.3 L3_RT_NETWORK_CONTROL ......................................................................... 5.6.7 Protection Mechanism (PM) Register Mapping Summary..................................................Hardware RequestsContents


www.ti.com

5.6.8

Protection Mechanism (PM) Register Descriptions

.........................................................

714

14.5.9.16 L3_PM_ERROR_LOG ................................................................................... 714 5.6.8.2 5.6.8.3 5.6.8.4 5.6.8.5 5.6.8.6 5.6.8.7 5.6.8.8 5.6.8.9 5.6.9 L3_PM_CONTROL ........................................................................................ 714 L3_PM_ERROR_CLEAR_SINGLE ..................................................................... 715 L3_PM_ERROR_CLEAR_MULTI ....................................................................... 716 L3_PM_REQ_INFO_PERMISSION_i ................................................................... 716 L3_PM_READ_PERMISSION_i ......................................................................... 717 L3_PM_WRITE_PERMISSION_i ........................................................................ 718 Bit Availability and Initialization Values for L3_PM_READ_PERMISSION_i and L3_PM_WRITE_PERMISSION_i ........................................................................ 719 L3_PM_ADDR_MATCH_k

............................................................................... .........................................................

721 724

Sideband Interconnect (SI) Register Mapping Summary ................................................... 723 L3_SI_CONTROL ......................................................................................... 724 L3_SI_FLAG_STATUS_1 ................................................................................ 725

5.6.10 Sideband Interconnect (SI) Register Descriptions 5.6.10.1 12.6.8.1 5.7 5.7.1

17.6.2.15 L3_SI_FLAG_STATUS_0 ............................................................................... 724 L4 Interconnects .......................................................................................................... 726 Overview .......................................................................................................... 726 L4-Core Interconnect...................................................................................... 728 L4-Per Interconnect ....................................................................................... 729 L4-Emu Interconnect ...................................................................................... 729 L4-Wakeup Interconnect.................................................................................. 730 731 731 731 731 731 731 732 732 732 733 733 733 733 733 733 735 741 741 741 742 742 742 742 743 744 745 5.7.1.1 5.7.1.2 5.7.1.3 5.7.1.4 5.8 5.8.1

L4 Interconnects Integration ............................................................................................. 731

5.9

5.1016

........................................................ 5.8.1.1 Clocks ....................................................................................................... 5.8.1.2 Resets....................................................................................................... 5.8.1.2.1 Hardware Reset....................................................................................... 5.8.1.2.2 Software Reset ........................................................................................ 5.8.1.3 Power Domain ............................................................................................. 5.8.1.4 Power Management ....................................................................................... 5.8.1.4.1 Module Power-Saving ................................................................................ 5.8.1.4.2 System Power Management and Wakeup ........................................................ L4 Interconnects Functional Description ............................................................................... 5.9.1 L4-Interconnects Initiator Identification........................................................................ 5.9.2 Endianness Management ....................................................................................... 5.9.3 L4 Security and Firewalls ....................................................................................... 5.9.3.1 Protection Mechanism .................................................................................... 5.9.3.2 Protection Group........................................................................................... 5.9.3.3 Segments and Regions ................................................................................... 5.9.3.4 L4 Firewall Address and Protection Registers Setting ............................................... 5.9.4 Error Handling .................................................................................................... 5.9.4.1 Overview .................................................................................................... 5.9.4.2 Error Logging............................................................................................... 5.9.4.2.1 No Target Core Found/Address Hole .............................................................. 5.9.4.2.2 Protection Violation ................................................................................... 5.9.4.2.3 Time-Out ............................................................................................... 5.9.4.3 TA Software Reset ........................................................................................ 5.9.4.4 Error Reporting ............................................................................................ L4 Interconnects Registers ..............................................................................................Clocking, Reset, and Power-Management Scheme

Contents


www.ti.com

5.10.1 L4 Initiator Agent (L4 IA) Register Mapping Summary 5.10.2.1 5.10.2.2 5.10.2.3 L4_IA_AGENT_CONTROL_L L4_IA_ERROR_LOG_L

....................................................

748 749 750 756 756 756 757 758 759 759 759 760 761 761 763 763 768 768 769 769 770 770 771 773

5.10.2 L4 Initiator Agent (L4 IA) Register Descriptions ............................................................ 749

...........................................................................

L4_IA_AGENT_STATUS_L .............................................................................. 749

..................................................................................

5.10.3 L4 Target Agent (L4 TA) Register Mapping Summary..................................................... 751

5.11

............................................................ 5.10.4.1 L4_TA_AGENT_CONTROL_L........................................................................... 5.10.4.2 L4_TA_AGENT_CONTROL_H .......................................................................... 5.10.4.3 L4_TA_AGENT_STATUS_L ............................................................................. 5.10.5 L4 Link Register Agent (LA) Register Mapping Summary ................................................ 5.10.6 L4 Link Register Agent (LA) Register Descriptions ........................................................ 5.10.6.1 L4_LA_NETWORK_H .................................................................................... 5.10.6.2 L4_LA_INITIATOR_INFO_L ............................................................................. 5.10.6.3 L4_LA_INITIATOR_INFO_H ............................................................................. 5.10.6.4 L4_LA_NETWORK_CONTROL_L ...................................................................... 5.10.6.5 L4_LA_NETWORK_CONTROL_H ...................................................................... 5.10.7 L4 Address Protection (AP) Register Mapping Summary ................................................. 19.8.2.9 Reset Values ............................................................................................... 5.10.8 L4 Address Protection (AP) Register Descriptions ......................................................... 5.10.8.1 L4_AP_SEGMENT_i_L ................................................................................... 5.10.8.2 L4_AP_SEGMENT_i_H .................................................................................. 5.10.8.3 L4_AP_PROT_GROUP_MEMBERS_k_L.............................................................. 5.10.8.4 L4_AP_PROT_GROUP_ROLES_k_L .................................................................. 5.10.8.5 L4_AP_REGION_l_L ...................................................................................... 5.10.8.6 L4_AP_REGION_l_H ..................................................................................... Revision History ...........................................................................................................5.10.4 L4 Target Agent (L4 TA) Register Descriptions

66.1 6.2

Interprocessor Communication (IPC) Module

............................................................. 775 ........................................................

IPC Overview .............................................................................................................. 776 IPC Integration ............................................................................................................ 777 6.2.1 Clocking, Reset, and Power-Management Scheme Module Clocks 777 777 6.2.1.1 6.2.1.2 Clocks ....................................................................................................... 777

6.2.1.1.1 6.2.1.2.1 6.2.1.2.2 6.2.1.3 6.2.1.4

........................................................................................

Resets....................................................................................................... 777 Hardware Reset....................................................................................... 777 Software Reset ........................................................................................ 777

Power Domains ............................................................................................ 778 Power Management ....................................................................................... 778 System Power Management ........................................................................ 778 Module Power Management ........................................................................ 778

6.2.1.4.1 6.2.1.4.2 6.2.2 6.2.2.1 6.2.2.2 6.3 6.3.1 6.3.2 6.3.3

Hardware Requests

............................................................................................. .................................................................................

779 779

Interrupt Requests ......................................................................................... 779 Idle Handshake Protocol

IPC Mailbox Functional Description .................................................................................... 780 Block Diagram .................................................................................................... 780 Mailbox Assignment ............................................................................................. 781

6.3.2.1

................................................................................................. Sending and Receiving Messages ............................................................................DescriptionContents

781 78117


www.ti.com

6.3.3.1 6.3.4 6.4 6.3.4.1 6.4.1

Description Description

................................................................................................. .................................................................................................

781 782 783 783 783 783 783 784 784 785 785 786 788

16-Bit Register Access .......................................................................................... 782

IPC Mailbox Basic Programming Model ............................................................................... 783

6.5

.................................................................... ............................................................................................ 6.4.1.2 Idle Mode and Clock Configuration ..................................................................... 6.4.2 Mailbox Assignment ............................................................................................. 6.4.3 Mailbox Communication Preparation .......................................................................... 6.4.4 Mailbox Communication Sequence ........................................................................... 6.4.5 Example of Communication .................................................................................... 6.4.5.1 Sending a Message (Polling Method)................................................................... 6.4.5.2 Sending a Message (Interrupt Method)................................................................. 6.4.5.3 Receiving Messages (Interrupt Method)................................................................ IPC Mailbox Use Cases and Tips ......................................................................................Initialization Flow for the Mailbox Module Software Reset 6.4.1.1 6.5.1 6.5.1.1 6.5.1.2

Camcorder Use Case: How to Configure the Mailbox Module for Communication Between the MPU and the IVA2.2 Subsystems ............................................................................. 788 Overview .................................................................................................... 788 Programming Flow ........................................................................................ 788 Initial Configuration ................................................................................... 788 Operational Mode ..................................................................................... 790

6.5.1.2.1 6.5.1.2.2 6.6 6.6.1 6.6.2

IPC Mailbox Registers

...................................................................................................

794

Mailbox Register Mapping Summary .......................................................................... 794 IPC Register Descriptions ...................................................................................... 795 MAILBOX_SYSCONFIG .................................................................................. 795

6.6.2.1 6.6.2.2 6.6.2.3 6.6.2.4 22.7.2.23 6.6.2.6 6.6.2.7

................................................................................. MAILBOX_MESSAGE_m ................................................................................ MAILBOX_FIFOSTATUS_m ............................................................................. MAILBOX_MSGSTATUS_m ............................................................................ MAILBOX_IRQSTATUS_u ............................................................................... MAILBOX_IRQENABLE_u ...............................................................................MAILBOX_SYSSTATUS

796 796 797 798 798 799

77.1 7.2

System Control Module

........................................................................................... 801

System Control Module Overview ...................................................................................... 802 System Control Module Environment .................................................................................. 803 7.2.1 Functional Interfaces ............................................................................................ 803 Basic System Control Module Pins 804 804 804 806 806 806 806 806 807 807 808 808 808 810

7.3

7.4

..................................................................... 7.2.1.2 System Control

omap3525_usermanual

Documents

l3 memory space mapping

l4 memory space mapping

global memory space

chip memory

external memory interfaces

omap35x family

package concept

mpu subsystem