Consume. Collaborate. Contribute.

ODSA: Technical IntroductionODSA Project Workshop at IBM

September 12th, 2019

AgendaStart Time End Time Speaker Company Topic

8:30 AM 9:30 AM IBM Auditorium

9:30 AM 9:40 AM Bapi Vinnakota/Mendy Furmanek Netronome/IBM Welcome/Logistics

9:40 AM 9:50 AM Archna Haylock OCP Intro to OCP

9:50 AM 10:00 AM Jeff Welser/Mendy Furmanek IBM IBM Welcome

10:00 AM 11:00 AM

Josh Friedrich

Jeff Stuecheli IBM

Exploiting Composable Heterogeneity

through Open Architectures

11:00 AM 11:15 AM Break Sponsored by IBM

11:15 AM 11:25 AM Bapi Vinnakota Netronome ODSA Technical Intro/Progress Summary

11:25 AM 11:50 AM Jayaprakash Balachandran/Jawad Nasrullah/Manish Shah Cisco/zGlue/Achronix PoC Progress and Call for Participation

11:50 AM 12:10 PM Mark Kuemerle Avera Semi BoW Interface Update

12:10 PM 12:30 PM Robert Wang Analog X PIPE Interface Update

12:30 PM 12:45 PM David Kehlet Intel Link Layer update

12:45 PM 1:30 PM Lunch Sponsored by IBM

1:30 PM 2:30 PM Z. Bandic, S. Fields, D. Jani, M. Kuemerle, mod B. Vinnakota TBD Open Uncore Panel

2:30 PM 2:50 PM Ashwin Poojary Facebook Monitoring

2:50 PM 3:10 PM Animesh Mishra/Robbie Adler Intel SImulation Models

3:10 PM 3:30 PM Millind Mittal Xilinx Xilinx and Chiplets

3:30 PM 3:50 PM Bill Chen IEEE IEEE Heterogeneous Integration Roadmap

3:50 PM 4:10 PM Eelco Bergman ASE ASE Heterogeneous Packaging

4:10 AM 4:25 PM Break Sponsored by IBM

4:25 PM 5:25 PM E. Bergman, M. Peng, W. Sauter, M. Hutner, mod S. Fuller IEEE/IBM/Tesla/Avera/ASE Packaging and Test Panel

5:25 AM 5:30 PM Archna Haylock/Bapi Vinnakota OCP Closing

The Open Domain-Specific Architecture

PCIe XSR Kandou BoW AIB HBM

PIPE Interface Adapter Common Abstraction

PCIe Link

Layer

SA

TA

CC

IX

Inter-Chiplet

Link Layer

Intra-Chiplet

Link Layer

Routing

Cache

Coherent

Non-

CoherentISF

Packag

e a

gg

rega

tio

n S

tack

Die

dis

agg

rega

tio

n S

tack

Inter-chiplet PHY technology options

Two motivation for chiplets:

• Shrinking a board into a package

• Disaggregating a complex and/or large die

Both require efficient inter-chiplet communication

• Different protocol stacks above the PHY layer

CX

L

Tile

Lin

k

ODSA ScopeReference architectures for:

Networking, Storage,

Inferencing, Training,

Video and Image processing

OCP Form Factors drive

Power,I/O Footprint, Performance

Business, Tools

Workflow to assemble

Product

Stack

Compliant

Interoperable

Chiplet

Marketplace

Accelerators drive the requirements

Chiplets are a means to meet requirements

Assemble DSAs from a library of ODSA-compliant chiplets.

Multi-technology

ODSA stack

HOST

STORAGE

NET

WO

RK

X8 PCIe G3 (64Gbps)40G Ethernet optical

40G Ethernet copper

NFP

FPGA

CPUF

F

QSFP 40G

QSFP 40G

MTP

MTP

F

F

QSFP 40G

QSFP 40G

MTP

MTPDRAM

DRAM

F

F

F

F

PCIe x4 Gen3

Active ProjectsProject Objective Organizations Participating Recent Results Upcoming Milestones Needs

PHY Analysis PHY requirementsPHY analysisCross-PHY abstraction

Alphawave, AnalogX, Aquantia, Avera Semi, Facebook, Intel, Kandou, Netronome, zGlue,

PHY Analysis paper(published at Hot Interconnect)

PIPE abstraction

BoW Interface No technology license fee, easy to port inter-chiplet interface spec

Aquantia, Avera Semi, Netronome

BoW Interface proposal(published at Hot Interconnect)

BoW specification 0.7End September, 2019

Test chips, Chiplet library supporting interface

Prototype product that integrates existing die from multiple companies into one package

Achronix, Cisco, Netronome, NXP, Samtec, Sarcina, zGlue,Macom, Facebook

Decomposable design flow. Committed schedule End user End user participation~30% funding is open

Chiplet design exchange

Open chiplet physical description format. Ayar, NXP, zGlue, Draft spec ZEF Exchange format draft specification

Link and Network Layer

Interface and implementations –requirements and proposals

Achronix, Avera Semi, Intel, Netronome, NXP, Xilinx

Reference Architectures

I/O, Compute, Memory, functional partition for SmartNIC, Inferencing, Storage, Learning, Image/Video

Chiplet proposals Proposals based on interfaces for chipletsfor common functions

Business workflow Formalize learnings from prototype effort

Wiki: https://www.opencompute.org/wiki/Server/ODSA, meet Fridays at 8 AM Pacific Time. Please join us.

https://www.opencompute.org/wiki/Server/ODSA

CHARTER

• Chiplet Machine Readable Description Standard Generation

• Chiplet Catalog – starting with a public catalog, hanging off the ODSA wiki

• PChiplet based SDV to Chiplet based package conversion flow

Chiplet Design Exchange Subgroup

Software

Dev Vehicle (SDV)

PCB

CDX

Inputs &

Flow

Packaged PoC Part

CDX Chiplet

Catalog

INDUSTRY SURVEY

• Executives and Business Developers

indicate the need for Chiplet sharing

mechanism.

• As business thinking develops and

business need arises, willingness to

participate in a marketplace will increase.

CDX effort will help.

CALL TO ACTION – JOIN US

• Looking for EDA, OSAT, Design Service, Chiplet Vendor, Distributor participation.

• Define a flow for PCB to Package conversion

• Setup a CDX service of your own

• List your Chiplets

• Share your requirements and wishlist for Chiplets

• Contact Jawad Nasrullah, jawad@zglue.com, for participation

CDX POC FLOW

mailto:jawad@zglue.com

OCP Market Survey - IHS

• An independent survey on the market size for chiplet-based designs at chip vendors, hyperscalers, service providers and systems vendors

worldwide.

• Aim to complete a preliminary release of the data by the regional summit in Amsterdam, more complete data to follow.

• Analyst, Tom Hackenberg (tom.hackenberg@ihsmarkit.com) is here at the workshop. All data will be anonymized and reported in aggregate.

• Please engage with him if you would like to provide primary data. Survey results will be publicly available.

Please Help! Join a WorkstreamJoin Interface/Standards:

(Mark Kuemerle/Ramin Farjad/Robert Wang/David Kehlet)

DevelopPackaging + Socket, Dev Board

Provide FPGA IP

Provide ODSA chiplets

Provide PHY Technology

Join the PoC, Build fast:(Quinn Jacobson/Jawad Nasrullah/

Jayaprakash Balachandran)

Join Business, IP and workflow:(Sam Fuller/Dharmesh Jani)

Develop software Define test andassembly workflow

Provide Chiplet IP

Workstream contact information at the ODSA wiki

Define ArchitecturalInterface

Thank you to IBM/Mendy/Anthony