octal, 14-bit, 50 msps, serial lvds, 1.8 v adc data sheet...
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Octal, 14-Bit, 50 MSPS,Serial LVDS, 1.8 V ADC
Data Sheet AD9252
Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.
FEATURES 8 analog-to-digital converters (ADCs) integrated into 1 package 93.5 mW ADC power per channel at 50 MSPS SNR = 73 dB (to Nyquist) ENOB = 12 bits SFDR = 84 dBc (to Nyquist) Excellent linearity
DNL = ±0.4 LSB (typical); INL = ±1.5 LSB (typical) Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 325 MHz, full-power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control
Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode
APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment
GENERAL DESCRIPTION The AD9252 is an octal, 14-bit, 50 MSPS ADC with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. Operating at a conversion rate of up to 50 MSPS, it is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.
The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.
FUNCTIONAL BLOCK DIAGRAM
SERIALLVDS
REFSELECT
AD9252
AGND
VIN – A
VIN + A
VIN – B
VIN + B
VIN – D
VIN + D
VIN – C
VIN + C
SENSE
VREF
AVDD DRVDD
14
14
14
14
PDWN
REFTREFB
D – AD + A
D – BD + B
D – DD + D
D – CD + C
FCO–
FCO+
DCO+DCO–
CLK+
DRGND
CLK–
SERIAL PORTINTERFACE
CSB SCLK/DTP
SDIO/ODM
RBIAS
SERIALLVDS
SERIALLVDS
SERIALLVDS
ADC
ADC
ADC
ADC
DATA RATEMULTIPLIER
0.5V
SERIALLVDSVIN – E
VIN + E
VIN – F
VIN + F
VIN – H
VIN + H
VIN – G
VIN + G
14
14
14
14
D – ED + E
D – FD + F
D – HD + H
D – GD + G
SERIALLVDS
SERIALLVDS
SERIALLVDS
ADC
ADC
ADC
ADC
06
296
-00
1
Figure 1.
The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
The AD9252 is available in an RoHS compliant, 64-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS 1. Small Footprint. Eight ADCs are contained in a small package. 2. Low Power of 93.5 mW per Channel at 50 MSPS. 3. Ease of Use. A data clock output (DCO) operates up to
350 MHz and supports double data rate (DDR) operation. 4. User Flexibility. SPI control offers a wide range of flexible
features to meet specific system requirements. 5. Pin-Compatible Family. This includes the AD9212 (10-bit)
and AD9222 (12-bit).
AD9252* PRODUCT PAGE QUICK LINKSLast Content Update: 02/23/2017
COMPARABLE PARTSView a parametric search of comparable parts.
EVALUATION KITS• AD9252 Evaluation Board
DOCUMENTATIONApplication Notes
• AN-282: Fundamentals of Sampled Data Systems
• AN-345: Grounding for Low-and-High-Frequency Circuits
• AN-501: Aperture Uncertainty and ADC System Performance
• AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-742: Frequency Domain Response of Switched-Capacitor ADCs
• AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter
• AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit
• AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs
• AN-835: Understanding High Speed ADC Testing and Evaluation
• AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front End
Data Sheet
• AD9252: Octal, 14-Bit, 50 MSPS, Serial LVDS, 1.8 V ADC Data Sheet
TOOLS AND SIMULATIONS• Visual Analog
• AD9252 IBIS Models
REFERENCE MATERIALSCustomer Case Studies
• National Instruments Case Study
Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
DESIGN RESOURCES• AD9252 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DISCUSSIONSView all AD9252 EngineerZone Discussions.
SAMPLE AND BUYVisit the product page to see pricing options.
TECHNICAL SUPPORTSubmit a technical question or find your regional support number.
DOCUMENT FEEDBACKSubmit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
AD9252 Data Sheet
Rev. E | Page 2 of 52
TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3
AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Diagrams .......................................................................... 7
Absolute Maximum Ratings ............................................................ 9 Thermal Impedance ..................................................................... 9 ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10 Equivalent Circuits ......................................................................... 12 Typical Performance Characteristics ........................................... 14 Theory of Operation ...................................................................... 17
Analog Input Considerations .................................................... 17
Clock Input Considerations ...................................................... 19 Serial Port Interface (SPI) .............................................................. 27
Hardware Interface ..................................................................... 27 Memory Map .................................................................................. 29
Reading the Memory Map Table .............................................. 29 Reserved Locations .................................................................... 29 Default Values ............................................................................. 29 Logic Levels ................................................................................. 29
Applications Information .............................................................. 32 Design Guidelines ...................................................................... 32
Evaluation Board ............................................................................ 33 Power Supplies ............................................................................ 33 Input Signals................................................................................ 33 Output Signals ............................................................................ 33 Default Operation and Jumper Selection Settings ................. 34 Alternative Analog Input Drive Configuration...................... 35
Outline Dimensions ....................................................................... 52 Ordering Guide .......................................................................... 52
REVISION HISTORY 12/11—Rev. D to Rev. E Changes to Output Signals Section and Figure 58 ..................... 33 Change to Default Operation and Jumper Selection Settings Section .............................................................................................. 34 Added Endnote 2 in Ordering Guide .......................................... 52
4/10—Rev. C to Rev. D Changes to Address 16 in Table 16 ............................................... 31 Updated Outline Dimensions ....................................................... 52 Changes to Ordering Guide .......................................................... 52
12/09—Rev. B to Rev. C Updated Outline Dimensions ....................................................... 52 Changes to Ordering Guide .......................................................... 52
7/09—Rev. A to Rev. B Changes to Figure 5 ........................................................................ 10 Changes to Figure 38 and Figure 39 ............................................. 18 Changes to Figure 51 and Figure 52 ............................................. 25 Updated Outline Dimensions ....................................................... 52
12/07—Rev. 0 to Rev. A Changes to Features .......................................................................... 1 Changes to Crosstalk Parameter ..................................................... 3 Changes to Figure 2 to Figure 4 ...................................................... 7 Changes to Table 9 Endnote .......................................................... 23
Changes to Digital Outputs and Timing Section ....................... 24 Added Table 10 ............................................................................... 24 Changes to Table 11 and Table 12 ................................................ 24 Changes to RBIAS Pin Section ..................................................... 25 Deleted Figure 51 to Figure 52...................................................... 25 Moved Figure 53 ............................................................................. 25 Changes to Serial Port Interface (SPI) Section ........................... 27 Changes to Table 15 ....................................................................... 28 Changes to Reading the Memory Map Table Section ............... 29 Added Applications Information and Design Guidelines Sections ...................................................... 32 Changes to Input Signals Section ................................................. 33 Changes to Output Signals Section .............................................. 33 Changes to Figure 60 ...................................................................... 33 Changes to Default Operation and Jumper Selection Settings Section .......................................................................... 34 Changes to Alternative Analog Input Drive Configuration Section............................................................... 35 Added Figure 62 and Figure 63 .................................................... 35 Changes to Figure 68 ...................................................................... 42 Changes to Table 17 ....................................................................... 48 Updated Outline Dimensions ....................................................... 52 Changes to Ordering Guide .......................................................... 52
10/06—Revision 0: Initial Version
Data Sheet AD9252
Rev. E | Page 3 of 52
SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1. AD9252-50 Parameter1 Temperature Min Typ Max Unit RESOLUTION 14 Bits ACCURACY
No Missing Codes Full Guaranteed Offset Error Full ±1 ±8 mV Offset Matching Full ±3 ±8 mV Gain Error Full ±1.5 ±2.5 % FS Gain Matching Full ±0.3 ±0.7 % FS Differential Nonlinearity (DNL) Full ±0.4 ±1 LSB Integral Nonlinearity (INL) Full ±1.5 ±4 LSB
TEMPERATURE DRIFT Offset Error Full ±2 ppm/°C Gain Error Full ±17 ppm/°C Reference Voltage (1 V Mode) Full ±21 ppm/°C
REFERENCE Output Voltage Error (VREF = 1 V) Full ±2 ±30 mV Load Regulation @ 1.0 mA (VREF = 1 V) Full 3 mV Input Resistance Full 6 kΩ
ANALOG INPUTS Differential Input Voltage Range (VREF = 1 V) Full 2 V p-p Common-Mode Voltage Full AVDD/2 V Differential Input Capacitance Full 7 pF Analog Bandwidth, Full Power Full 325 MHz
POWER SUPPLY AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V IAVDD Full 360 373.4 mA IDRVDD Full 55.5 58 mA Total Power Dissipation (Including Output Drivers) Full 748 773 mW Power-Down Dissipation Full 2 11 mW Standby Dissipation2 Full 89 mW
CROSSTALK AIN = −0.5 dBFS Full −90 dB Overrange3 Full −90 dB
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Can be controlled via the SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range.
AD9252 Data Sheet
Rev. E | Page 4 of 52
AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 2. AD9252-50 Parameter1 Temperature Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz Full 73.2 dB fIN = 19.7 MHz Full 71 73 dB fIN = 35 MHz Full 72.7 dB fIN = 70 MHz Full 71 dB
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz Full 72.5 dB fIN = 19.7 MHz Full 70.2 72.2 dB fIN = 35 MHz Full 72 dB fIN = 70 MHz Full 70.5 dB
EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz Full 11.87 Bits fIN = 19.7 MHz Full 11.5 11.84 Bits fIN = 35 MHz Full 11.79 Bits fIN = 70 MHz Full 11.5 Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz Full 85 dBc fIN = 19.7 MHz Full 73 84 dBc fIN = 35 MHz Full 83 dBc fIN = 70 MHz Full 79 dBc
WORST HARMONIC (SECOND OR THIRD) fIN = 2.4 MHz Full −85 dBc fIN = 19.7 MHz Full −84 −73 dBc fIN = 35 MHz Full −83 dBc fIN = 70 MHz Full −79 dBc
WORST OTHER (EXCLUDING SECOND OR THIRD) fIN = 2.4 MHz Full −90 dBc fIN = 19.7 MHz Full −90 −80 dBc fIN = 35 MHz Full −90 dBc fIN = 70 MHz Full −89 dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS fIN1 = 15 MHz, fIN2 = 16 MHz 25°C 80.0 dBc fIN1 = 70 MHz, fIN2 = 71 MHz 25°C 80.0 dBc
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Data Sheet AD9252
Rev. E | Page 5 of 52
DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3. AD9252-50 Parameter1 Temperature Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage2 Full 250 mV p-p Input Common-Mode Voltage Full 1.2 V Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 1.5 pF
LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 0.5 pF
LOGIC INPUT (CSB) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 70 kΩ Input Capacitance 25°C 0.5 pF
LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Full 1.2 DRVDD + 0.3 V Logic 0 Voltage Full 0 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF
LOGIC OUTPUT (SDIO/ODM)3 Logic 1 Voltage (IOH = 800 μA) Full 1.79 V Logic 0 Voltage (IOL = 50 μA) Full 0.05 V
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644) Logic Compliance LVDS Differential Output Voltage (VOD) Full 247 454 mV Output Offset Voltage (VOS) Full 1.125 1.375 V Output Coding (Default) Offset binary
DIGITAL OUTPUTS (D + x, D − x), (LOW POWER, REDUCED SIGNAL OPTION)
Logic Compliance LVDS Differential Output Voltage (VOD) Full 150 250 mV Output Offset Voltage (VOS) Full 1.10 1.30 V Output Coding (Default) Offset binary
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 This is specified for LVDS and LVPECL only. 3 This is specified for 13 SDIO pins sharing the same connection.
AD9252 Data Sheet
Rev. E | Page 6 of 52
SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4. AD9252-50 Parameter1 Temp Min Typ Max Unit CLOCK2
Maximum Clock Rate Full 50 MSPS Minimum Clock Rate Full 10 MSPS Clock Pulse Width High (tEH) Full 10.0 ns Clock Pulse Width Low (tEL) Full 10.0 ns
OUTPUT PARAMETERS2, 3 Propagation Delay (tPD) Full 1.5 2.3 3.1 ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps FCO Propagation Delay (tFCO) Full 1.5 2.3 3.1 ns DCO Propagation Delay (tCPD)4 Full tFCO + (tSAMPLE/28) ns DCO to Data Delay (tDATA)4 Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps DCO to FCO Delay (tFRAME)4 Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps Data-to-Data Skew (tDATA-MAX − tDATA-MIN) Full ±50 ±200 ps Wake-Up Time (Standby) 25°C 600 ns Wake-Up Time (Power-Down) 25°C 375 μs Pipeline Latency Full 8 CLK cycles
APERTURE Aperture Delay (tA) 25°C 750 ps Aperture Uncertainty (Jitter) 25°C <1 ps rms Out-of-Range Recovery Time 25°C 1 CLK cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Can be adjusted via the SPI. 3 Measurements were made using a part soldered to FR-4 material. 4 tSAMPLE/28 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
Data Sheet AD9252
Rev. E | Page 7 of 52
TIMING DIAGRAMS
DCO–
DCO+
D – x
D + x
FCO–
FCO+
VIN ± x
CLK–
CLK+
MSBN – 9
D12N – 9
D11N – 9
D10N – 9
D9N – 9
D8N – 9
D7N – 9
D6N – 9
D5N – 9
D4N – 9
D3N – 9
D2N – 9
D0N – 9
D1N – 9
D12N – 8
MSBN – 8
N – 1
tA
N
tDATA
tFRAMEtFCO
tPD
tCPD
tEH tEL
062
96-
002
Figure 2. 14-Bit Data Serial Stream (Default), MSB First
DCO–
DCO+
D – x
D + x
FCO–
FCO+
VIN ± x
CLK–
CLK+
MSBN – 9
D10N – 9
D9N – 9
D8N – 9
D7N – 9
D6N – 9
D5N – 9
D4N – 9
D3N – 9
D2N – 9
D1N – 9
D0N – 9
D10N – 8
MSBN – 8
N – 1
N
tDATA
tFRAMEtFCO
tPD
tCPD
tEH
tA
tEL
062
96-0
03
Figure 3. 12-Bit Data Serial Stream, MSB First
AD9252 Data Sheet
Rev. E | Page 8 of 52
062
96-
004
DCO–
DCO+
D – x
D + x
FCO–
FCO+
VIN ± x
CLK–
CLK+
LSBN – 9
D0N – 9
D1N – 9
D2N – 9
D3N – 9
D4N – 9
D5N – 9
D6N – 9
D7N – 9
D8N – 9
D9N – 9
D10N – 9
D11N – 9
D12N – 9
LSBN – 8
D0N – 8
N – 1
tA
N
tDATA
tFRAMEtFCO
tPD
tCPD
tEH tEL
Figure 4. 14-Bit Data Serial Stream, LSB First
Data Sheet AD9252
Rev. E | Page 9 of 52
ABSOLUTE MAXIMUM RATINGS Table 5.
Parameter With Respect To Rating
ELECTRICAL AVDD AGND −0.3 V to +2.0 V DRVDD DRGND −0.3 V to +2.0 V AGND DRGND −0.3 V to +0.3 V AVDD DRVDD −2.0 V to +2.0 V Digital Outputs
(D + x, D − x, DCO+, DCO−, FCO+, FCO−)
DRGND −0.3 V to +2.0 V
CLK+, CLK− AGND −0.3 V to +3.9 V VIN + x, VIN − x AGND −0.3 V to +2.0 V SDIO/ODM AGND −0.3 V to +2.0 V PDWN, SCLK/DTP, CSB AGND −0.3 V to +3.9 V REFT, REFB, RBIAS AGND −0.3 V to +2.0 V VREF, SENSE AGND −0.3 V to +2.0 V
ENVIRONMENTAL Operating Temperature
Range (Ambient) −40°C to +85°C
Storage Temperature Range (Ambient)
−65°C to +150°C
Maximum Junction Temperature
150°C
Lead Temperature (Soldering, 10 sec)
300°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL IMPEDANCE
Table 6. Air Flow Velocity (m/s) θJA
1 θJB θJC Unit 0.0 17.7 °C/W 1.0 15.5 8.7 0.6 °C/W 2.5 13.9 °C/W 1 θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad
soldered to PCB.
ESD CAUTION
AD9252 Data Sheet
Rev. E | Page 10 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
0629
6-0
05
PIN 1INDICATOR
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D –
GD
+ G
D –
FD
+ F
D –
ED
+ E
DC
O–
DC
O+
FC
O–
FC
O+
D –
DD
+ D
D –
CD
+ C
D –
BD
+ B
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VIN
+ F
VIN
– F
AV
DD
VIN
– E
VIN
+ E
AV
DD
RE
FT
RE
FB
VR
EF
SE
NS
ER
BIA
SV
IN +
DV
IN –
DA
VD
DV
IN –
CV
IN +
C
123456789
10111213141516
AVDDVIN + GVIN – G
AVDDVIN – HVIN + H
AVDDAVDDCLK–CLK+AVDDAVDD
DRGNDDRVDD
D – HD + H
AVDDVIN + BVIN – BAVDDVIN – AVIN + AAVDDPDWNCSBSDIO/ODMSCLK/DTPAVDDDRGNDDRVDDD + AD – A
48474645444342414039383736353433
AD9252TOP VIEW
(Not to Scale)
EXPOSED PADDLE, PIN 0(BOTTOM OF PACKAGE)
NOTES1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND
Figure 5. 64-Lead LFCSP Pin Configuration, Top View
Table 7. Pin Function Descriptions Pin No. Mnemonic Description 0 AGND Analog Ground (Exposed Paddle) 1, 4, 7, 8, 11, 12, 37, 42, 45, 48, 51, 59, 62
AVDD 1.8 V Analog Supply
13, 36 DRGND Digital Output Driver Ground 14, 35 DRVDD 1.8 V Digital Output Driver Supply 2 VIN + G ADC G Analog Input True 3 VIN − G ADC G Analog Input Complement 5 VIN − H ADC H Analog Input Complement 6 VIN + H ADC H Analog Input True 9 CLK− Input Clock Complement 10 CLK+ Input Clock True 15 D − H ADC H Digital Output Complement 16 D + H ADC H Digital Output True 17 D − G ADC G Digital Output Complement 18 D + G ADC G Digital Output True 19 D − F ADC F Digital Output Complement 20 D + F ADC F Digital Output True 21 D − E ADC E Digital Output Complement 22 D + E ADC E Digital Output True 23 DCO− Data Clock Digital Output Complement 24 DCO+ Data Clock Digital Output True 25 FCO− Frame Clock Digital Output Complement 26 FCO+ Frame Clock Digital Output True 27 D − D ADC D Digital Output Complement 28 D + D ADC D Digital Output True 29 D − C ADC C Digital Output Complement 30 D + C ADC C Digital Output True 31 D − B ADC B Digital Output Complement
Data Sheet AD9252
Rev. E | Page 11 of 52
Pin No. Mnemonic Description 32 D + B ADC B Digital Output True 33 D − A ADC A Digital Output Complement 34 D + A ADC A Digital Output True 38 SCLK/DTP Serial Clock/Digital Test Pattern 39 SDIO/ODM Serial Data Input-Output/Output Driver Mode 40 CSB Chip Select Bar 41 PDWN Power-Down 43 VIN + A ADC A Analog Input True 44 VIN − A ADC A Analog Input Complement 46 VIN − B ADC B Analog Input Complement 47 VIN + B ADC B Analog Input True 49 VIN + C ADC C Analog Input True 50 VIN − C ADC C Analog Input Complement 52 VIN − D ADC D Analog Input Complement 53 VIN + D ADC D Analog Input True 54 RBIAS External Resistor to Set the Internal ADC Core Bias Current 55 SENSE Reference Mode Selection 56 VREF Voltage Reference Input/Output 57 REFB Negative Differential Reference 58 REFT Positive Differential Reference 60 VIN + E ADC E Analog Input True 61 VIN − E ADC E Analog Input Complement 63 VIN − F ADC F Analog Input Complement 64 VIN + F ADC F Analog Input True
AD9252 Data Sheet
Rev. E | Page 12 of 52
EQUIVALENT CIRCUITS
VIN ± x
0629
6-00
6
Figure 6. Equivalent Analog Input Circuit
10Ω
10kΩ
10kΩ
CLK–10Ω
1.25V
CLK+
0629
6-00
7
Figure 7. Equivalent Clock Input Circuit
SDIO/ODM350Ω
30kΩ
0629
6-00
8
Figure 8. Equivalent SDIO/ODM Input Circuit
DRVDD
DRGND
D – x D + x
V
V
V
V
0629
6-00
9
Figure 9. Equivalent Digital Output Circuit
SCLK/DTP OR PDWN30kΩ
1kΩ
0629
6-01
0
Figure 10. Equivalent SCLK/DTP or PDWN Input Circuit
100ΩRBIAS
0629
6-01
1
Figure 11. Equivalent RBIAS Circuit
Data Sheet AD9252
Rev. E | Page 13 of 52
CSB
70kΩ1kΩ
AVDD
0629
6-01
2
Figure 12. Equivalent CSB Input Circuit
SENSE1kΩ
0629
6-01
3
Figure 13. Equivalent SENSE Circuit
VREF
6kΩ
0629
6-01
4
Figure 14. Equivalent VREF Circuit
AD9252 Data Sheet
Rev. E | Page 14 of 52
TYPICAL PERFORMANCE CHARACTERISTICS 0
–1200 25
FREQUENCY (MHz)
AM
PLIT
UD
E (d
BFS
)
0629
6-04
8
–20
–40
–60
–80
–100
5 10 15 20
AIN = –0.5dBFSSNR = 73.71dBENOB = 11.95 BITSSFDR = 85.86dBc
Figure 15. Single-Tone 32k FFT with fIN = 2.3 MHz, fSAMPLE = 50 MSPS
0
–1200 25
FREQUENCY (MHz)
AM
PLIT
UD
E (d
BFS
)
0629
6-04
9
–20
–40
–60
–80
–100
5 10 15 20
AIN = –0.5dBFSSNR = 72.98dBENOB = 11.83 BITSSFDR = 83.8dBc
Figure 16. Single-Tone 32k FFT with fIN = 35 MHz, fSAMPLE = 50 MSPS
0
–1200 25
FREQUENCY (MHz)
AM
PLIT
UD
E (d
BFS
)
0629
6-05
0
–20
–40
–60
–80
–100
5 10 15 20
AIN = –0.5dBFSSNR = 72.36dBENOB = 11.73 BITSSFDR = 86.21dBc
Figure 17. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 50 MSPS
0
–1200 25
FREQUENCY (MHz)
AM
PLIT
UD
E (d
BFS
)
0629
6-05
1
–20
–40
–60
–80
–100
5 10 15 20
AIN = –0.5dBFSSNR = 71.16dBENOB = 11.53 BITSSFDR = 72.92dBc
Figure 18. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 50 MSPS
0629
6-03
9
ENCODE RATE (MSPS)
SNR
/SFD
R (d
B)
60
65
70
75
80
85
90
10 15 20 25 30 35 40 45 50
SNR
SFDR
Figure 19. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz, AD9252-50
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ENCODE RATE (MSPS)
SNR
/SFD
R (d
B)
60
65
70
75
80
85
90
10 15 20 25 30 35 40 45 50
SNR
SFDR
Figure 20. SNR/SFDR vs. fSAMPLE, fIN = 19.7 MHz, AD9252-50
Data Sheet AD9252
Rev. E | Page 15 of 52
10
20
30
40
50
60
70
80
90
–60 –50 –40 –30 –20 –10 0ANALOG INPUT LEVEL (dBFS)
SNR
/SFD
R (d
B)
SNR
SFDR
80dB REFERENCE
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1
Figure 21. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 50 MSPS
10
20
30
40
50
60
70
80
90
–60 –50 –40 –30 –20 –10 0ANALOG INPUT LEVEL (dBFS)
SNR
/SFD
R (d
B)
SNR
SFDR
80dB REFERENCE
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2
Figure 22. SNR/SFDR vs. Analog Input Level, fIN = 19.7 MHz, fSAMPLE = 50 MSPS
–120
–100
–80
–60
–40
–20
0
0 5 10 15 20 25FREQUENCY (MHz)
AM
PLIT
UD
E (d
BFS
)
AIN1 AND AIN2 = –7dBFSSFDR = 86.27dBIMD2 = 97.82dBcIMD3 = 86.13dBc
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Figure 23. Two-Tone 32k FFT with fIN1 = 15 MHz and
fIN2 = 16 MHz, fSAMPLE = 50 MSPS
–120
–100
–80
–60
–40
–20
0
AM
PLIT
UD
E (d
BFS
)
AIN1 AND AIN2 = –7dBFSSFDR = 83.64dBIMD2 = 95.57dBcIMD3 = 84.26dBc
0 5 10 15 20 25FREQUENCY (MHz) 06
296-
044
Figure 24. Two-Tone 32k FFT with fIN1 = 70 MHz and
fIN2 = 71 MHz, fSAMPLE = 50 MSPS
60
65
70
75
80
85
90
1 10 100 1000ANALOG INPUT FREQUENCY (MHz)
SNR
/SFD
R (d
B)
SNR
SFDR
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Figure 25. SNR/SFDR vs. fIN, fSAMPLE = 50 MSPS
60
65
70
75
80
85
90
–40 –20 0 20 40 60 80TEMPERATURE (°C)
SIN
AD
/SFD
R (d
B)
SFDR
SINAD
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Figure 26. SINAD/SFDR vs. Temperature, fIN = 19.7 MHz, fSAMPLE = 50 MSPS
AD9252 Data Sheet
Rev. E | Page 16 of 52
2.0
–2.00 16000
CODE
INL
(LSB
)
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1.5
1.0
0.5
0
–0.5
–1.0
–1.5
2000 4000 6000 8000 10000 12000 14000
Figure 27. INL, fIN = 2.3 MHz, fSAMPLE = 50 MSPS
1.0
–1.00 16000
CODE
DN
L (L
SB)
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0.8
0.6
0.2
0.4
0
–0.4
–0.2
–0.6
–0.8
2000 4000 6000 8000 10000 12000 14000
Figure 28. DNL, fIN = 2.3 MHz, fSAMPLE = 50 MSPS
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FREQUENCY (MHz)
CM
RR
(dB
)
–70
–65
–60
–55
–50
–45
–40
–35
–30
0 5 10 15 20 25 30 35 40
Figure 29. CMRR vs. Frequency, fSAMPLE = 50 MSPS
CODE
NU
MB
ER O
F H
ITS
(Mill
ions
)
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0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3
1.047LSB rms
Figure 30. Input-Referred Noise Histogram, fSAMPLE = 50 MSPS
AM
PLIT
UD
E (d
BFS
)
–120
0
–20
–40
–60
–80
–100
0 5 10 15 20 25FREQUENCY (MHz)
NPR = 62.5dBNOTCH = 18.0MHzNOTCH WIDTH = 2.3MHz
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Figure 31. Noise Power Ratio (NPR), fSAMPLE = 50 MSPS
0
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0 50045040035030025020015010050
AM
PLIT
UD
E (d
BFS
)
FREQUENCY (MHz)
–3dB BANDWIDTH = 325MHz
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Figure 32. Full-Power Bandwidth vs. Frequency, fSAMPLE = 50 MSPS
Data Sheet AD9252
Rev. E | Page 17 of 52
THEORY OF OPERATION The AD9252 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The data is then serialized and aligned to the frame and data clocks.
ANALOG INPUT CONSIDERATIONS The analog input to the AD9252 is a differential switched-capacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. An input common-mode voltage of midsupply minimizes signal-dependent errors and provides optimum performance.
S S
HCPAR
CSAMPLE
CSAMPLE
CPAR
VIN – x
H
S S
HVIN + x
H
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Figure 33. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between sample mode and hold mode (see Figure 33). When the input circuit is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low-Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and therefore achieve the maximum bandwidth of the ADC. Such use of low-Q inductors or ferrite beads is required when driving the converter
front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; the AN-827 Application Note, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article “Transformer-Coupled Front-End for Wideband A/D Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application.
The analog inputs of the AD9252 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 34 and Figure 35.
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ANALOG INPUT COMMON-MODE VOLTAGE (V)
SNR
/SFD
R (d
B)
60
65
70
75
80
85
90
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
SNR (dB)
SFDR (dBc)
Figure 34. SNR/SFDR vs. Common-Mode Voltage,
fIN = 2.3 MHz, fSAMPLE = 50 MSPS
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ANALOG INPUT COMMON-MODE VOLTAGE (V)
SNR
/SFD
R (d
B)
60
65
70
75
80
85
90
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
SNR (dB)
SFDR (dBc)
Figure 35. SNR/SFDR vs. Common-Mode Voltage,
fIN = 35 MHz, fSAMPLE = 50 MSPS
AD9252 Data Sheet
Rev. E | Page 18 of 52
For best dynamic performance, the source impedances driving VIN + x and VIN − x should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates the positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as
REFT = 1/2 (AVDD + VREF) REFB = 1/2 (AVDD − VREF) Span = 2 × (REFT − REFB) = 2 × VREF
It can be seen from these equations that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage.
Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9252, the largest input span available is 2 V p-p.
Differential Input Configurations
There are several ways to drive the AD9252 either actively or passively; however, optimum performance is achieved by driving the analog input differentially. For example, using the AD8334 differential driver to drive the AD9252 provides excellent perfor-mance and a flexible interface to the ADC (see Figure 39) for baseband applications. This configuration is commonly used for medical ultrasound systems.
For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration (see Figure 36 and Figure 37), because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9252.
Regardless of the configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed.
2Vp-p
R
R
CDIFF1
C
1CDIFF IS OPTIONAL.
49.9Ω
0.1μF
1kΩ
1kΩ
AGNDAVDD
ADT1-1WT1:1 Z RATIO
VIN – x
ADCAD9252
VIN + x
C
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Figure 36. Differential Transformer-Coupled Configuration
for Baseband Applications
ADCAD9252
2Vp-p
2.2pF 1kΩ
0.1μF
1kΩ
1kΩ
AVDD
ADT1-1WT1:1 Z RATIO16nH 16nH0.1μF
16nH
33Ω
33Ω
499Ω65Ω
VIN+x
VIN–x
06
296-
019
Figure 37. Differential Transformer-Coupled Configuration for IF Applications
Single-Ended Input Configuration
A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common-mode swing. If the application requires a single-ended input configuration, ensure that the source impedances on each input are well matched in order to achieve the best possible performance. A full-scale input of 2 V p-p can still be applied to the ADC’s VIN + x pin while the VIN − x pin is terminated. Figure 38 details a typical single-ended input configuration.
2V p-p
R
R
49.9Ω 0.1µF
0.1µF
AVDD
1kΩ 25Ω
1kΩ
1kΩ
1kΩ
AVDD
VIN – x
ADCAD9252
VIN + x
CDIFF1
C
1CDIFF IS OPTIONAL.
C
062
96-
020
Figure 38. Single-Ended Input Configuration
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AD8334 1.0kΩ
1.0kΩ
374Ω
187Ω R
R
C
0.1μF
187Ω
0.1μF
0.1μF0.1μF
0.1μF 10μF
0.1μF
1V p-p0.1μF
LNA
120nH
VGA
VOH
VIP
INH
22pF
LMD
VIN
LOP
LON
VOL
18nF 274Ω
VIN – x
ADCAD9252
VIN + x
1kΩ
1kΩ
AVDD
Figure 39. Differential Input Configuration Using the AD8334
Data Sheet AD9252
Rev. E | Page 19 of 52
CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9252 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional biasing.
Figure 40 shows the preferred method for clocking the AD9252. The low jitter clock source is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9252 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9252, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance.
0.1µF
0.1µF
0.1µF0.1µF
SCHOTTKYDIODES:HSM2812
CLK+50Ω 100Ω
CLK–
CLK+ADC
AD9252
Mini-Circuits®ADT1-1WT, 1:1Z
XFMR
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Figure 40. Transformer-Coupled Differential Clock
Another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 41. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515 family of clock drivers offers excellent jitter performance.
100Ω0.1µF
0.1µF0.1µF
0.1µF
240Ω240Ω
AD9510/AD9511/AD9512/AD9513/AD9514/AD9515
50Ω1 50Ω1CLK
CLK
150Ω RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADCAD9252PECL DRIVER
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CLK+
CLK–
Figure 41. Differential PECL Sample Clock
100Ω0.1µF
0.1µF0.1µF
0.1µF
50Ω1
LVDS DRIVER
50Ω1CLK
CLK
150Ω RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADCAD9252
AD9510/AD9511/AD9512/AD9513/AD9514/AD9515
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CLK+
CLK–
Figure 42. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 43). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages of up to 3.3 V, making the selection of the drive logic voltage very flexible.
0.1µF
0.1µF
0.1µF
39kΩ
CMOS DRIVER50Ω1
OPTIONAL100Ω
0.1µFCLK
CLK
150Ω RESISTOR IS OPTIONAL.
CLK–
CLK+
ADCAD9252
AD9510/AD9511/AD9512/AD9513/AD9514/AD9515
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CLK+
Figure 43. Single-Ended 1.8 V CMOS Sample Clock
0.1µF
0.1µF
0.1µF
CMOS DRIVER50Ω1
OPTIONAL100Ω
CLK
CLK
150Ω RESISTOR IS OPTIONAL.
0.1µFCLK–
CLK+
ADCAD9252
AD9510/AD9511/AD9512/AD9513/AD9514/AD9515
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CLK+
Figure 44. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9252 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9252. When the DCS is on, noise and distortion perfor-mance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the Memory Map section for more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate.
AD9252 Data Sheet
Rev. E | Page 20 of 52
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 45).
The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9252. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs.
1 10 100 1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps0.25ps
0.5ps1.0ps2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
SNR
(dB
)
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Figure 45. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 46, the power dissipated by the AD9252 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers.
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ENCODE (MSPS)
CU
RR
ENT
(A)
10 500
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
15 20 25 30 35 40 450.50
0.55
0.60
0.65
0.70
0.75
0.80
POW
ER (W
)
TOTAL POWER
AVDD CURRENT
DRVDD CURRENT
Figure 46. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 50 MSPS
Data Sheet AD9252
Rev. E | Page 21 of 52
By asserting the PDWN pin high, the AD9252 is placed into power-down mode. In this state, the ADC typically dissipates 11 mW. During power-down, the LVDS output drivers are placed into a high impedance state. The AD9252 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant.
In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode: shorter cycles result in proportionally shorter wake-up times. With the recommended 0.1 µF and 4.7 µF decoupling capacitors on REFT and REFB, approximately 1 sec is required to fully discharge the reference buffer decoupling capacitors and approximately 375 µs is required to restore full operation.
There are several other power-down options available when using the SPI. The user can individually power down each channel or put the entire device into standby mode. The latter option allows the user to keep the internal PLL powered when fast wake-up times (~600 ns) are required. See the Memory Map section for more details on using these features.
Digital Outputs and Timing
The AD9252 differential outputs conform to the ANSI-644 LVDS standard by default upon power-up. This can be changed to a low power, reduced signal option (similar to the IEEE 1596.3 standard) via the SDIO/ODM pin or the SPI. This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW. See the SDIO/ODM Pin section or Table 16 in the Memory Map section for more information. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver.
The AD9252 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. If there is no far-end receiver termination or there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is
recommended that the trace length be no longer than 24 inches and that the differential output traces be kept close together and at equal lengths. An example of the FCO and data stream when the AD9252 is used with traces of proper length and position is shown in Figure 47.
CH1 500mV/DIV = FCOCH2 500mV/DIV = DCOCH3 500mV/DIV = DATA
5.0ns/DIV
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Figure 47. LVDS Output Timing Example in ANSI-644 Mode (Default)
An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on standard FR-4 material is shown in Figure 48. Figure 49 shows an example of the trace length exceeding 24 inches on standard FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. It is the user’s responsibility to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (increasing the current) of all eight outputs in order to drive longer trace lengths (see Figure 50). Even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. In addition, notice in Figure 50 that the histogram has improved.
In cases that require increased driver strength to the DCO± and FCO± outputs because of load mismatch, Register 0x15 allows the user to increase the drive strength by 2×. To do this, first set the appropriate bit in Register 0x05. Note that this feature cannot be used with Bit 4 and Bit 5 in Register 0x15. Bit 4 and Bit 5 take precedence over this feature. See the Memory Map section for more details.
AD9252 Data Sheet
Rev. E | Page 22 of 52
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns–1.5ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns
EYE
DIA
GR
AM
VO
LTA
GE
(mV)
EYE: ALL BITS ULS: 12071/12071
90
50
10
20
30
40
60
70
80
0–150ps –100ps –50ps 0ps 50ps 100ps 150ps
TIE
JITT
ER H
ISTO
GR
AM
(Hits
)
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Figure 48. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less Than 24 Inches on Standard FR-4
60
80
90
70
50
40
20
10
100
30
0–200ps –100ps 100ps0ps 200ps
TIE
JITT
ER H
ISTO
GR
AM
(Hits
)
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns –0.5ns 0ns 0.5ns 1.5ns–1.5ns 1.0ns
EYE
DIA
GR
AM
VO
LTA
GE
(mV)
EYE: ALL BITS ULS: 12067/12067
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Figure 49. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater Than 24 Inches on Standard FR-4
400
300
200
100
–400
–300
–200
–100
0
–0.5ns 0ns 0.5ns
EYE
DIA
GR
AM
VO
LTA
GE
(mV)
EYE: ALL BITS ULS: 12072/12072
80
50
10
20
30
40
60
70
0–150ps –100ps –50ps 0ps 50ps 100ps 150ps
TIE
JITT
ER H
ISTO
GR
AM
(Hits
)
–1.0ns 1.5ns–1.5ns 1.0ns
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Figure 50. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω
Termination On and Trace Lengths Greater Than 24 Inches on Standard FR-4
The format of the output data is offset binary by default. An example of the output coding format can be found in Table 8. To change the output data format to twos complement, see the Memory Map section.
Table 8. Digital Output Coding
Code (VIN + x) − (VIN − x), Input Span = 2 V p-p (V)
Digital Output Offset Binary (D13 ... D0)
16383 +1.00 11 1111 1111 1111 8192 0.00 10 0000 0000 0000 8191 −0.000122 01 1111 1111 1111 0 −1.00 00 0000 0000 0000
Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 14 bits times the sample clock rate, with a maximum of 700 Mbps (14 bits × 50 MSPS = 700 Mbps). The lowest typical conversion rate is 10 MSPS. However, if lower sample rates are required for a specific application, the PLL can be set up via the SPI to allow encode rates as low as 5 MSPS. See the Memory Map section for information about enabling this feature.
Data Sheet AD9252
Rev. E | Page 23 of 52
Two output clocks are provided to assist in capturing data from the AD9252. The DCO is used to clock the output data and is equal to seven times the sample clock (CLK) rate. Data is clocked out of the AD9252 and must be captured on the rising and
falling edges of the DCO that supports double data rate (DDR) capturing. The FCO is used to signal the start of a new output byte and is equal to the sample clock rate. See the timing diagram shown in Figure 2 for more information.
Table 9. Flexible Output Test Modes
Output Test Mode Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2
Subject to Data Format Select
0000 Off (default) N/A N/A N/A 0001 Midscale short 1000 0000 (8-bit)
10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit)
Same Yes
0010 +Full-scale short 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit)
Same Yes
0011 −Full-scale short 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit)
Same Yes
0100 Checkerboard 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit)
0101 0101 (8-bit) 01 0101 0101 (10-bit) 0101 0101 0101 (12-bit) 01 0101 0101 0101 (14-bit)
No
0101 PN sequence long1 N/A N/A Yes 0110 PN sequence short1 N/A N/A Yes 0111 One-/zero-word toggle 1111 1111 (8-bit)
11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit)
0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit)
No
1000 User input Register 0x19 and Register 0x1A Register 0x1B and Register 0x1C No 1001 1-/0-bit toggle 1010 1010 (8-bit)
10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit)
N/A No
1010 1× sync 0000 1111 (8-bit) 00 0001 1111 (10-bit) 0000 0011 1111 (12-bit) 00 0000 0111 1111 (14-bit)
N/A No
1011 One bit high 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit)
N/A No
1100 Mixed frequency 1010 0011 (8-bit) 10 0110 0011 (10-bit) 1010 0011 0011 (12-bit) 10 1000 0110 0111 (14-bit)
N/A No
1 All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.
AD9252 Data Sheet
Rev. E | Page 24 of 52
When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO− timing, as shown in Figure 2, is 90° relative to the output data edge.
An 8-, 10-, and 12-bit serial stream can also be initiated from the SPI. This allows the user to implement different serial stream to test the device’s compatibility with lower and higher resolution systems. When changing the resolution to an 8-, 10-, or 12-bit serial stream, the data stream is shortened. See Figure 3 for a 12-bit example.
When the SPI is used, the data outputs can be inverted from their nominal state. This is not to be confused with inverting the serial stream to an LSB-first mode. In default mode, as shown in Figure 2, the MSB is first in the data output serial stream. However, this can be inverted so that the LSB is first in the data output serial stream (see Figure 4).
There are 12 digital output test pattern options available that can be initiated through the SPI. This feature is useful when validating receiver capture and timing. Refer to Table 9 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some patterns do not adhere to the data format select option. In addition, customer user-defined test patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.
The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 − 1 or 511 bits. A description of the PN sequence and how it is generated can be found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The only difference is that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values).
The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 − 1 or 8,388,607 bits. A description of the PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values) and the AD9252 inverts the bit stream with relation to the ITU standard.
Table 10. PN Sequence
Sequence Initial Value
First Three Output Samples (MSB First)
PN Sequence Short 0x0df 0x37e4, 0x3533, 0x0063 PN Sequence Long 0x26e028 0x191f, 0x35c2, 0x2359
SDIO/ODM Pin
The SDIO/ODM pin is for use in applications that do not require SPI mode operation. This pin can enable a low power, reduced signal option (similar to the IEEE 1596.3 reduced range link output standard) if it and the CSB pin are tied to AVDD during device power-up. This option should only be used when the digital output trace lengths are less than 2 inches from the LVDS receiver. When this option is used, the FCO, DCO, and outputs function normally, but the LVDS signal swing of all channels is reduced from 350 mV p-p to 200 mV p-p, allowing the user to further reduce the power on the DRVDD supply.
For applications where this pin is not used, it should be tied low. In this case, the device pin can be left open, and the 30 kΩ internal pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant. If applications require this pin to be driven from a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current.
Table 11. Output Driver Mode Pin Settings
Selected ODM ODM Voltage Resulting Output Standard
Resulting FCO and DCO
Normal Operation
AGND (10 kΩ pull-down resistor)
ANSI-644 (default)
ANSI-644 (default)
ODM AVDD Low power, reduced signal option
Low power, reduced signal option
SCLK/DTP Pin
The SCLK/DTP pin is for use in applications that do not require SPI mode operation. This pin can enable a single digital test pattern if it and the CSB pin are held high during device power-up. When the SCLK/DTP is tied to AVDD, the ADC channel outputs shift out the following pattern: 10 0000 0000 0000. The FCO and DCO function normally while all channels shift out the repeatable test pattern. This pattern allows the user to perform timing alignment adjustments among the FCO, DCO, and output data. For normal operation, this pin should be tied to AGND through a 10 kΩ resistor. This pin is both 1.8 V and 3.3 V tolerant.
Table 12. Digital Test Pattern Pin Settings
Selected DTP DTP Voltage Resulting D + x and D − x
Resulting FCO and DCO
Normal Operation
AGND (10 kΩ pull-down resistor)
Normal operation
Normal operation
DTP AVDD 10 0000 0000 0000
Normal operation
Additional and custom test patterns can also be observed when commanded from the SPI port. Consult the Memory Map section for information about the options available.
Data Sheet AD9252
Rev. E | Page 25 of 52
CSB Pin
The CSB pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. This pin is both 1.8 V and 3.3 V tolerant.
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor that is nominally equal to 10.0 kΩ between the RBIAS pin and ground. The resistor current is derived on chip and sets the AVDD current of the ADC to a nominal 360 mA at 50 MSPS. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance.
Voltage Reference
A stable, accurate 0.5 V voltage reference is built into the AD9252. This is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span of 2 V p-p. VREF is set internally by default; however, the VREF pin can be driven externally with a 1.0 V reference to improve accuracy.
When applying the decoupling capacitors to the VREF, REFT, and REFB pins, use ceramic low-ESR capacitors. These capacitors should be close to the ADC pins and on the same layer of the PCB as the AD9252. The recommended capacitor values and configurations for the AD9252 reference pin are shown in Figure 51.
Table 13. Reference Settings
Selected Mode
SENSE Voltage
Resulting VREF (V)
Resulting Differential Span (V p-p)
External Reference
AVDD N/A 2 × external reference
Internal, 2 V p-p FSR
AGND to 0.2 V 1.0 2.0
Internal Reference Operation
A comparator within the AD9252 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 51), setting VREF to 1 V.
The REFT and REFB pins establish their input span of the ADC core from the reference configuration. The analog input full-scale range of the ADC equals twice the voltage at the reference pin for either an internal or an external reference configuration.
If the reference of the AD9252 is used to drive multiple converters to improve gain matching, the loading of the refer-ence by the other converters must be considered. Figure 53 depicts how the internal reference voltage is affected by loading.
1µF 0.1µF
VREF
SENSE
0.5V
REFT
0.1µF0.1µF 4.7µF
0.1µF
REFB
SELECTLOGIC
ADCCORE
+
VIN – x
VIN + x
0629
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1
Figure 51. Internal Reference Configuration
1µF1 0.1µF1
VREF
SENSE
AVDD0.5V
REFT
0.1µF0.1µF 4.7µF
0.1µF
REFB
SELECTLOGIC
ADCCORE
+
VIN – x
VIN + x
EXTERNALREFERENCE
1OPTIONAL. 0629
6-03
2
Figure 52. External Reference Operation
0 1.00.5 2.01.5 3.02.5 3.5
VREF
ER
RO
R (%
)
CURRENT LOAD (mA)
0629
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1
–30
–5
–10
–15
–20
–25
5
0
Figure 53. VREF Accuracy vs. Load
AD9252 Data Sheet
Rev. E | Page 26 of 52
External Reference Operation
The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac-teristics. Figure 54 shows the typical drift characteristics of the internal reference in 1 V mode.
When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external reference is loaded with an equivalent 6 kΩ load. An internal reference buffer generates the positive and negative full-scale references, REFT and REFB, for the ADC core. Therefore, the external reference must be limited to a nominal voltage of 1.0 V.
0.02
–0.18
–0.14
–0.10
–0.06
–0.02
–0.16
–0.12
–0.08
–0.04
0
–40
VREF
ER
RO
R (%
)
TEMPERATURE (°C) 0629
6-06
0
–20 0 20 40 60 80
Figure 54. Typical VREF Drift
Data Sheet AD9252
Rev. E | Page 27 of 52
SERIAL PORT INTERFACE (SPI) The AD9252 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This may provide the user with additional flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, as documented in the Memory Map section. Detailed operational information can be found in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
Three pins define the SPI: the SCLK, SDIO, and CSB pins (see Table 14). The SCLK pin is used to synchronize the read and write data presented to the ADC. The SDIO pin is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB pin is an active low control that enables or disables the read and write cycles.
Table 14. Serial Port Pins Pin Function SCLK Serial Clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes. SDIO Serial Data Input/Output. A dual-purpose pin that typically
serves as an input or output, depending on the instruction sent and the relative position in the timing frame.
CSB Chip Select Bar (Active Low). This control gates the read and write cycles.
The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions can be found in Figure 56 and Table 15.
During normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to execute instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data.
When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without requiring additional instructions.
Regardless of the mode, if CSB is taken high in the middle of a byte transfer, the SPI state machine is reset and the device waits for a new instruction.
In addition to the operation modes, the SPI port configuration influences how the AD9252 operates. For applications that do not require a control port, the CSB line can be tied and held high. This places the remainder of the SPI pins into their secondary modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin sections. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, the user should ensure that the serial port remains synchronized with the CSB line when using this mode. When operating in 2-wire mode, it is recommended that a 1-, 2-, or 3-byte transfer be used exclusively. Without an active CSB line, streaming mode can be entered but not exited.
In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pin to change from an input to an output at the appropriate point in the serial frame.
Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
HARDWARE INTERFACE The pins described in Table 14 constitute the physical interface between the user’s programming device and the serial port of the AD9252. The SCLK and CSB pins function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback.
If multiple SDIO pins share a common connection, care should be taken to ensure that proper VOH levels are met. Assuming the same load for each AD9252, Figure 55 shows the number of SDIO pins that can be connected together and the resulting VOH level.
This interface is flexible enough to be controlled by either serial PROMs or PIC microcontrollers, providing the user with an alternative method, other than a full SPI controller, to program the ADC (see the AN-812 Application Note).
If the user chooses not to use the SPI, these dual-function pins serve their secondary functions when the CSB is strapped to AVDD during device power-up. See the Theory of Operation section for details on which pin-strappable functions are supported on the SPI pins.
AD9252 Data Sheet
Rev. E | Page 28 of 52
0629
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59
NUMBER OF SDIO PINS CONNECTED TOGETHER
VO
H(V
)
1.715
1.720
1.725
1.730
1.735
1.740
1.745
1.750
1.755
1.760
1.765
1.770
1.775
1.780
1.785
1.790
1.795
1.800
0 302010 40 50 60 70 80 90 100
Figure 55. SDIO Pin Loading
DON’T CARE
DON’T CAREDON’T CARE
DON’T CARE
SDIO
SCLK
CSB
tS tDH
tHI tCLK
tLO
tDS tH
R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0
062
96-
03
3
Figure 56. Serial Timing Details
Table 15. Serial Timing Definitions Parameter Timing (Minimum, ns) Description tDS 5 Setup time between the data and the rising edge of SCLK tDH 2 Hold time between the data and the rising edge of SCLK tCLK 40 Period of the clock tS 5 Setup time between CSB and SCLK tH 2 Hold time between CSB and SCLK tHI 16 Minimum period that SCLK should be in a logic high state tLO 16 Minimum period that SCLK should be in a logic low state tEN_SDIO 10 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 56) tDIS_SDIO 10 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 56)
Data Sheet AD9252
Rev. E | Page 29 of 52
MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map register table (Table 16) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x04, Address 0x05, and Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x22).
The leftmost column of the memory map indicates the register address number; the default value is shown in the second right-most column. The Bit 7 column is the start of the default hexadecimal value given. For example, Address 0x09, the clock register, has a default value of 0x01, meaning Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing 0 to Bit 0 of this address followed by writing 0x01 in Register 0xFF (transfer bit), the duty cycle stabilizer turns off. It is important to follow each writing sequence with a transfer bit to update the SPI registers. All registers, except Register 0x00, Register 0x04, Register 0x05, and Register 0xFF, are buffered with a master-slave latch and require writing to the transfer bit. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
RESERVED LOCATIONS Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have 0 written to their registers during power-up.
DEFAULT VALUES When the AD9252 comes out of a reset, critical registers are preloaded with default values. These values are indicated in Table 16, where an X refers to an undefined feature.
LOGIC LEVELS An explanation of various registers follows: “bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.”
AD9252 Data Sheet
Rev. E | Page 30 of 52
Table 16. Memory Map Register1
Addr. (Hex) Parameter Name
(MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB) Bit 0
Default Value (Hex)
Notes/ Comments
Chip Configuration Registers 00 chip_port_config 0 LSB first
1 = on 0 = off (default)
Soft reset 1 = on 0 = off (default)
1 1 Soft reset 1 = on 0 = off (default)
LSB first 1 = on 0 = off (default)
0 0x18 The nibbles should be mirrored so that LSB- or MSB-first mode is set correctly regardless of shift mode.
01 chip_id 8-bit Chip ID Bits [7:0] (AD9252 = 0x09), (default)
Read only
Default is unique chip ID, different for each device. This is a read-only register.
02 chip_grade X Child ID [6:4] (identify device variants of Chip ID) 011 = 50 MSPS
X X X X Read only
Child ID used to differentiate graded devices.
Device Index and Transfer Registers 04 device_index_2 X X X X Data
Channel H 1 = on (default) 0 = off
Data Channel G 1 = on (default) 0 = off
Data Channel F 1 = on (default) 0 = off
Data Channel E 1 = on (default) 0 = off
0x0F Bits are set to determine which on-chip device receives the next write command.
05 device_index_1 X X Clock Channel DCO 1 = on 0 = off (default)
Clock Channel FCO 1 = on 0 = off (default)
Data Channel D 1 = on (default) 0 = off
Data Channel C 1 = on (default) 0 = off
Data Channel B 1 = on (default) 0 = off
Data Channel A 1 = on (default) 0 = off
0x0F Bits are set to determine which on-chip device receives the next write command.
FF device_update X X X X X X X SW transfer 1 = on 0 = off (default)
0x00 Synchronously transfers data from the master shift register to the slave.
ADC Functions Registers 08 modes X X X X X Internal power-down mode
000 = chip run (default) 001 = full power-down 010 = standby 011 = reset
0x00 Determines various generic modes of chip operation.
09 clock X X X X X X X Duty cycle stabilizer 1 = on (default) 0 = off
0x01 Turns the internal duty cycle stabilizer on and off.
0D test_io User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once
Reset PN long gen 1 = on 0 = off (default)
Reset PN short gen 1 = on 0 = off (default)
Output test mode—see in the section
0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checkerboard output 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode)
0x00 When this register is set, the test data is placed on the output pins in place of normal data.
Data Sheet AD9252
Rev. E | Page 31 of 52
Addr. (Hex) Parameter Name
(MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB) Bit 0
Default Value (Hex)
Notes/ Comments
14 output_mode X 0 = LVDS ANSI-644 (default) 1 = LVDS low power, (IEEE 1596.3 similar)
X X X Output invert 1 = on 0 = off (default)
00 = offset binary (default) 01 = twos complement
0x00 Configures the outputs and the format of the data.
15 output_adjust X X Output driver termination 00 = none (default) 01 = 200 Ω 10 = 100 Ω 11 = 100 Ω
X X X DCO and FCO 2× drive strength 1 = on 0 = off (default)
0x00 Determines LVDS or other output properties. Primarily func-tions to set the LVDS span and common-mode levels in place of an external resistor.
16 output_phase X X X X 0011 = output clock phase adjust (0000 through 1010) 0000 = 0° relative to data edge 0001 = 60° relative to data edge 0010 = 120° relative to data edge 0011 = 180° relative to data edge (default) 0101 = 300° relative to data edge 0110 = 360° relative to data edge 1000 = 480° relative to data edge 1001 = 540° relative to data edge 1010 = 600° relative to data edge 1011 to 1111 = 660° relative to data edge
0x03 On devices that utilize global clock divide, this register determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected.
19 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB.
1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB.
1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB.
1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB.
21 serial_control LSB first 1 = on 0 = off (default)
X X X <10 MSPS, low encode rate mode 1 = on 0 = off (default)
000 = 14 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits
0x00 Serial stream control. Default causes MSB first and the native bit stream (global).
22 serial_ch_stat X X X X X X Channel output reset 1 = on 0 = off (default)
Channel power-down 1 = on 0 = off (default)
0x00 Used to power down individual sections of a converter (local).
1 X = an undefined feature.
AD9252 Data Sheet
Rev. E | Page 32 of 52
APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9252 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9252, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be routed to the AVDD first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD. The user can employ several different decoupling capacitors to cover both high and low frequencies. These capacitors should be located close to the point of entry at the PC board level and close to the parts with minimal trace lengths.
A single PC board ground plane should be sufficient when using the AD9252. With proper decoupling and smart parti-tioning of the PC board’s analog, digital, and clock sections, optimum performance can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9252. An exposed continuous copper plane on the PCB should mate to the AD9252 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides multiple tie points between the ADC and PCB during the reflow process, whereas using one continuous plane with no partitions guarantees only one tie point. See Figure 57 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).
SILKSCREEN PARTITIONPIN 1 INDICATOR
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Figure 57. Typical PCB Layout
Data Sheet AD9252
Rev. E | Page 33 of 52
EVALUATION BOARD The AD9252 evaluation board provides all the support cir-cuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially by using a transformer (default) or an AD8334 driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the drive circuitry of the AD8334. Each input configuration can be selected by changing the connections of various jumpers (see Figure 62 to Figure 66). Figure 58 shows the typical bench characterization setup used to evaluate the ac performance of the AD9252. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance.
See Figure 62 to Figure 72 for the complete schematics and layout diagrams demonstrating the routing and grounding techniques that should be applied at the system level.
POWER SUPPLIES This evaluation board has a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end of the supply is a 2.1 mm inner diameter jack that connects to the PCB at P701. Once on the PC board, the 6 V supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board.
When operating the evaluation board in a nondefault condition, L701 to L704 can be removed to disconnect the switching power supply. This enables the user to bias each section of the
board individually. Use P702 to connect a different supply for each section. At least one 1.8 V supply is needed for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for both analog and digital signals and that each supply have a current capability of 1 A. To operate the evaluation board using the VGA option, a separate 5.0 V analog supply (AVDD_5 V) is needed. To operate the evaluation board using the SPI and alternate clock options, a separate 3.3 V analog supply (AVDD_3.3 V) is needed in addition to the other supplies.
INPUT SIGNALS When connecting the clock and analog sources to the evaluation board, use clean signal generators with low phase noise, such as Rohde & Schwarz SMA or HP8644 signal generators or the equivalent, as well as a 1 m, shielded, RG-58, 50 Ω coaxial cable. Enter the desired frequency and amplitude from the ADC specifications tables. Typically, most Analog Devices, Inc., evalu-ation boards can accept approximately 2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 Ω terminations. Good choices of such band-pass filters are available from TTE, Allen Avionics, and K&L Microwave, Inc. The filter should be connected directly to the evaluation board if possible.
OUTPUT SIGNALS The default setup uses the Analog Devices HSC-ADC-FIFO5-INTZ to interface with the Analog Devices standard dual-channel FIFO data capture board (HCS-ADC-EVALCZ). Two of the eight channels can be evaluated at the same time. For more information on the channel settings and optional settings of these boards, visit www.analog.com/FIFO.
ROHDE & SCHWARZ,SMA,
2V p-p SIGNALSYNTHESIZER
ROHDE & SCHWARZ,SMA,
2V p-p SIGNALSYNTHESIZER
BAND-PASSFILTER
XFMRINPUT
CLK
CH A TO CH H14-BIT
SERIALLVDS
USBCONNECTION
AD9252EVALUATION BOARD
INTERPOSERBOARD
HSC-ADC-EVALCZFIFO DATACAPTURE
BOARD
PCRUNNING
ADCANALYZER
AND SPIUSER
SOFTWARE
1.8V– +– +
AV
DD
_DU
T
AV
DD
_3.3
V
DR
VD
D_D
UT
GN
D
GN
D
– +5.0V
GN
D
AV
DD
_5V
1.8V
6V DC2A MAX
WALL OUTLET100V AC TO 240V AC47Hz TO 63Hz
SWITCHINGPOWERSUPPLY
– +
GN
D
3.3V– +
VC
C
GN
D
3.3V
SPI SPISPI SPI
062
96-0
35
Figure 58. Evaluation Board Connection
AD9252 Data Sheet
Rev. E | Page 34 of 52
DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9252 Rev. A evaluation board.
Power: Connect the switching power supply that is provided with the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P701.
AIN: The evaluation board is set up for a transformer-coupled analog input with an optimum 50 Ω impedance match of 150 MHz of bandwidth (see Figure 59). For more bandwidth response, the differential capacitor across the analog inputs can be changed or removed. The common mode of the analog inputs is developed from the center tap of the transformer or AVDD_DUT/2.
0
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
0
–14
–12
–11
–10
–8
–6
–4
–2
50 100 150 200 250 300 350 400 450 500
–13
–9
–7
–5
–3
–1
–3dB CUTOFF = 186MHz
0629
6-0
36
Figure 59. Evaluation Board Full-Power Bandwidth
VREF: VREF is set to 1.0 V by tying the SENSE pin to ground, R317. This causes the ADC to operate in 2.0 V p-p full-scale range. A separate external reference option using the ADR510 is also included on the evaluation board. Populate R312 and R313, and remove C307. Proper use of the VREF options is noted in the Voltage Reference section.
RBIAS: RBIAS has a default setting of 10 kΩ (R301) to ground and is used to set the ADC core bias current.
Clock: The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T401) that adds a very low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs.
A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U401). Populate R406 and R407 with 0 Ω resistors, and remove R215 and R216 to disconnect the default clock path inputs. In addition, populate C205 and C206 with a 0.1 μF capacitor, and remove C409 and C410 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set to a default mode of operation. Consult the AD9515 data sheet for more information about these and other options.
In addition, an on-board oscillator is available on the OSC401 and can act as the primary clock source. The setup is quick and involves installing R403 with a 0 Ω resistor and setting the enable jumper (J401) to the on position. If the user wishes to employ a different oscillator, two oscillator footprint options are available (OSC401) to check the ADC performance.
PDWN: To enable the power-down feature, short J301 to the on position (AVDD) for the PDWN pin.
SCLK/DTP: To enable the digital test pattern on the digital outputs of the ADC, use J304. If J304 is tied to AVDD during device power-up, Test Pattern 10 0000 0000 0000 is enabled. See the SCLK/DTP Pin section for details.
SDIO/ODM: To enable the low power, reduced signal option (similar to the IEEE 1595.3 reduced range link LVDS output standard), use J303. If J303 is tied to AVDD during device power-up, it enables the LVDS outputs in a low power, reduced signal option from the default ANSI-644 standard. This option changes the signal swing from 350 mV p-p to 200 mV p-p, reducing the power of the DRVDD supply. See the SDIO/ODM Pin section for more details.
CSB: To enable processing of the SPI information on the SDIO and SCLK pins, tie J302 low in the always enable mode. To ignore the SDIO and SCLK information, tie J302 to AVDD.
Non-SPI Mode: For users who wish to operate the DUT without using the SPI, simply remove Jumpers J302, J303, and J304. This disconnects the CSB, SCLK/DTP, and SDIO/ODM pins from the control bus, allowing the DUT to operate in its simplest mode. Each of these pins has internal termination and will float to its respective level.
D + x, D − x: If an alternative data capture method to the setup shown in Figure 62 is used, optional receiver terminations, R318 and R320 to R328, can be installed next to the high speed backplane connector.
Data Sheet AD9252
Rev. E | Page 35 of 52
ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION The following is a brief description of the alternative analog input drive configuration using the AD8334 dual VGA. If this drive option is in use, some components may need to be populated, in which case all the necessary components are listed in Table 17. For more details on the AD8334 dual VGA, including how it works and its optional pin settings, consult the AD8334 data sheet.
To configure the analog input to drive the VGA instead of the default transformer option, the following components need to be removed and/or changed.
• Remove R102, R115, R128, R141, R161, R162, R163, R164, R202, R208, R218, R225, R234, R241, R252, R259, T101, T102, T103, T104, T201, T202, T203, and T204 in the default analog input path.
• Populate R101, R114, R127, R140, R201, R217, R233, and R251 with 0 Ω resistors in the analog input path.
• Populate R152, R153, R154, R155, R156, R157, R158, R159, R215, R216, R229, R230, R247, R248, R263, R264, C103, C105, C110, C112, C117, C119, C124, C126, C203, C205, C210, C212, C217, C219, C224, and C226 with 10 kΩ resistors to provide an input common-mode level to the ADC analog inputs.
• Populate R105, R113, R118, R124, R131, R137, R151, R160, R205, R213, R221, R222, R237, R238, R255, and R256 with 0 Ω resistors in the ADC analog input path to connect the VGA outputs.
• Remove R515, R520, R527, R532, R615, R620, R627, and R632 on the AD8334 analog outputs.
• Remove R512, R524, R612, and R624 to set the AD8334 mode and AD8334 HILO pin low. Some applications may require this to be different. Consult the AD8334 data sheet for more information on these functions.
In this configuration, L505 to L520 and L605 to L620 are populated with 0 Ω resistors to allow signal connection and use of a filter if additional requirements are necessary.
In this example, a 16 MHz, two-pole low-pass filter was applied to the AD8334 outputs. The following components need to be removed and/or changed:
• Remove L507, L508, L511, L512, L515, L516, L519, L520, L607, L608, L611, L612, L615, L616, L619, and L620 on the AD8334 analog outputs.
• Populate L507, L508, L511, L512, L515, L516, L519, L520, L607, L608, L611, L612, L615, L616, L619, and L620 with 680 nH inductors.
• Populate C543, C547, C551, C555, C643, C647, C651, and C655 with a 68 pF capacitor.
68pF680nH
680nH
0629
6-08
3
Figure 60. Example Filter Configured for16 MHz, Two-Pole Low-Pass Filter
0
–120
–100
–80
–60
–40
–20
0 5.0 7.52.5 10.0 15.0 17.512.5 20.0 22.5 25.0
AM
PLIT
UD
E (d
BFS
)
FREQUENCY (MHz) 0629
6-08
4
fSAMPLE = 50MSPSAIN = 3.5MHzAD8334 = MAX GAIN SETTING
Figure 61. AD9252 FFT Example Results Using
16 MHz, Two-Pole Low-Pass Filter Applied to the AD8334 Outputs (Analog Input Signal = −1.03 dBFS, SNR = 60.2 dBc, SFDR = 66.23 dBc)
AD9252 Data Sheet
Rev. E | Page 36 of 52
DN
PD
NP
DN
P
VG
A In
put
Ain
Ain
Ain
VG
A In
put
VG
A In
put
Con
nect
ion
Con
nect
ion
Con
nect
ion
Con
nect
ion
VG
A In
put
Cha
nnel
C
Ain
DN
P
Ain
Cha
nnel
A
Ain
AinC
hann
el B
Ain
Cha
nnel
D
R13
433
Ω
P10
5
P10
2
R14
81k
Ω
R16
0
0Ω−D
NP
R15
10Ω
−DN
P
R13
7
0Ω−D
NP
R13
10Ω
−DN
P
R12
4
0Ω−D
NP
R11
80Ω
−DN
P
R11
3
0Ω−D
NP
R10
50Ω
−DN
P
R10
10Ω
−DN
P
R14
00Ω
−DN
P
R12
70Ω
−DN
P
R11
40Ω
−DN
P
R10
7D
NP
1 256
T104
1 2 34
3456
T103
CM
3
1 256
T101
1 2 34
34 56
T102
1E
102
1E
101
DN
PC
127
10Ω
FB11
2
10Ω
FB11
110
ΩFB
110
10Ω
FB10
9
10Ω
FB10
8
10Ω
FB10
7
10Ω
FB10
6
10Ω
FB10
510
ΩFB
104
DN
PC
113
10Ω
FB10
3
10Ω
FB10
2
10Ω
FB10
1
DN
PC
106
2.2p
FC
118
DN
PC
124
VIN
_D
0.1µ
FC
114
0.1µ
FC
107
VIN
_D
VIN
_C
VIN
_B
VIN
_B
AV
DD
_DU
T
AV
DD
_DU
T
CM
2
CM
1
CH
_D
CH
_D
CM
3C
M1
INH
4INH
3IN
H1
CH
_A
CH
_AC
H_C
CM
4
AV
DD
_DU
T
AV
DD
_DU
TA
VD
D_D
UT
CM
4
AV
DD
_DU
T
INH
2
CH
_B
CH
_B
CM
2
CH
_C
R10
40Ω
R11
60Ω
R13
00Ω R14
30Ω
AV
DD
_DU
T
AV
DD
_DU
TA
VD
D_D
UT
AV
DD
_DU
T
AV
DD
_DU
T
AV
DD
_DU
TD
NP
C12
0
0.1µ
FC
128
0.1µ
FC
121
0.1µ
FC
101
2.2p
FC
125
DN
PC
117
DN
PC
126
DN
PC
119
DN
PC
112
0.1µ
FC
108
0.1µ
FC
109
0.1µ
FC
116
0.1µ
FC
115
0.1µ
FC
122
0.1µ
FC
123
DN
PC
110
2.2p
FC
111
DN
PC
103
2.2p
FC
104
DN
PC
105
0.1µ
FC
102
VIN
_A
VIN
_A
CM
1
CM
2
1E
103
1E
104
CM
3 CM
4
R13
51k
Ω
R12
31k
Ω
R10
91k
Ω
499Ω
R16
4
R16
349
9Ω
R16
249
9Ω
499Ω
R16
1
DN
PR
159
DN
PR
158
DN
PR
157
R15
6D
NP
R10
833
Ω
DN
PR
152
DN
PR
155
DN
PR
154
DN
PR
153
R10
264
.9Ω
R14
733
Ω
R14
633
Ω
R14
5D
NP
R14
91k
Ω
R13
633
Ω
R13
3D
NP
R13
2D
NP
R12
51K
Ω
R12
233
Ω
R12
133
Ω
R11
11k
Ω
R10
6D
NP
R11
21k
Ω
R15
01k
Ω
R13
91k
Ω
R13
81k
Ω
R12
61k
Ω
R11
033
Ω
R14
164
.9Ω
R14
20Ω
R12
864
.9Ω
R12
90Ω
R11
564
.9Ω
R11
70Ω
R10
30Ω
R14
4D
NP
R12
0D
NP
R11
9D
NP
P10
1
P10
6
P10
8
P10
7
P10
4
P10
3
VIN
_C
06296-072
DN
P: D
O N
OT
PO
PU
LATE
.
Figure 62. Evaluation Board Schematic, DUT Analog Inputs
Data Sheet AD9252
Rev. E | Page 37 of 52
DN
PD
NP
DN
P
VG
A In
put
Ain
Ain
Ain
Ain
VG
A In
put
VG
A In
put
VG
A In
put
Ain
Con
nect
ion
Con
nect
ion
Con
nect
ion
Con
nect
ion
Cha
nnel
E
DN
P
AinC
hann
el G
AinCha
nnel
HC
hann
el F
Ain
1 256
T204
R26
61k
Ω
10Ω
FB21
2
R26
51k
Ω
10Ω
FB20
910
ΩFB
207
R24
533
Ω
R24
0D
NP
1 25
34
346
T203
2.2p
FC
211
R23
1
1kΩ
10Ω
FB20
6
10Ω
FB20
3
1 256
T202
R22
00Ω
R25
7D
NP
R25
8D
NP
R22
4D
NP
R22
3D
NP
2.2p
FC
204
R20
7D
NP
R20
6D
NP
1 25
34
346
T201
10Ω
FB20
1
R26
21k
ΩR
256
0Ω−D
NP
R25
50Ω
−DN
P
R23
8
0Ω−D
NP
R23
70Ω
−DN
P
R22
2
0Ω−D
NP
R22
10Ω
−DN
P
R21
30Ω
−DN
P
R20
50Ω
−DN
P
R20
10Ω
−DN
P
R25
10Ω
−DN
P
R23
30Ω
−DN
P
R21
70Ω
−DN
P
CM
7
1E
202
1E
201
DN
PC
227
10Ω
FB21
110
ΩFB
210
10Ω
FB20
8
10Ω
FB20
510
ΩFB
204
DN
PC
213
10Ω
FB20
2
DN
PC
206
2.2p
FC
218
DN
PC
224
VIN
_H
0.1µ
F
C21
4
0.1µ
F
C20
7
VIN
_H
VIN
_G
VIN
_G
VIN
_F
VIN
_F
AV
DD
_DU
T
AV
DD
_DU
T
CM
6
CM
5
CH
_H
CH
_H
CM
7C
M5
INH
8INH
7IN
H5
CH
_E
CH
_EC
H_G
CM
8
AV
DD
_DU
T
AV
DD
_DU
TA
VD
D_D
UT
CM
8
AV
DD
_DU
T
INH
6
CH
_F
CH
_F
CM
6
CH
_G
R20
40Ω
R23
60Ω R25
40Ω
AV
DD
_DU
T
AV
DD
_DU
TA
VD
D_D
UT
AV
DD
_DU
T
AV
DD
_DU
T
AV
DD
_DU
TD
NP
C22
0
0.1µ
F
C22
8
0.1µ
F
C22
1
0.1µ
FC
201
2.2p
FC
225
DN
PC
217
DN
PC
226
DN
PC
219
DN
PC
212
0.1µ
FC
208
0.1µ
FC
209
0.1µ
FC
216
0.1µ
FC
215
0.1µ
FC
222
0.1µ
FC
223
DN
PC
210
DN
P
C20
3
DN
PC
205
0.1µ
FC
202
VIN
_E
VIN
_E
CM
5
CM
6
1E
203
1E
204
CM
7
CM
8
R24
61k
Ω
R22
81k
ΩR21
41k
Ω
499Ω
R25
9
R24
149
9Ω
R22
549
9Ω
499Ω
R20
8
DN
PR
263
DN
PR
247
DN
PR
229
R21
5D
NP
R20
933
ΩD
NP
R21
6
DN
PR
264
DN
PR
248
DN
PR
230
R20
264
.9Ω
R26
133
Ω
R26
033
Ω
R23
9D
NP
R22
733
Ω
R22
633
Ω
R21
11k
Ω R21
21k
ΩR
250
1kΩ
R24
91k
Ω
R23
21k
Ω
R21
033
Ω
R24
233
Ω
R25
264
.9Ω
R25
30Ω
R23
464
.9kΩ
R23
50Ω
R21
864
.9Ω
R21
90Ω
R20
30Ω
P20
1
P20
2
P20
5
P20
6
P20
8
P20
7P
203
P20
4
06296-073
DN
P: D
O N
OT
PO
PU
LATE
.
Figure 63. Evaluation Board Schematic, DUT Analog Inputs (Continued)
AD9252 Data Sheet
Rev. E | Page 38 of 52
4.7µ
F
CW
GND
VO
UT
TRIM
/NC
AD
9252
BC
PZ-
50
AV
DD
CLK
+
CLK
−
D+B
D+C
D+D
D+E
D+F
D+G
D+H
D−B
D−C
D−D
D−E
D−F
D−G
D−H
DCO+
DCO−
DR
GN
D
DR
VD
D
FCO+
FCO−
PD
WN
AV
DD
RBIAS
REFB
REFT
SC
LK/D
TP
SD
IO/O
DM
VIN
+A
VIN+C
VIN+D
VIN+E
VIN
+G
VIN
−A
VIN
−B
VIN−C
VIN−D
VIN−F
VIN
−G
VREF
VIN+F
SLUG
AVDD
AV
DD
AV
DD
DR
GN
D
VIN
−H
D+A
D−A
VIN
+B
CS
B
SENSE
VIN−E
VIN
+H
DR
VD
D
AV
DD
AV
DD
AV
DD
AVDD
AV
DD
AV
DD
AV
DD
AVDD
A1
A10
A2
A3
A4
A5
A6
A7
A8
A9
B1
B10 B
2
B3
B4
B5
B6
B7
B8
B9
C1
C10
C2
C3
C4
C5
C6
C7
C8
C9
D1
D10 D
2
D3
D4
D5
D6
D7
D8
D9
GN
DA
B1
GN
DA
B10
GN
DA
B2
GN
DA
B3
GN
DA
B4
GN
DA
B5
GN
DA
B6
GN
DA
B7
GN
DA
B8
GN
DA
B9
GN
DC
D1
GN
DC
D10
GN
DC
D2
GN
DC
D3
GN
DC
D4
GN
DC
D5
GN
DC
D6
GN
DC
D7
GN
DC
D8
GN
DC
D9
Opt
iona
l Out
put
Term
inat
ions
Dig
ital O
utpu
ts
usin
g ex
tern
al V
ref
VR
EF
= 1V
VR
EF
= E
xter
nal
VR
EF
= 0.
5V
Rem
ove
C21
4 w
hen
ALW
AY
S E
NA
BLE
SP
I
OD
M E
nabl
e
DT
P E
nabl
e
VR
EF
= 0.
5V(1
+ R
219/
R22
0)
Vre
f Sel
ect
1.0V
Ref
eren
ceD
ecou
plin
g
OP
TIO
NA
LE
XT
RE
F
PD
WN
EN
AB
LE
NC
Ref
eren
ceC
ircui
try
R31
8,R
320−
R32
8D
NP
R32
2C
HB
110 23456789
1120 1213141516171819
3140 3233343536373839
4150 4243444546474849
2130 22232425262728295160 5253545556575859
P30
1
CH
B
DN
PR
318
DN
PR
320
DN
PR
321
DN
PR
323
DN
PR
324
DN
PR
325
DN
PR
328
DN
PR
326
3
2
1J3
04
1
2
3J3
03
1
2
3J3
02
3
2
1J3
01
R31
9
1kΩ
AV
DD
_DU
T
AVDD_DUT
AVDD_DUT
VIN_E
VIN_E
VIN_F
VIN_F
1
59
4
424548
51
62
7 109 118
32
30
28
22
20
18
16
31
29
27
21
19
17
15
24
23
1336
143537
26
25
33344047
55
61
5 6
41
12
54
57
58
383943
49
53
60
2
4446
50
52
63
3
56
64
0
U30
1
R306100kΩ
R305100kΩ
R30
310
0kΩ
DN
PR
304
DNPR302
SC
LK_D
TP
SD
IO_O
DM
CS
B_D
UT
0.1µ
FC
305
4.99
kΩR
309
1µF
C30
7
C30
10.
1µF
C30
40.
1µF
C30
20.
1µF
AD
R51
0AR
TZ
U30
2
10kΩ
R31
0
DN
PR
311
R30710kΩ
VS
EN
SE
_DU
T
470k
ΩR
308
DN
PR
313
DN
PR
312
0ΩR31
7
DN
PR
31
DN
PR
315
DN
PR
314
R30110kΩ
0.1µ
FC
306
AV
DD
_DU
T
VR
EF_
DU
T
AVDD_DUT
AV
DD
_DU
T
DR
VD
D_D
UT
AV
DD
_DU
T
AVDD_DUT
AV
DD
_DU
T
CLK
CLK
CHB
CHC
CHD
CH
H
CHB
CHC
CHD
CH
H
DCO
DCO
GN
D
DR
VD
D_D
UT
FCO
FCO
VSENSE_DUT
VIN
_H
VIN
_H
VIN_C
VIN_D
VIN
_G
VIN_C
VIN_D
VIN
_G
VREF_DUT
CHG
CHG
CHF
CHF
CHE
CHE
AV
DD
_DU
T
AV
DD
_DU
T
GN
D
AV
DD
_DU
T
VIN
_A
VIN
_A
CH
A
CH
A
AV
DD
_DU
T
VIN
_B
VIN
_B
AV
DD
_DU
T
AV
DD
_DU
T
AV
DD
_DU
T
DN
PR
327
SC
LK_C
HA
SD
I_C
HA
CS
B1_
CH
A
CS
B2_
CH
A
SD
O_C
HA
SC
LK_C
HB
SD
I_C
HB
CS
B3_
CH
B
CS
B4_
CH
B
SD
O_C
HB
DC
O
FCO
CH
A
CH
C
CH
D
CH
E
CH
F
CH
G
CH
HC
HH
CH
G
CH
F
CH
E
CH
D
CH
C
CH
A
FCO
DC
O
C30
3
06296-074
DN
P: D
O N
OT
PO
PU
LATE
.
Figure 64. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface
Data Sheet AD9252
Rev. E | Page 39 of 52
CR
YS
TAL_
3
GN
DOE
OU
T
VC
C
OE
GN
DO
UT
VC
C
CLK
CLK
B
GND
GN
D_P
AD
OU
T0
OU
T0B
OU
T1
OU
T1B
RSET
S0
S1
S10
S2
S3
S4
S5
S6
S7
S8
S9
SY
NC
B
VREF
VS
SIG
NA
L=D
NC
;27,
28
DN
P
DN
P
DN
P
DN
P
DN
P
DN
P
DN
P
DN
P
Inpu
tE
ncod
e
Enc E
nc
Clo
ck C
ircui
t
DN
P
DN
P
DN
P
DN
P
DIS
AB
LE O
SC
401
EN
AB
LE O
SC
401
Opt
iona
l Clo
ckO
scill
ator
AD95
15 P
in−s
trap
setti
ngs
OPT
ION
AL C
LOC
K D
RIV
E C
IRC
UIT
LVP
EC
L O
UTP
UT
DN
P: D
O N
OT
PO
PU
LATE
.
DN
P
DN
P
DN
P
LVD
S O
UTP
UT
CLI
P S
INE
OU
T (D
EFA
ULT
)
DN
P
12
6
7
25
8
16
9
15
10
14
11
13
32 5
181923 22
32
1
31
33
U40
1
SIG
NA
L=A
VD
D_3
.3V
;4,1
7,20
,21,
24,2
6,29
,30
AD
9515
BC
PZ
0Ω
R43
0
R44
6
0Ω
R42
4
R42
8
0Ω
R42
5
0Ω
R42
7
0Ω
1
2
3 J401
10123 5 71
814O
SC
401
0Ω
R42
6S
0
0Ω
R43
6R
437
0Ω
10kΩ
R41
3
C40
10.
1µF
R40
110
kΩ
R40
30Ω D
NP
0.1µ
F514
C214
C0.
1µF
C41
6
C41
10.
1µF
0ΩR40
6
0ΩR41
5
10kΩ
R40
2
49.9
ΩR
411
R40
70Ω
0Ω
R43
4
C40
50.
1µF
DN
P
0.1µ
FC
406
DN
P
0.1µ
FC
407
DN
P
C40
80.
1µF
DN
P
R44
4
0Ω0Ω
R44
2
R44
0
0Ω0Ω
R43
8
R43
2
0Ω
0Ω
R44
5
R44
3
0Ω0Ω
R44
1
R43
9
0Ω
R43
5
0Ω0Ω
R43
3
R43
1
0Ω0Ω
R42
9
S4
1E
401
AV
DD
_3.3
V
0ΩR41
6
3
2
1
CR
401
HS
MS
-281
2-TR
1G
R41
44.
12kΩ
S5
S3
S2
S1
AV
DD
_3.3
V
R42
124
0Ω
C40
90.
1µF
R40
9D
NP
240Ω
R42
0
6543 2 1
T401
0.1µ
FC
402
C41
00.
1µF
49.9
ΩR
404
R41
010
kΩ
R41
2D
NP
DN
PR
408
R40
50Ω
C40
30.
1µF
100Ω
R42
3
R42
210
0Ω
R41
80ΩR41
70Ω
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
OP
T_C
LK
OP
T_C
LK
CLK
AV
DD
_3.3
V
OP
T_C
LK
OP
T_C
LK
CLK
CLK
CLK
AV
DD
_3.3
V
AV
DD
_3.3
V
AV
DD
_3.3
V
AV
DD
_3.3
V
AV
DD
_3.3
V
AV
DD
_3.3
VA
VD
D_3
.3V
AV
DD
_3.3
V
AV
DD
_3.3
V
AV
DD
_3.3
V
AV
DD
_3.3
V
S6
S7
S8
S9
S10
C41
30.
1µF
0.1µ
F814
C41 4
C0.
1µF
0.1µ
FC
417
AV
DD
_3.3
V
AV
DD
_3.3
V
P40
1
P40
2
06296-075
0.1µ
F
Figure 65. Evaluation Board Schematic, Clock Circuitry
AD9252 Data Sheet
Rev. E | Page 40 of 52
CWCW
AD
8334
AC
PZ-
RE
EL
INH
2
LMD
2
CO
M2X
LON
2
LOP
2
VIP
2
VIN
2
VP
S2
VP
S3
VIN
3
VIP
3
LOP
3
LON
3
CO
M3X
LMD
3
INH
3
COM4
INH4
LMD4
COM4X
LON4
LOP4
VIP4
VIN4
VPS4
HILO
MO
DE
VPS1
VIN1
VIP1
LOP1
LON1
COM1X
LMD1
INH1
COM1
NCNC
VO
L2
VO
H2
COM2
VCM2
COM3
VCM3V
OL3
VO
H3
VCM4
VO
H4
VO
L4
VO
L1
VO
H1
VCM1
GAIN12
CLMP12
EN12
CO
M12
VP
S12
CO
M12
EN34
CO
M34
VP
S34
CO
M34
CLMP34
GAIN34
EX
T V
G
ExternalVariable Gain Drive
Variable Gain Circuit(0−1.0V DC)
HIL
O P
in=H
=+/−
75m
VH
ILO
Pin
=LO
=+/−
50m
V
Rcl
amp
Pin
EX
T V
G
HIL
O P
in=H
=+/−
75m
VH
ILO
Pin
=LO
=+/−
50m
V
Rcl
amp
Pin
ExternalVariable Gain Drive
Variable Gain Circuit(0−1.0V DC)
resi
stor
s or
des
ign
your
ow
n fil
ter.
Pow
er D
own
Ena
ble
(0−1
V=D
isab
le P
ower
)
DN
P: D
O N
OT
PO
PU
LATE
.
MO
DE
Pin
Pos
itive
Gai
n S
lope
= 0
−1.0
VN
egiti
ve G
ain
Slo
pe =
2.2
5−5.
0V
Pop
ulat
e L5
05−L
520
with
0Ω
0.1µ
FC
537
0ΩL519
0ΩL515
374Ω
R53
237
4ΩR
527
DN
PR
522
DN
PR
517
0.1µ
FC
530
0.1µ
F
C52
9
0.1µ
FC
528
120nHL503
0.1µ
FC
524
0.1µ
F
C52
3
0.1µ
F
C51
8
374Ω
R51
5
10kΩR504
0.1µ
FC
504
62
61
60
59
58
57
56
55
54
53
52
51
50
49
3334353637383941424344454647
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16151413121110987654321
63
64
48 40
U50
1
0.1µ
F
C50
6
AV
DD
_5V 10kΩ
R51110kΩ
R512
10kΩR505 AVDD_5V
AV
DD
_5V
AV
DD
_5V
AVDD_5V
VG34
0.1µ
FC
538
AV
DD
_5V
AV
DD
_5V
0.1µFC505
22pFC503
VG12
C51210µF
AV
DD
_5V
AVDD_5V
0.1µFC501
187ΩR513
10kΩ
DN
P
R50
6
10kΩ
R50
1
274ΩR503
0.018µFC502
12
JP50
1
120nHL501
0.1µ
FC
508
0.1µFC509
1000
pFC
507
39kΩ
R50
2
C51010µF
AVDD_5V
VG12
VG12
GND
R52
1D
NP0ΩL5
10
R51
6D
NP
C54
2D
NP
187Ω
R51
818
7ΩR
514
0.1µ
FC
545
0.1µ
FC
541
0.1µ
FC
540
0ΩL505
0ΩL511
0ΩL508
0ΩL507
0ΩL509
0ΩL506
0ΩL512
374Ω
R52
0
187Ω
R51
9
0.1µ
FC
544
C54
6D
NP
C54
3D
NP
C54
7D
NP
CH
_CC
H_D
CH
_DC
H_C
DN
PR
534
R53
3D
NP0ΩL5
18
R52
8D
NP
C55
0D
NP
187Ω
R53
0
187Ω
R52
6
0.1µ
FC
553
0.1µ
FC
549
0.1µ
FC
548
0ΩL513
0ΩL516
0ΩL517
0ΩL514
0ΩL520
187Ω
R53
1
187Ω
R52
5
0.1µ
FC
552
C55
4D
NP
C55
1D
NP
C55
5D
NP
DN
PR
529
CH
_AC
H_B
CH
_BC
H_A
INH
4
0.1µFC511
22pFC514
0.1µFC513
120nHL502
INH
3
274ΩR507
0.018µFC515
0.1µ
FC
522
22pFC520
0.1µFC519
274ΩR508
0.018µFC521
INH
2
C52622pF
C5250.1µF
L504120nH
R509274Ω
C5270.018µF
INH
1
0.1µF0.1µFC536C535C534C533
10µF10µF
10kΩ
DN
P
R51
00.
1µF
C53
210
00pF
C53
1
10kΩ
R53
5
1JP
502
39kΩ
R53
6
AVDD_5V
VG34
VG34
GND
10kΩR523
10kΩR524
AV
DD
_5V
06296-076
2
Figure 66. Evaluation Board Schematic, Optional DUT Analog Input Drive
Data Sheet AD9252
Rev. E | Page 41 of 52
CWCW
AD
8334
AC
PZ-
RE
EL
INH
2
LMD
2
CO
M2X
LON
2
LOP
2
VIP
2
VIN
2
VP
S2
VP
S3
VIN
3
VIP
3
LOP
3
LON
3
CO
M3X
LMD
3
INH
3
COM4
INH4
LMD4
COM4X
LON4
LOP4
VIP4
VIN4
VPS4
HILO
MO
DE
VPS1
VIN1
VIP1
LOP1
LON1
COM1X
LMD1
INH1
COM1
NCNC
VO
L2
VO
H2
COM2
VCM2
COM3
VCM3
VO
L3
VO
H3
VCM4
VO
H4
VO
L4
VO
L1
VO
H1
VCM1
GAIN12
CLMP12
EN12
CO
M12
VP
S12
CO
M12
EN34
CO
M34
VP
S34
CO
M34
CLMP34
GAIN34
MO
DE
Pin
Pos
itive
Gai
n S
lope
= 0
−1.0
VN
egat
ive
Gai
n S
lope
= 2
.25−
5.0V
EX
T V
G
ExternalVariable Gain Drive
Variable Gain Circuit(0−1.0V DC)
HIL
O P
in=H
=+/−
75m
VH
ILO
Pin
=LO
=+/−
50m
VR
clam
p P
in
EX
T V
G
HIL
O P
in=H
=+/−
75m
VH
ILO
Pin
=LO
=+/−
50m
VR
clam
p P
in
ExternalVariable Gain Drive
Variable Gain Circuit(0−1.0V DC)
Pop
ulat
e L6
05−L
620
with
0Ω
resi
stor
s or
des
ign
your
ow
n fil
ter.
Pow
er D
own
Ena
ble
(0−1
V=D
isab
le P
ower
)
DN
P: D
O N
OT
PO
PU
LATE
.
62
61
60
59
58
57
56
55
54
53
52
51
50
49
3334353637383941424344454647
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16151413121110987654321
63
64
48 40
U60
1
374Ω
R62
0
DN
PR
636
374Ω
R63
237
4ΩR
627
DN
PR
622
0ΩL619
0ΩL611
0.1µ
FC
630
0.1µ
F
C62
9
0.1µ
FC
628
0.1µ
FC
624
0.1µ
F
C62
3
0.1µ
F
C61
8
0.1µ
FC
616
10kΩR604
0.1µ
FC
604
10kΩR612
10kΩ
R62
4
AVDD_5V
AV
DD
_5V
AV
DD
_5V
AVDD_5V
VG78
0.1µ
FC
617
AV
DD
_5V
AV
DD
_5V
0.1µFC605
22pFC603
0.1µ
F
C60
6
VG56
C61210µF
AV
DD
_5V
AVDD_5V
0.1µFC601
187ΩR613
10kΩ
DN
P
R60
6
10kΩ
R60
1
274ΩR603
0.018µFC602
12
JP60
1
L601120nH
0.1µ
FC
608
0.1µFC609
10kΩR605
1000
pFC
607
39kΩ
R60
2
C61010µF
AVDD_5V
VG56
VG56
GND
R62
1D
NP0ΩL6
10
R61
6D
NP
C64
2D
NP
374Ω
R61
5
187Ω
R61
818
7ΩR
614
0.1µ
FC
645
0.1µ
FC
641
0.1µ
FC
640
0ΩL605
0ΩL608
0ΩL607
0ΩL609
0ΩL606
0ΩL612
187Ω
R61
9
0.1µ
FC
644
C64
6D
NP
C64
3D
NP
C64
7D
NP
DN
PR
617
CH
_GC
H_H
CH
_HC
H_G
R63
3D
NP0ΩL6
18
R62
8D
NP
C65
0D
NP
187Ω
R63
018
7ΩR
626
0.1µ
FC
653
0.1µ
FC
649
0.1µ
FC
648
0ΩL613
0ΩL616
0ΩL615
0ΩL617
0ΩL614
0ΩL620
187Ω
R63
118
7ΩR
625
0.1µ
FC
652
C65
4D
NP
C65
1D
NP
C65
5D
NP
DN
PR
629
CH
_EC
H_F
CH
_FC
H_E
INH
8
0.1µFC611
22pFC614
0.1µFC613
L602120nH
INH
7
274ΩR607
0.018µFC615
0.1µ
FC
622
22pFC620
0.1µFC619
L603120nH
274ΩR608
C621
INH
6
C62622pF
C6250.1µF
L604120nH
R609274Ω
C6270.018µF
INH
5
0.1µF0.1µFC636
10µFC634C633
10µF
10kΩ
DN
P
R61
00.
1µF
C63
210
00pF
C63
1
10kΩ
R63
4
12
JP60
2
39kΩ
R63
5
AVDD_5V
VG78
VG78
GND
10kΩR611
AV
DD
_5V
10kΩ
R62
3AV
DD
_5V
C635
06296-077
0.018µF
Figure 67. Evaluation Board Schematic, Optional DUT Analog Input Drive (Continued)
AD9252 Data Sheet
Rev. E | Page 42 of 52
NA
NO
SM
DC
110F
-2
S2A
-TP
GP
0
GP
1G
P2
GP
4
GP
5
VD
DV
SS
MC
LR/G
P3
PIC
12F6
29-I/
SN
G4
Y1
VC
C Y2
A2
GN
D
A1
CO
N00
57.
5V P
OW
ER
2.5M
M J
AC
K
P1
P2
P3
P4
P5
P6
P7
P8
GND
GND
GND
GND
OU
T
Y1
VC
C Y2
A2
GN
D
A1
OPTIONAL
+3.3
V =
NO
RM
AL
OP
ER
ATI
ON
= A
VD
D_3
.3V
+5V
= P
RO
GR
AM
MIN
G =
AV
DD
_5V
RE
SE
T/ R
EP
RO
GR
AM
ISP
PIC
PR
OG
RA
MM
ING
HE
AD
ER
RE
MO
VE
WH
EN
US
ING
OR
PR
OG
RA
MM
ING
PIC
(U40
2)
SP
I CIR
CU
ITR
Y F
RO
M F
IFO
Pow
er S
uppl
y In
put
Inpu
t
6V,
2A m
ax
+5.0
V
DN
P: D
O N
OT
PO
PU
LATE
.
+1.8
V
+1.8
V
+3.3
V
Dec
oupl
ing
Cap
acito
rs
Opt
iona
l Pow
er
D70
2
6 5 4321
U70
3
NC
7WZ1
6P6X
_NL
3.3V
_AV
DD
5V_A
VD
D
DU
T_A
VD
D
DU
T_D
RV
DD
L701
10µH
AV
DD
_5V
1
23
4
U70
7 AD
P33
39A
KC
Z−1.
8-R
L
AV
DD
_5V
AV
DD
_DU
T
CR702
GREEN
MCLR/GP3
CR701
GREEN
423
1A
DP
3339
AK
CZ−
5-R
L7
U70
6
1
23
4
U70
4 AD
P33
39A
KC
Z−1.
8-R
L
423
1
AD
P33
39A
KC
Z−3.
3-R
L
U70
5
24
31
FER
701
1 2 3 4 5 6 7 8
P70
2D
NP
1
32
P70
1
1 2 3456
NC
7WZ0
7P6X
_NL
U70
2
1kΩ
R71
3
0ΩR709
R708 0Ω
0Ω
0ΩR706
2
4
6
8
109
7
5
3
1
J702
1 2
3S
701
43
7 6 5
2
81
U70
1
0.1µ
FC
726
0.1µ
FC
742
AV
DD
_DU
T
0.1µ
FC
730
D70
1
F701
AV
DD
_3.3
V
0.1µ
FC
740
0.1µ
FC
741
L702
10µH
C71
00.
1µF
C70
910
µF
10µH
L705
R71
626
1Ω
10µH
L706
L704
10µH
C71
51µ
F
0.1µ
FC
708
0.1µ
FC
712
C70
60.
1µF
C71
71µ
FC
716
1µF
C71
41µ
F
PW
R_I
N
PW
R_I
N
10µF
C70
7
C70
510
µF
10µF
C71
1
DU
T_A
VD
D
DU
T_D
RV
DD
0.1µ
FC
735
0.1µ
FC
734
0.1µ
FC
733
0.1µ
FC
727
0.1µ
FC
732
0.1µ
FC
731
0.1µ
FC
743
0.1µ
FC
723
0.1µ
FC
725
0.1µ
FC
724
10µH
L703
5V_A
VD
D
3.3V
_AV
DD
PW
R_I
N
PW
R_I
N
1µF
C71
9
1µF
C72
11µ
FC
722
1µF
C72
0
L708
10µHL7
0710
µH
DR
VD
D_D
UT
1kΩ
R71
2
1kΩ
R71
0
R707
C70
1
0.1µ
F
R71
510
kΩ
10kΩ
R71
1
0.1µF
C703
R70
4
0Ω−D
NP
0Ω−D
NP
R70
3
0Ω−D
NP
R70
5
261Ω
R70
2
3
2
1J7
01
R70
14.
7kΩ
1E70
1
C702
0.1µF
10kΩ
R71
4
PICVCC
GP1
GP0
MCLR/GP3
PICVCC
AV
DD
_DU
T
AV
DD
_3.3
VA
VD
D_5
V
AV
DD
_DU
T
SC
LK_D
TP
CS
B_D
UTA
VD
D_3
.3V
GP0
CSB1_CHA
SCLK_CHA
SDI_CHA
GP1
SDO_CHA
AV
DD
_DU
T
SD
IO_O
DM
PW
R_I
N
AV
DD
_3.3
V
AV
DD
_5V
AV
DD
_DU
T
DR
VD
D_D
UT
0.1µ
FC
744
0.1µ
FC
748
0.1µ
FC
747
0.1µ
FC
746
0.1µ
FC
745
0.1µ
FC
752
0.1µ
FC
753
0.1µ
FC
749
0.1µ
FC
751
0.1µ
FC
750
C70
410
µF
06296-078
ININO
UT
OU
TO
UT
SK
33-T
P
OU
T
ININO
UT
OU
TO
UT
Figure 68. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry
Data Sheet AD9252
Rev. E | Page 43 of 52
0629
6-07
9
Figure 69. Evaluation Board Layout, Primary Side
AD9252 Data Sheet
Rev. E | Page 44 of 52
0629
6-08
0
Figure 70. Evaluation Board Layout, Ground Plane
Data Sheet AD9252
Rev. E | Page 45 of 52
0629
6-08
1
Figure 71. Evaluation Board Layout, Power Plane
AD9252 Data Sheet
Rev. E | Page 46 of 52
0629
6-08
2
Figure 72. Evaluation Board Layout, Secondary Side (Mirrored Image)
Data Sheet AD9252
Rev. E | Page 47 of 52
Table 17. Evaluation Board Bill of Materials (BOM)1
Item
Qty per Board
Reference Designator Device Package Value Manufacturer
Manufacturer Part Number
1 1 AD9252LFCSP_REVA PCB PCB PCB 2 118 C101, C102, C107,
C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C202, C207, C208, C209, C214, C215, C216, C221, C222, C223, C228, C301, C302, C304, C305, C306, C401, C402, C403, C409, C410, C411, C412, C413, C414, C415, C416, C417, C418, C501, C504, C505, C506, C508, C509, C511, C513, C518, C519, C522, C523, C524, C525, C528, C529, C530, C532, C534, C536, C537, C538, C601, C604, C605, C606, C608, C609, C611, C613, C616, C617, C618, C619, C622, C623, C624, C625, C628, C629, C630, C632, C634, C636, C701, C702, C703, C706, C708, C710, C712, C723, C724, C725, C726, C727, C730, C731, C732, C733, C734, C735, C740, C741, C742, C743, C744, C745, C746, C747, C748, C749, C750, C751, C752, C753
Capacitor 402 0.1 μF, ceramic, X5R, 10 V, 10% tol
Murata GRM155R71C104KA88D
3 8 C104, C111, C118, C125, C204, C211, C218, C225
Capacitor 402 2.2 pF, ceramic, COG, 0.25 pF tol, 50 V
Murata GRM1555C1H2R20CZ01D
4 8 C510, C512, C533, C535, C610, C612, C633, C635
Capacitor 805 10 μF, 6.3 V ±10%, ceramic, X5R
Murata GRM219R60J106KE19D
5 1 C303 Capacitor 603 4.7 μF, ceramic, X5R, 6.3 V, 10% tol
Murata GRM188R60J475KE19D
6 4 C507, C531, C607, C631
Capacitor 402 1000 pF, ceramic, X7R, 25 V, 10% tol
Murata GRM155R71H102KA01D
7 8 C502, C515, C521, C527, C602, C615, C621, C627
Capacitor 402 0.018 μF, ceramic, X7R, 16 V, 10% tol
AVX 0402YC183KAT2A
AD9252 Data Sheet
Rev. E | Page 48 of 52
Item
Qty per Board
Reference Designator Device Package Value Manufacturer
Manufacturer Part Number
8 8 C503, C514, C520, C526, C603, C614, C620, C626
Capacitor 402 22 pF, ceramic, NPO, 5% tol, 50 V
Murata GRM1555C1H220JZ01D
9 1 C704 Capacitor 1206 10 μF, tantalum, 16 V, 20% tol
ROHM Co., Ltd. TCA1C106M8R
10 9 C307, C714, C715, C716, C717, C719, C720, C721, C722
Capacitor 603 1 μF, ceramic, X5R, 6.3 V, 10% tol
Murata GRM188R61C105KA93D
11 16 C540, C541, C544, C545, C548, C549, C552, C553, C640, C641, C644, C645, C648, C649, C652, C653
Capacitor 805 0.1 μF, ceramic, X7R, 50 V, 10% tol
Murata GRM21BR71H104KA01L
12 4 C705, C707, C709, C711
Capacitor 603 10 μF, ceramic, X5R, 6.3 V, 20% tol
Murata GRM188R60J106ME47D
13 1 CR401 Diode SOT-23 30 V, 20 mA, dual Schottky
Avago Technologies
HSMS-2812-TR1G
14 2 CR701, CR702 LED 603 Green, 4 V, 5 m candela Panasonic LNJ314G8TRA 15 1 D702 Diode DO-
214AB 3 A, 30 V, SMC Micro
Commercial Co. SK33-TP
16 1 D701 Diode DO-214AA
5 A, 50 V, SMC Micro Commercial Co.
S2A-TP
17 1 F701 Fuse 1210 6.0 V, 2.2 A trip-current resettable fuse
Tyco/Raychem NANOSMDC110F-2
18 1 FER701 Choke coil 2020 10 μH, 5 A, 50 V, 190 Ω @ 100 MHz
Murata DLW5BSN191SQ2L
19 24 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112, FB201, FB202, FB203, FB204, FB205, FB206, FB207, FB208, FB209, FB210, FB211, FB212
Ferrite bead 603 10 Ω, test frequency 100 MHz, 25% tol, 500 mA
Murata BLM18BA100SN1D
20 4 JP501, JP502, JP601, JP602
Connector 2-pin 100 mil header jumper, 2-pin
Samtec TSW-102-07-G-S
21 6 J301, J302, J303, J304, J401, J701
Connector 3-pin 100 mil header jumper, 3-pin
Samtec TSW-103-07-G-S
23 1 J702 Connector 10-pin 100 mil header, male, 2 × 5 double row straight
Samtec TSW-105-08-G-D
24 8 L701, L702, L703, L704, L705, L706, L707, L708
Ferrite bead 1210 10 μH, bead core 3.2 × 2.5 × 1.6 SMD, 2 A
Murata BLM31PG500SN1L
25 8 L501, L502, L503, L504, L601, L602, L603, L604
Inductor 402 120 nH, test freq 100 MHz, 5% tol, 150 mA
Murata LQG15HNR12J02D
Data Sheet AD9252
Rev. E | Page 49 of 52
Item
Qty per Board
Reference Designator Device Package Value Manufacturer
Manufacturer Part Number
26 32 L505, L506, L507, L508, L509, L510, L511, L512, L513, L514, L515, L516, L517, L518, L519, L520, L605, L606, L607, L608, L609, L610, L611, L612, L613, L614, L615, L616, L617, L618, L619, L620
Resistor 805 0 Ω, 1/8 W, 5% tol NIC Components Corp.
NRC04Z0TRF
27 1 OSC401 Oscillator SMT Clock oscillator, 50.00 MHz, 3.3 V, ±5% duty cycle
Valpey Fisher VFAC3-BHL-50MHz
28 9 P101, P103, P105, P107, P201, P203, P205, P207, P401
Connector SMA Side-mount SMA for 0.063" board thickness
Johnson Components
142-0701-851
29 1 P301 Connector HEADER 1469169-1, right angle 2-pair, 25 mm, header assembly
Tyco 6469169-1
30 1 P701 Connector 0.1", PCMT
RAPC722, power supply connector
Switchcraft RAPC722X
31 21 R301, R307, R401, R402, R410, R413, R504, R505, R511, R512, R523, R524, R604, R605, R611, R612, R623, R624, R711, R714, R715
Resistor 402 10 kΩ, 1/16 W, 5% tol NIC Components Corp.
NRC04J103TRF
32 18 R103, R117, R129, R142, R203, R219, R235, R253, R317, R405, R415, R416, R417, R418, R706, R707, R708, R709
Resistor 402 0 Ω, 1/16 W, 5% tol NIC Components Corp.
NRC04Z0TRF
33 8 R102, R115, R128, R141, R202, R218, R234, R252
Resistor 402 64.9 Ω, 1/16 W, 1% tol NIC Components Corp.
NRC04F64R9TRF
34 8 R104, R116, R130, R143, R204, R220, R236, R254
Resistor 603 0 Ω, 1/10 W, 5% tol NIC Components Corp.
NRC06Z0TRF
35 28 R109, R111, R112, R123, R125, R126, R135, R138, R139, R148, R149, R150, R211, R212, R214, R228, R231, R232, R246, R249, R250, R262, R265, R266, R319, R710, R712, R713
Resistor 402 1 kΩ, 1/16 W, 1% tol NIC Components Corp.
NRC04F1001TRF
36 16 R108, R110, R121, R122, R134, R136, R146, R147, R209, R210, R226, R227, R242, R245, R260, R261
Resistor 402 33 Ω, 1/16 W, 5% tol NIC Components Corp.
NRC04J330TRF
AD9252 Data Sheet
Rev. E | Page 50 of 52
Item
Qty per Board
Reference Designator Device Package Value Manufacturer
Manufacturer Part Number
37 8 R161, R162, R163, R164, R208, R225, R241, R259
Resistor 402 499 Ω, 1/16 W, 1% tol NIC Components Corp.
NRC04F4990TRF
38 3 R303, R305, R306 Resistor 402 100 kΩ, 1/16 W, 1% tol NIC Components Corp.
NRC04F1003TRF
39 1 R414 Resistor 402 4.12 kΩ, 1/16W, 1% tol NIC Components Corp.
NRC04F4121TRF
40 1 R404 Resistor 402 49.9 Ω, 1/16 W, 0.5% tol Susumu RR0510R-49R9-D 41 1 R309 Resistor 402 4.99 kΩ, 1/16 W, 5% tol NIC
Components Corp.
NRC04F4991TRF
42 5 R310, R501, R535, R601, R634
Potentiometer 3-lead 10 kΩ, Cermet trimmer potentiometer, 18-turn top adjust, 10%, 1/2 W
Copal Electronics Corp.
CT94EW103
43 1 R308 Resistor 402 470 kΩ, 1/16 W, 5% tol NIC Components Corp.
NRC04J474TRF
44 4 R502, R536, R602, R635
Resistor 402 39 kΩ, 1/16 W, 5% tol NIC Components Corp.
NRC04J393TRF
45 16 R513, R514, R518, R519, R525, R526, R530, R531, R613, R614, R618, R619, R625, R626, R630, R631
Resistor 402 187 Ω, 1/16 W, 1% tol NIC Components Corp.
NRC04F1870TRF
46 8 R515, R520, R527, R532, R615, R620, R627, R632
Resistor 402 374 Ω, 1/16 W, 1% tol NIC Components Corp.
NRC04F3740TRF
47 8 R503, R507, R508, R509, R603, R607, R608, R609
Resistor 402 274 Ω, 1/16 W, 1% tol NIC Components Corp.
NRC04F2740TRF
48 11 R425, R427, R429, R431, R433, R435, R436, R439, R441, R443, R445
Resistor 201 0 Ω, 1/20 W, 5% tol NIC Components Corp.
NRC02Z0TRF
49 1 R701 Resistor 402 4.7 kΩ, 1/16 W, 1% tol NIC Components Corp.
NRC04J472TRF
50 1 R702 Resistor 402 261 Ω, 1/16 W, 1% tol NIC Components Corp.
NRC04F2610TRF
51 1 R716 Resistor 603 261 Ω, 1/16 W, 1% tol NIC Components Corp.
NRC06F261OTRF
52 2 R420, R421 Resistor 402 240 Ω, 1/16 W, 5% tol NIC Components Corp.
NRC04J241TRF
53 2 R422, R423 Resistor 402 100 Ω, 1/16 W, 1% tol NIC Components Corp.
NRC04F1000TRF
54 1 S701 Switch SMD Light Touch, 100 GE, 5 mm
Panasonic EVQPLDA15
Data Sheet AD9252
Rev. E | Page 51 of 52
Item
Qty per Board
Reference Designator Device Package Value Manufacturer
Manufacturer Part Number
55 9 T101, T102, T103, T104, T201, T202, T203, T204, T401
Transformer CD542 ADT1-1WT+, 1:1 impedance ratio transformer
Mini-Circuits ADT1-1WT+
56 2 U704, U707 IC SOT-223 ADP3339AKC-1.8-RL, 1.5 A, 1.8 V LDO regulator
Analog Devices ADP3339AKCZ-1.8-RL
57 2 U501, U601 IC CP-64-3 AD8334ACPZ-REEL, ultralow noise precision dual VGA
Analog Devices AD8334ACPZ-REEL
58 1 U706 IC SOT-223 ADP3339AKC-5-RL7 Analog Devices ADP3339AKCZ-5-RL7 59 1 U705 IC SOT-223 ADP3339AKC-3.3-RL Analog Devices ADP3339AKCZ-3.3-RL 60 1 U301 IC CP-64-3 AD9252BCPZ-50, octal,
14-bit, 50 MSPS serial LVDS 1.8 V ADC
Analog Devices AD9252BCPZ-50
61 1 U302 IC SOT-23 ADR510ARTZ, 1.0 V, precision low noise shunt voltage reference
Analog Devices ADR510ARTZ
62 1 U401 IC LFCSP CP-32-2
AD9515BCPZ, 1.6 GHz clock distribution IC
Analog Devices AD9515BCPZ
63 1 U702 IC SC70, MAA06A
NC7WZ07P6X_NL, UHS dual buffer
Fairchild NC7WZ07P6X_NL
64 1 U703 IC SC70, MAA06A
NC7WZ16P6X_NL, UHS dual buffer
Fairchild NC7WZ16P6X_NL
65 1 U701 IC 8-SOIC Flash prog mem 1k × 14, RAM size 64 × 8, 20 MHz speed, PIC12F controller series
Microchip PIC12F629-I/SNG
1 This BOM is RoHS compliant.
AD9252 Data Sheet
Rev. E | Page 52 of 52
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
0.22 MINTOP VIEW
8.75BSC SQ
9.00BSC SQ
164
1617
4948
3233
0.500.400.30
0.50BSC
0.20 REF
12° MAX 0.80 MAX0.65 TYP
1.000.850.80
7.50REF
0.05 MAX0.02 NOM
0.60 MAX0.60MAX
SEATINGPLANE
PIN 1INDICATOR
7.557.50 SQ7.45
PIN 1INDICATOR
0.300.230.18
FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.
02-2
3-20
10-B
EXPOSED PAD(BOTTOM VIEW)
Figure 73. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad (CP-64-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Notes Temperature Range Package Description
Package Option
AD9252ABCPZ-50 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 AD9252ABCPZRL7-50 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7” Tape and Reel CP-64-6 AD9252-50EBZ 2 Evaluation Board 1 Z = RoHS Compliant Part. 2 Interposer board (HSC-ADC-FIFO5-INTZ) is required to connect to HSC-ADC-EVALCZ data capture board.
©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06296-0-12/11(E)