nuc972 development board introduction.ppt -...
TRANSCRIPT
![Page 1: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/1.jpg)
NUC972 Development Board
Introduction
Jan. 9th, 2015
Nuvoton Technology Corp.
Lecturer: Cliff Huang
Tel.: +886-3-5786612 #7608
Email: [email protected]
![Page 2: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/2.jpg)
2
Overview
System Block Diagram
Features
Development Board Outline
Mainboard Block
Pin Definition (Excel file)
Board Description
Phenomenon
Packaged Item & Naming Rule
FAQ
RTC for power control
Layout Guideline in Ethernet
![Page 3: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/3.jpg)
3
Mainboard Outline
![Page 4: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/4.jpg)
4
Accessory Board Outline
5” 24-bit LCD board CMOS sensor board
![Page 5: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/5.jpg)
5
Assembled Board Outline
![Page 6: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/6.jpg)
6
System Block Diagram
Debug IFUSBD 2.0
USBH 2.0
Video In
IIS
ADC/TP
32kHz
RTC
PWM x 4
24-bit LCD
KPI
LDO
3.3V RTC
NUC8822L
12MHz
NUC9724W-TP
Backlight Control
Power
Adaptor
CMOS Sensor
Key 3x2
PC Down load
DC/DC
3.3V, 1.2V, 1.8V
JTAG ICE
IIC
Li-ion BAT
Memory
SIM card
CAN bus
Main
OSC
32kHz
UART0
UART x 4
Ethernet
SD card
eMMC
NAND
SPI
CAN bus x 2
![Page 7: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/7.jpg)
7
Features I
CAN Bus x 2
EBI (External Bus Interface)
10-bit address bus
16-bit data bus
IIS
Audio codec, NUC8822L.
Dual microphone.
Human Interface:
Power Key x 1, Reset Key x 1
3 x 2 matrix function
5” LCD with 24-bit RGB with resistor type touch panel
CMOS sensor
![Page 8: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/8.jpg)
8
Features II
Memory −−−− eMMC card, SD card, NAND flash, SPI
flash.
PWM x 4
JTAG ICE
UART x 5
Default is UART 0 for debugging message
USB
USB0 is OTG
USB1 is Host
ADC x 8
ADC0 is for battery detection.
ADC [3:7] for touch panel.
![Page 9: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/9.jpg)
9
Mainboard Block
![Page 10: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/10.jpg)
10
Board Description I
Power Block
System power control by RTCWkUp & RTCPWREn.
RTC power input
LDO – NUC3705
Battery paddle – CR2032.
JATAG ICE port
U-Link − Not to system reset.
Peripheral Device 1
eMMC – bus is shared with NAND flash.
SD
NAND – bus is conflicted with eMMC.
SPI flash – 4-bit.
![Page 11: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/11.jpg)
11
Dev. Board Description II
Peripheral Device 3
CAN Bus x 2
Slew rate setting by SW19.
PWM x 4
Peripheral Device 2
IIS – NUC8822L
Ethernet – RMII
USB
USB OTG – Control power chip by GPIO.
USB host
SIM card
![Page 12: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/12.jpg)
12
Dev. Board Description III
Peripheral Device 4
3 x 2 matrix Keypads.
CMOS sensor.
LCD – 5” RGB888.
Touch panel – ADC[3:7].
PWM – Backlight control.
EBI pin header.
Peripheral Device 6
UART0 – Debugging message
UART[1:4]
![Page 13: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/13.jpg)
13
Dev. Board Description IV
Peripheral Device 5
Power On Setting
PA[0:9] (= Cfg[0:9])
Setting pin has to be pulled low with a 10KΩ.
Cfg[1:0] = 00 : Boot from USB.
01 : Boor from eMMC.
10 : Boot from NANA Flash.
11 : Boot from SPI Flash.
Cfg2 = 0 : System clock is from 12 MHz crystal.
1 : System clock is from UPLL output.
Cfg3 = 0 : WDT is OFF after power-on.
1 : WDT is ON after power-on.
Cfg4 = 0 : Pin PJ[4:0] used as GPIO pin.
1 : Pin PJ[4:0] used as JTAG interface.
Cfg[7:6] = 00 : NAND Flash page size is 2KB.
01 : NAND Flash page size is 4KB.
10 : NAND Flash page size is 8KB.
11 : Ignore Power-On Setting.
Cfg[9:8] = 00 : NAND Flash ECC type is BCH T12.
01 : NAND Flash ECC type is BCH T15.
10 : NAND Flash ECC type is BCH T24.
11 : Ignore Power-On Setting.
![Page 14: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/14.jpg)
14
Phenomenon I
Power Block
ICE port reset
U-Link − Not to system reset. Open J4 on 2nd Dev. Board.
JTAG - 1st version is traced to system reset. 2nd one adds one
switch (J4) for shorting to system reset.
USB 0
Recognize device and host by software driver.
Power is controlled by software.
![Page 15: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/15.jpg)
15
Phenomenon IIICE Link
1st to Turbo writer connection, link to ICE
Install WinUSB4NuCom
IIC
Use PG[3:2], PH[3:2]
ADC
Vref – tied with band gap.
ADC0
Battery detection
Leakage current → 0.5mA.
Add one switch circuit for detection.
![Page 16: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/16.jpg)
16
Packaged Item & Naming Rule
Packaged Item:
NUC972DF62Y
NUC973DF62Y
NUC976DK51Y
NUC976DK52Y
NUC976DK62Y
NUC977DK62Y
![Page 17: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/17.jpg)
17
FAQ
Pin Header
VD33 is at the first 2-pin, VS is at the last 2-pin.
UART0
No message
SW31.1 must be turned on.
NAND fail
Bus is shared with eMMC.
Turn off SW11.
SIM card fail
Is shared with IIS.
Turn off SW15.
![Page 18: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/18.jpg)
18
RTC Power Control
RTC’s register setting
PCLR_TIME –
the period of the power core will be cleared after the power key is
pressed. Its time scalar is 1S and the default is 5 second.
Key_Pressed_Period_To_Power_Off = (PCLR_TIME+3) sec.
EDGE_TRIG –
1 = Edge trigger
0 = Level trigger (≥ programming time).
HW_PCLR_EN
= 1, the RPWR pin will clear to low when the power key is pressed
over the PCLR_TIME second.
= 0, the RPWR pin isn’t influenced by the pressed time of power key.
PWR_ON
PWRCE = 1 when PWR_ON = 1.
PWRCE = 0 when PWR_ON = 0, HW_PCLR_EN = 1 and PowerKey
is pressed over setting time.
![Page 19: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/19.jpg)
19
RTC Control Waveform
![Page 20: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/20.jpg)
20
RTC Checking ListPart No. Ext. RTC
OSC.
Int. RC
for RTC
VRTC
N3290x √ × 1.8V
N3291x √ √ 3.3V
N3292x √ √ 3.3V
NUC97x √ × 3.3V
Case 1
Case 2 Case 3
![Page 21: NUC972 Development Board Introduction.ppt - …caxapa.ru/thumbs/617763/NUC972_Development_Board_Introduction.pdfNUC972 Development Board Introduction Jan. 9th, 2015 ... Default is](https://reader036.vdocuments.us/reader036/viewer/2022062600/5b3fcf277f8b9a2f138c8276/html5/thumbnails/21.jpg)
21
Layout Guideline in Ethernet Phy
The trace impedance (Tx+/Tx-, Rx+/Rx-) should be
100Ω, as short as possible between phy and
transformer.
The signal traces (red line) of Tx/Rx should be
symmetry.
The trace of Tx/Rx (red line) is not longer than 12 cm.
Surround with ground
Tx+/Tx-, Rx+/Rx- Iset, Crystal
If necessary the trace routing is under transformer, D2 ≥ 60mil.
The distance is 30mil between Tx and Rx at least.
D1 ≥ 60mil, D2 ≥ 80mil