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NOW Handout

EECS 150 - Components and Design Techniques for Digital Systems

Lec 25 – Division & ECC

David CullerElectrical Engineering and Computer Sciences

University of California, Berkeley

http://www.eecs.berkeley.edu/~cullerhttp://www-inst.eecs.berkeley.edu/~cs150

12/2/2004 EECS 150, Fa04, Lec 25-div & errors 2

Division1001 Quotient

Divisor 1000 1001010 Dividend–1000

101011010–1000

10 Remainder (or Modulo result)

• At each step, determine one bit of the quotient– If current “remainder” larger than division, subtract and set Q bit to 1– Otherwise, bring down a bit of the dividend and set Q bit to 0

• Dividend = Quotient x Divisor + Remaindersizeof(dividend) = sizeof(quotient) + sizeof(divisor)

• 3 versions of divide, successive refinement


32-bit DIVIDE HARDWARE Version 1

• 64-bit Divisor register, 64-bit adder/subtractor, 64-bit Remainder register, 32-bit Quotient register

Remainder

Quotient

Divisor

add/sub

Shift Right

Shift Left

WriteControl

32 bits

64 bits

64 bits


2b. Restore the original value by adding the Divisor register to the Remainder register, &place the sum in the Remainder register. Alsoshift the Quotient register to the left, setting the new least significant bit to 0.

Divide Alg. Version 1n+1 steps for n-bit Quotient & Rem.Remainder Quotient Divisor00000111 0000 00100000

710 210Test

RemainderRemainder < 0Remainder≥≥≥≥ 0

1. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register.

2a. Shift the Quotient register to the left setting the new rightmostbit to 1.

3. Shift the Divisor register right 1 bit.

Done

Yes: n+1 repetitions (n = 4 here)

Start: Place Dividend in Remainder

n+1repetition?

No: < n+1 repetitions


Example: initial condition

Remainder/Dividend

Quotient

Divisor

add/sub

Shift Right

Shift Left

WriteControl

0000

0010 0000

0000 0111


Example: iter 1, step 1

• 1: rem <= rem – div; [7 – 32 --> -25]• Check rem <0?

Remainder/Dividend

Quotient

Divisor

add/sub

Shift Right

Shift Left

WriteControl

0000

0010 0000

0000 01111110 0111

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NOW Handout


Example: iter 1, step 2b

• rem <= rem + div;• Shift Q left, bringing in 0

Remainder/Dividend

Quotient

Divisor

add/sub

Shift Right

Shift Left

WriteControl

0000

0010 0000

0000 0111


Example: iter 1, step 3

• Shift div right

Remainder/Dividend

Quotient

Divisor

add/sub

Shift Right

Shift Left

WriteControl

0000

00010000

0000 0111


Example: Iter 2, Steps 1,2b,3

• 1: rem <= rem – div; [7 – 16 --> -9]

• 2. check rem <0? rem <= rem + div; sll Q, Q0=0• 3. srl div

Remainder/Dividend

Quotient

Divisor

add/sub

Shift Right

Shift Left

WriteControl0000 0111

0000

0001000000001000

0000


Example: Iter 3, Steps 1,2b,3

• 1: rem <= rem – div; [7 – 8 --> -1]

• 2. check rem <0? rem <= rem + div; sll Q, Q0=0• 3. srl div

Remainder/Dividend

Quotient

Divisor

add/sub

Shift Right

Shift Left

WriteControl

0000

00000100

0000 0111


Example: Iter 4, Steps 1,2a,3

• 1: rem <= rem – div; [7 – 4 --> 3]

• 2. check rem <0? sll Q, Q0=1• 3. shr div

Remainder/Dividend

Quotient

Divisor

add/sub

Shift Right

Shift Left

WriteControl

00000100

0000 01110000 0011

00000001

00000010


Example: Iter 5, Steps 1,2a,3

• 1: rem <= rem – div; [3 – 2 --> 1]

• 2. check rem <0? sll Q, Q0=1• 3. shr div

Remainder/Dividend

Quotient

Divisor

add/sub

Shift Right

Shift Left

WriteControl

00000010

0000 00110000 0001

00010011

00000001

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NOW Handout


Version 1: Division 7/2Iteration step quotientdivisor remainder0 Initial values 0000 0010 0000 0000 01111 1: rem=rem-div 0000 0010 0000 1110 0111

2b: rem<0 �� +div, sll Q, Q0=0 0000 0010 0000 0000 01113: shift div right 0000 0001 0000 0000 0111

2 1: rem=rem-div 0000 0001 0000 1111 01112b: rem<0 �� +div, sll Q, Q0=0 0000 0001 0000 0000 01113: shift div right 0000 0000 1000 0000 0111

3 1: rem=rem-div 0000 0000 1000 1111 11112b: rem<0 �� +div, sll Q, Q0=0 0000 0000 1000 0000 01113: shift div right 0000 0000 0100 0000 0111

4 1: rem=rem-div 0000 0000 0100 0000 00112a: rem≥≥≥≥0 �� sll Q, Q0=1 0001 0000 0100 0000 00113: shift div right 0001 0000 0010 0000 0011

5 1: rem=rem-div 0001 0000 0010 0000 00012a: rem≥≥≥≥0 �� sll Q, Q0=1 0011 0000 0010 0000 0001

3: shift div right 0011 0000 0001 0000 0001 12/2/2004 EECS 150, Fa04, Lec 25-div & errors 14

Observations on Divide Version 1

• 1/2 bits in divisor always 0�� 1/2 of 2n-bit adder is wasted�� 1/2 of 2n-bit divisor is wasted

• Instead of shifting divisor to right, shift remainder to left?

• 1st step cannot produce a 1 in quotient bit (otherwise quotient ≥≥≥≥ 2n)�� switch order to shift first and then subtract,

can save 1 iteration


DIVIDE HARDWARE Version 2

• 32-bit Divisor register, 32-bit ALU, 64-bit Remainder register, 32-bit Quotient register

Remainder

Quotient

Divisor

add/sub

Shift Left

WriteControl

32 bits

32 bits

64 bits

Shift Left


Divide Alg. Version 2Remainder Quotient Divisor00000111 0000 0010

710 210

3b. Restore the original value by adding the Divisor register to the left half of the Remainder register, &place the sum in the left half of the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0.

Test Remainder

Remainder < 0Remainder ≥≥≥≥ 0

2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register.

3a. Shift the Quotient register to the left setting the new rightmostbit to 1.

1. Shift the Remainder register left 1 bit.

Done

Yes: n repetitions (n = 4 here)

nthrepetition?

No: < n repetitions



Example V2: 7/2 initial conditions

Remainder

Quotient

Divisor

add/sub

Shift Left

WriteControl

Shift Left00000111

0010

0000


Example V2: 7/2 iter 1

• 1. Shift left rem• 2. sub: remLH <- remLH – div [0 – 2]• Test remLH < 0• 3b restore remLH <- remLH + div • Shift 0 into Q

Remainder

Quotient

Divisor

add/sub

Shift Left

WriteControl

Shift Left00000111

0010

000011101110111000001110

00000000

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NOW Handout


Announcements

• Dec 9, last day of class will do HKN survey• Final mid term: Dec 15 12:30 – 3:30 in 1 LECONTE • EECS in the news• Recovery Oriented Computing

– Joint with Stanford!– Availability = MTBF / (MTBF + Time to Repair)– Historically focus on increasing MTBF– ROC focuses on reducing Time to Restart:

» Isolation and Redundancy » System-wide support for Undo » Integrated Diagnostic Support. » Online Verification of Recovery Mechanisms. » Design for high modularity, measurability, and

restartability.» Dependability/Availability Benchmarking.

Dave Patterson



• Eliminate Quotient register by combining with Remainder as shifted left.– Start by shifting the Remainder left as before. – Thereafter loop contains only two steps because the

shifting of the Remainder register shifts both the remainder in the left half and the quotient in the right half

– The consequence of combining the two registers together and the new order of the operations in the loop is that the remainder will shifted left one time too many.

– Thus the final correction step must shift back only the remainder in the left half of the register


DIVIDE HARDWARE Version 3

• 32-bit Divisor register, 32-bit adder/subtractor, 64-bit Remainder register, (0-bit Quotient reg)

Remainder (Quotient)

Divisor

32-bit ALU

WriteControl

32 bits

64 bits

Shift Left“HI” “LO”


Divide Algorithm Version 3Remainder Divisor0000 0111 0010

710 210

3b. Restore the original value by adding the Divisor register to the left half of the Remainder register, &place the sum in the left half of the Remainder register. Also shift the Remainder register to the left, setting the new least significant bit to 0.

Test Remainder

Remainder < 0Remainder ≥≥≥≥ 0

2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register.

3a. Shift the Remainder register to the left setting the new rightmostbit to 1.

1. Shift the Remainder register left 1 bit.

Done. Shift left half of Remainder right 1 bit.Yes: n repetitions (n = 4 here)

nthrepetition?

No: < n repetitions


*upper-half



• Same Hardware as shift and add multiplier: just 63-bit register to shift left or shift right

• Signed divides: Simplest is to remember signs, make positive, and complement quotient and remainder if necessary– Note: Dividend and Remainder must have same sign– Note: Quotient negated if Divisor sign & Dividend sign

disagreee.g., –7 ÷ 2 = –3, remainder = –1


Error Correction Codes (ECC)

• Memory systems generate errors (accidentally flipped-bits)– DRAMs store very little charge per bit– “Soft” errors occur occasionally when cells are struck by alpha particles

or other environmental upsets.– Less frequently, “hard” errors can occur when chips permanently fail.– Problem gets worse as memories get denser and larger

• Where is “perfect” memory required?– servers, spacecraft/military computers, ebay, …

• Memories are protected against failures with ECCs• Extra bits are added to each data-word

– used to detect and/or correct faults in the memory system– in general, each possible data word value is mapped to a unique “code

word”. A fault changes a valid code word to an invalid one - which can be detected.

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NOW Handout


Correcting Code Concept

• Detection: bit pattern fails codeword check• Correction: map to nearest valid code word

Space of possible bit patterns (2N)

Sparse population of code words (2M << 2N)

- with identifiable signature

Error changes bit pattern to

non-code


Simple Error Detection Coding

• Each data value, before it is written to memory is “tagged”with an extra bit to force the stored word to have even parity:

• Each word, as it is read from memory is “checked” by finding its parity (including the parity bit).

Parity Bit

b7b6b5b4b3b2b1b0p

+

b7b6b5b4b3b2b1b0p

+c

• A non-zero parity indicates an error occurred:– two errors (on different bits) is not detected (nor any even number of errors)– odd numbers of errors are detected.

• What is the probability of multiple simultaneous errors?


Hamming Error Correcting Code• Use more parity bits to pinpoint

bit(s) in error, so they can be corrected.

• Example: Single error correction (SEC) on 4-bit data

– use 3 parity bits, with 4-data bits results in 7-bit code word

– 3 parity bits sufficient to identify any one of 7 code word bits

– overlap the assignment of parity bits so that a single error in the 7-bit work can be corrected

• Procedure: group parity bits so they correspond to subsets of the 7 bits:

– p1 protects bits 1,3,5,7– p2 protects bits 2,3,6,7– p3 protects bits 4,5,6,7

1 2 3 4 5 6 7

p1 p2 d1 p3 d2 d3 d4

Bit position number001 = 110

011 = 310

101 = 510

111 = 710

010 = 210

011 = 310

110 = 610

111 = 710

100 = 410

101 = 510

110 = 610

111 = 710

p1

p2

p3

Note: number bits from left to right.


Hamming Code Example• Example: c = c3c2c1= 101

– error in 4,5,6, or 7 (by c3=1)– error in 1,3,5, or 7 (by c1=1)– no error in 2, 3, 6, or 7 (by c2=0)

• Therefore error must be in bit 5.• Note the check bits point to 5

• By our clever positioning and assignment of parity bits, the check bits always address the position of the error!

• c=000 indicates no error– eight possibilities

1 2 3 4 5 6 7p1 p2 d1 p3 d2 d3 d4

– Note: parity bits occupy power-of-two bit positions in code-word.

– On writing to memory:» parity bits are assigned to force

even parity over their respective groups.

– On reading from memory:» check bits (c3,c2,c1) are

generated by finding the parity of the group and its parity bit. If an error occurred in a group, the corresponding check bit will be 1, if no error the check bit will be 0.

» check bits (c3,c2,c1) form the position of the bit in error.


Interactive Quiz

• You receive:

–1111110–0000010–1010010

• What is the correct value?

1 2 3 4 5 6 7 positions

001 010 011 100 101 110 111

P1 P2 d1 P3 d2 d3 d4 role

Position of error = C3C2C1

Where Ci is parity of group i


Hamming Error Correcting Code• Overhead involved in single

error correction code:– let p be the total number of parity

bits and d the number of data bits in a p + d bit word.

– If p error correction bits are to point to the error bit (p + d cases) plus indicate that no error exists (1 case), we need:

2p >= p + d + 1,thus p >= log(p + d + 1)for large d, p approaches log(d)

8 data => 4 parity 16 data => 5 parity32 data => 6 parity64 data => 7 parity

• Adding on extra parity bit covering the entire word can provide double error detection1 2 3 4 5 6 7 8p1 p2 d1 p3 d2 d3 d4 p4

• On reading the C bits are computed (as usual) plus the parity over the entire word, P:

C=0 P=0, no errorC!=0 P=1, correctable single errorC!=0 P=0, a double error occurredC=0 P=1, an error occurred in p4 bit

Typical modern codes in DRAM memory systems:64-bit data blocks (8 bytes) with 72-bit code words (9 bytes).

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NOW Handout


Summary

• Arithmetic– Addition, subtraction, multiplication, & division follow the

rules you learned as a child, but in base 2– Iterative Multiplication and Division are essentially same

circuit– Clever book keeping so n-bit add/sub using n-bit register and

2n-bit shift register– tricks to avoid sub/check/add restore???– See “Booth’s Alg” tricks below for multiply (if time)

• Error coding– Map data word into larger code word– Hamming distance is number of bit flips between symbols– Parity detects errors of hamming distance 1– Overlapping parity detects 2 and corrects 1 (SECDED)


Motivation for Booth’s Algorithm� ��

0010x 0110+ 0000 shift (0 in multiplier)+ 0010 add (1 in multiplier)+ 0010 add (1 in multiplier)+ 0000 shift (0 in multiplier)

00001100

� �� 6 = – 2 + 8 0110 = – 00010 + 01000 = 11110 + 01000

� ! ��

0010x 0110

0000 shift (0 in multiplier)– 0010 sub(first 1 in multiplier)

0000 shift (mid string of 1s) + 0010 add (prior step had last 1)

00001100


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Recoding (Encoding) Example

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Booth Multiplication Example

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Booth’s Alg: Implementation Approach

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7

NOW Handout


Booth’s Example (2 x 7)

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