Novita’ FTK da luglioP. Giannetti per il gruppo FTK

• Review Amchip - lieve cambiamento alla schedule

• Il problema del cooling ed I tests a punto 1

• Test miniasic e ordini di AMchip05

• Le schede

• FTK nel TDR del TDAQ

• Richieste e responsabilita’

LegendaAsic submission Stand-alone test Integrated testGlobal Integration testProduction - InstallationReviewMonths 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6TasksDual Output HOLAFTK Input Mezzanine Data FormatterMiniasicAMchip05 tapeout testAMchip06 tapeoutAMBSLP-Mini-LAMBSLP auxAMBSLP-LAMBSLP w AM05AUX wAM06AUX CARD w AMBSLPSecond Stage Board (SSB)FTK Level-2 Interface Crate (FLIC) cooling

Global Int.Global Int.Global Int.Global Int.

8-16 PUs8-16 PUs

test w AUX

test

20152013 2014

test

test

w DF/IBL/RODsGlobal Int.Global Int.Global Int.

test w SSB - ROSw FLIC/AUX

test w DFtest

Review cooling @point 1

Review AMchipReview Boards

TDR schedule

MOU schedule

AMCHIP status

• MiniAsic - ongoing tests at Milan – Silicon Creation Serializer/Deserializer OK• Design of AMchip05

(LPNHE-MI-LNF-PI-) advanced – Submission during october

• Design of AMchip06 expected for spring 2014 – as early as possible to maintain

the commissioning milestoneBGA package common to AMchip05 & 06 defined – Amchip05 order started

VSSS VSSS VSSSPATTIN1H

OLDVSSS VSSS VSSS

PATTIN0_P

VSSS H1_P VSSS H3_P VSSS H5_P VSSS H7_P VSSS VSSSPATTOUT

HOLDVSSS VSSS VSSS VSSS

VSSS VSSS VSSSPATTIN0H

OLDVSSS VSSS VSSS

PATTIN0_N

VSSS H1_N VSSS H3_N VSSS H5_N VSSS H7_N VSSS VSSS VSSS VSSS VSSS VSSS VSSS

VSSS VSSS VSSS VSSS VSSS VSSSPATTIN1_

PVSSS H0_P VSSS H2_P VSSS H4_P VSSS H6_P VSSS

PATTOUT_P

VSSS VSSS VSSS VSSS VSSS VSSS

VSSS VSSS VSSS VSSS VSSS VSSSPATTIN1_

NVSSS H0_N VSSS H2_N VSSS H4_N VSSS H6_N VSSS

PATTOUT_N

VSSS VSSS VSSS VSSS VSSS VSSS

VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSSVSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS

VSSS VSSS VDDIO VDDIO VDDIO VDDH VDDH VDDH VSSS VSSS VSSS VSSS VSSS VSSS VSSS VDDH VDDH VDDHVDDSERD

ESVDDIO VDDIO VSSS VSSS

VSSS VSSS VDDIO VDDIO VDDIO VDDA VDDA VDDA VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDA VDDA VDDAVDDSERD

ESVDDIO VDDIO VSSS VSSS

VSS VSS VDDIOVDDSERD

ESVDDSERD

ESVDDSERD

ESVSS VSS VDDA VDDA VDDA VDDA VDDA VDDA VDDA VSS VSS

VDDSERDES

VDDSERDES

VDDIO VDDIO VDDIO VSS

VSS VSS VDDIO VDDIOVDDSERD

ESVDDSERD

ESVSS VSS VSSS VSSS VSSS VSSS VSSS VSSS VSSS VSS VSS

VDDSERDES

VDDSERDES

VDDIO VDDIO VSS VSS

VSS VDDIO VDDIO VDDIO VDDIOVDDSERD

ESVDDSERD

ESVSS VSS VSS VSS VSS VSS VSS VSS VSS

VDDSERDES

VDDSERDES

VDDIO VDDIO VDDIO VSS VSS

VSS VDDIO VDDIO VDDIO VDDIOVDDSERD

ESVDDSERD

ESVSS VSS VSS VSS VSS VSS VSS VSS VSS

VDDSERDES

VDDFC VDDIO VDDIO VDDIO VSS VSS

VSS VSS VDDIO VDDIO VDDIO VDDFC VDDFC VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDFC VDDFC VDDIO VDDIO VDDIO VSS VSSVSS VSS VDDIO VDDIO VDDFC VDDFC VDDFC VDDFC VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDFC VDDFC VDDIO VDDIO VSS VSSVSS VSS VDDIO VDDFC VDDFC VDDFC VDDFC VDDFC VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDFC VDDFC VDDIO VDDIO VSS VSS

VSS VSS VDDIO VDDIO VDDFC VDDFC VDDCORE VDDCORE VDDCORE VDDCORE VDDCOREVSSA_LVD

SVDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDFC VDDFC VDDIO VDDIO VSS VSS

VSS VSS VDDIO VDDIO VDDIO VDDIO VDDCORE VDDCORE VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDCORE VDDCORE VDDCORE VDDFC VDDFC VDDIO VDDIO VSS VSS

VSS VSS VDDIO VDDIO VDDIO VDDIO VDDCORE VDDCORE VDDCORE VDDIO VDDIO VDDIO VDDIO VDDIO VDDCORE VDDCORE VDDCORE VDDFC VDDFC VDDIO VDDIO VSS VSS

VSS VSS VDDIO VDDIO VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDIO VDDIOVSSA_LVD

SVDDIO VDDIO VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDIO VSS VSS

VSS VSS VSS VSS VDDCORE VDDCORE VDDCORE VDDCORE VDDIO VDDIO VDDIOVSSA_LVD

SVDDIO VDDIO VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDIO VSS VSS

VSS VSS VSS VSS VDDCORE VDDIO VDDIO VDDIO VDDIO VDDIOVSSA_LVD

SVSSA_LVD

SVDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSSVSSA_LVD

SVSSA_LVD

SVSSA_LVD

SVDDIO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

TMS TDI INIT TRST VSS VSSVDDA_BG

REFVSSA_BG

REFVDDA_LV

DSVSSA_LVD

SCLK_N CLK_P TCK VSS VSS VSS VSS VSS VSS DTEST TDO VSS VSS

PACKAGE ASE DESIGN

2 Gb/s data transfer

SETUP for COOLING TESTsat Point 1

52515049484746454443424140393837363534333231302928272625242322212019181716151413121110987654321

Rack Y.05-09.A2

TURBINE

HEAT EXCHANGER

External PS unit

HEAT EXCHANGER

9U VME bin (AM PU)

Fan tray

Network switch

Air deflector

Closing panel

Fan tray

Closing panelHEAT EXCHANGER

External PS unit

HEAT EXCHANGER

9U VME bin (AM PU)

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1 Network switch

HEAT EXCHANGER

9U VME bin (AM PU)

HEAT EXCHANGER

CAEN OPTION

Rack Y.05-09.A2

TURBINE

Closing panel

Fan tray

HEAT EXCHANGER

Fan tray

Fan tray

External PS unit

Air deflector

9U VME bin (AM PU)

Responsabile A. Lanza (PAVIA)

BOARDS

• FTK_IM prototype compatible with DF via FMC connector.• Problem with power generator solved (changed component)• Output to DF tested up to 400 MHz (design) for some lines.• New requirement from DF: more lines at 400MHz required → new version needed

FRASCATI / WASEDA

La nuova scheda AMBSLP just arrived – under test

XILINX ARTIX 7 in place ofSPARTAN 6

Smaller LAMBS → normal shape

High Density connectors

NO PARALLEL BUSESONLY SERIAL LINK

CONNECTIONS

miniLAMBSLP and LAMBSLP

miniLAMBSLP

LAMBSLP

READY to order

QFN64

BGA 23x23

HW is OK but…. TDAQ - TDR…..• I samples dalla produzione ufficiale di ATLAS per

rifare I plots di FTK con IBL incluso nella simulazione non sono ancora disponibili.

• Integrazione con il sistema di produzione ha richiesto lavoro addizionale ed imprevisto, sample di calibrazione del sistema arrivati con 1 mese di ritardo

• Esiste il capitolo 8 pronto su FTK, ma I plot sono vuoti → non possiamo essere sicuri di riuscire ad ordinare AMchip06 nel 2013 se approvazione FTK ritarda - proponiamo di spostare i fondi (200 keuro) al 2014

Richieste SBLOCCO SJ 2013: solo 5 k€ su Pisa (non core) per completare miniLAMB e LAMBSLP

PER IL 2014:

FRASCATI: Produzione mezzanine FTK_IM -> 135 keuro; CPU ATCA (non core) 7 keuro.

PISA: schede e chips per 20 AMBSLPs -> 30 Pisa + 10 keuro SJ di contingenza.

MILANO: 1. AMchip06 MLM masks 200 keuro (I 195 keuro recuperati dal 2013 + 5)2. tests AMchips alla Microtest 50 keuro + 50 SJ alla definizione finale del costo.

PAVIA: consumo per test di raffreddamento e sviluppo del controllo del power supply: 5 keuro

TOT = [135 + 30 + 250] core + [7+5] (not core) = 415 k€ (core) + 12 k€ (non core) + 60 k€ SJ

FTK team organizationDeputy Project Manager - P. Giannetti (Pisa)Task LeadersHardware FTK_IM - M. Beretta (Frascati) AMBoard - M. Piendibene (Pisa) LAMB – P. Giannetti (Pisa) AMBoard and LAMB firmware - D. Magalotti (Perugia) AM chip - A. Stabile (Milan),

System Integration Tests & board integration in the Vertical Slice - M. Piendibene (PI) DAQ integration: Vertical Slice/Demonstrator - A. Annovi (Frascati) Rack integration including power supplies, cooling, & safety - A. Lanza (Pavia) Interface to level-2 - A. Negri (Pavia), A. Annovi (Frascati) FTK simulation - G. Volpi (LNF)

RESPONSABILITA’ ITALIANE IN FTK

THIS IS THE PAST: project leader will be voted and will nominate all the others

Conclusions

• Hardware development is ok

• The collaboration is strong with new important entries

• Simulation and performance studies with IBL accumulated a significant delay

"Test AMchip05 completo" milestone di fine giugno

"Completa integrazione AMBSLP in FTK con AMchip05" milestone di dicembre.

MILESTONES

14

• LVDS @ 2GHz: 11 SERDES (2 pattern in, 1 pattern out, 8 hit buses)• LVDS @ 100 MHz: CLK• single-ended control signals: JTAG Init, Dtest, Holds

AMchip05 design

15

Changes in LOGIC (LPNHE-Milan):o SERDES I/O @ 16 bits (2 DC)

(AMchip04 was 15 bits 3 DC. Internally it's always 18 bits with configurable DC)

o Two pattern inputs one pattern output (merge of pattern streams)

o 1-layer match threshold (other thresholds: never, 8, 7, 6, always)

o double width mode (4 bus - 32 bit)o optional continuous readout mode

(AMchip04 was event based only)

Change for implementation of designo Majority inside pattern becomes full custom (MILAN)o New Low Power full custom cell for pattern (LNF)

New features wrt AMchip04

Milan

16

Not USA responsabilitiescost sharing – 2014 -2017 – TDR status

ITALIA core 2013: = 220 keuro AMchip06ITALIA core 2014: 135 (FTK_IM)+ 30 (AMBSLP) + 120 (tests parzialmente SJ)

= 285 keuroITALIA core 2015: 80 (AMBSLP)+200 wafers = 280 keuroITALIS core 2016-2017: = 390 keuro AMBSLP + qualche spesa piccola non-core

FTK Am & FTK_IM TOT k€ UNI-GE ITA Waseda Heidelberg USA AM Melburne AUTH Parigi STOT

AMBSLP-LAMBSLP 80 '14; 80 '15; 390 '16-'17 550 30 500 10 10DF mezzanine - ITA 2014 135 135DF mezzanine - Waseda 2014 135 135Am05 12 mm 2̂ MPW 2013 45,00 45100 PBGA1 for AM05 2013 18,00 0 20AMchip06 MLM masks 2013 410,00 200 190 xxeng lot 9 wafers for first AMchip06 production 55,00 55package PBGA for AMchip06 +40 20,00 60AMchip06 production test 120,00 120~50wafers: 2 lots of AMchip06 2015 - 2016-17 300,00 200 100PBGA production 9000 pieces for AMchip06 35,00 35SUPER TOT 1823,00 90 1175 170 100 290 10 10 1845