novel symmetric and asymmetric multilevel inverter topologies...

Indian Journal of Geo Marine Sciences

Vol.46 (09), September 2017, pp. 1920-1930

Novel Symmetric and Asymmetric Multilevel Inverter Topologies

With Minimum Number of Switches for High Voltage of Electric Ship

Propulsion System

S.Menaka1*

& S.Muralidharan2

1 Department of Electrical and Electronics Engineering, Agni College of Technology, Chennai-600130, Tamilnadu, India

2 Department of Electrical and Electronics Engineering, Mepco Schlenk Engineering College, Sivakasi, Tamilnadu, India

*[Email:[email protected]]

Received 04 December 2015 ; revised 29 January 2016

Multilevel inverters are the excellent solution to attain speed range from minimum to maximum with high torque

at the propeller shaft in electric ship propulsion system. To produce high voltage with less harmonic content, multilevel

inverter requires more number of switching devices. In this paper, a new topology for symmetric, asymmetric multilevel

inverter is proposed. Hybrid topologies are extracted from proposed topologies for operating in higher voltage levels. It

generates dc voltage levels analogous to conventional topologies with less number of switches. It results in the reduction of

switching losses, complexity and converter cost. The effectiveness of the suggested topologies are verified by simulation

using MATLAB/SIMULINK. From the proposed topologies, asymmetric multilevel inverter is experimentally verified with

simulation results. By proper selection of switches in the proposed topologies, it is possible to supply power to the ship

propeller with maximum efficiency.

[Keywords: Propeller, Propulsion, Multilevel inverters, Cascaded H-bridge, Symmetric, Asymmetric, Hybrid]

Introduction

In recent years, multilevel inverters receive more

attention from both academy and industry.

Multilevel inverters are the excellent solution to

attain higher voltages with better harmonic

spectrum. Multilevel inverter is a power

electronic system that synthesizes a desired output

voltage from several levels of dc voltages as

inputs. The objective of multilevel inverter is to

produce a staircase output voltage using available

dc voltage sources. Quality of the output voltage

is improved by increasing the number of voltage

levels. Multilevel inverter not only achieves high

power ratings, but also enables the use of

renewable energy sources like photovoltaic, wind

and fuel cells1-4

.

Fig.1 shows the diagram of an electric ship

propulsion system. In this system, each diesel

engine is directly coupled to a permanent magnet

synchronous generator. A diode rectifier connects

the output of the generator to a variable voltage dc

bus. The dc bus feeds one of the input sides of the

double inverter. The double inverter acts as a

multilevel inverter and it is able to drive the 3-

phase 6-wire motor coupled to the propeller.

The two generator sets can operate either jointly

or one at a time, depending on the power demand

from the drive system. The working point of each

diesel engine is determined in order to supply

power to the propeller with maximum efficiency.

Depending upon the application requirements, it

is possible to connect the output of N number of

Fig. 1 Diagram of an electric ship propulsion system

INDIAN J. MAR. SCI., VOL. 46, NO. 09, SEPTEMBER 2017

generator set by using multilevel inverter.

The multilevel concept is used to diminish the

harmonic distortion in the output waveform

without decreasing the inverter power output.

Multilevel inverter is classified as multilevel with

common dc source such as diode clamped, flying

capacitor and cascaded H-bridge(CHB)1-4

. Among

the familiar topologies, the most popular one is

cascaded multilevel inverter. It exhibits several

attractive features such as simple circuit layout,

modular in structure and avoid unbalance

capacitor voltage problem.

Based upon the values of dc voltage sources, the

CHB multilevel inverter is classified as symmetric

and asymmetric multilevel inverter. Symmetric

multilevel inverter has the equal magnitude of

voltage sources. But the magnitude of dc voltage

sources used in an asymmetric multilevel inverter

are not equal. The symmetric CHB multilevel

inverter offers the advantage of high modularity.

However this topology uses high number of

switches resulting in high cost and control

complexity. Asymmetric CHB Multilevel inverter

rectifies the above problem. However,

asymmetric topology looses modularity.

Apart from the basic topologies, nowadays many

modified topologies5-10

have been introduced for

both symmetric and asymmetric multilevel

inverter with less number of switches. In this

paper new topology is proposed for both

symmetric and asymmetric multilevel inverters.

Principle of operation of proposed symmetric and

asymmetric multilevel inverters are discussed in

the next section. These proposed multilevel

inverters produce higher level output voltage with

fewer components when compared with

conventional symmetric, asymmetric CHB11

and

other topologies12

. Finally simulation results are

illustrated to validate the capability of the

proposed topology in generation of desired output

voltage.

Materials and Methods

The main purpose of this paper is to reduce the

number of components in cascaded H-bridge

multilevel inverters. Single phase structure of a

proposed symmetric multilevel inverter is shown

in Fig.2. This inverter includes three parts:

separate dc sources (N), main switches (N) and

one H-bridge cell. The separate dc sources(SDCS)

used in the proposed topology have the same

magnitude equal to Vdc. H bridge is used to

change the polarity of the output voltage in every

half cycle and also produce the zero voltage

level. Based on the states of the switches,

different levels of output voltage are generated.

To obtain +Vdc, switches SA,SB and S1 are turned

on, whereas –Vdc can be obtained by turning on

switches SC,SD and S1 .To obtain +2Vdc, switches

SA,SB and S2 are turned on, whereas –2Vdc can be

obtained by turning on switches SC,SD and S2.

Similarly, ac output voltage at each level can be

obtained in the same manner. Zero level is

produced by turning on SA and SC or SB and SD.

The main switches (S1,S2,S3…..SN ) are used to

produce ac output voltage levels from Vdc to

NVdc.

An output phase voltage waveform of an Nlevel

proposed multilevel inverter is obtained by

Van(ωt)=Va1(ωt)+Va2(ωt)+……+Va(N-1)(ωt)+VaN(ωt). (1)

The effective number of output phase voltage

levels (Nlevel) in symmetric multilevel converter

may be related to the number of separate dc

sources (N) by:

Nlevel = 2N+1 (2)

Nswitch = N+4 (3)

The maximum output voltage (Vo.Max) of this

proposed symmetric multilevel inverter is:

Vo.Max = NVdc (4)

From the equations (2) and (3), the relation

between Nlevel and Nswitch can be derived as

follows for the proposed symmetric topology.

Nlevel = 2Nswitch - 7 (5)

Fig. 2 Proposed symmetric multilevel inverter

1921

MENAKA & MURALIDHARAN: NOVEL SYMMETRIC AND ASYMMETRIC MULTILEVEL INVERTER TOPOLOGIES

Table 1: Status of the switches for different output voltage

levels in the proposed symmetric multilevel inverter

Single phase structure of proposed asymmetric

multilevel inverter is shown in Fig.3.This inverter

includes three parts: separate dc sources (N), main

switches (2N) and one H-bridge cell. The separate

dc sources (SDCS) used in this proposed topology

are not of equal magnitudes. The H-bridge part is

as same as the symmetric topology. Unlike the

symmetric topology, the asymmetric topology

must be able to bypass or conduct the dc voltage

sources separately. This is necessary to generate

all of the desired voltage levels.

For the asymmetric multilevel inverter, the

separate dc sources are chosen such that

Vk = 2(k-1)

Vdc k = 1, 2, . . . N (6)

Then

Nlevel = 2(N+1)

- 1

(7)

Nswitch = 2N+4 (8)

Vo.Max = (2N-1)Vdc (9)

From the equations (7) and (8), the relation

between Nlevel and Nswitch can be derived as

follows for the proposed asymmetric topology.

122/)2(

switchN

levelN (10)

Table1 and 2 shows the switching states of

proposed symmetric and asymmetric multilevel

inverter.

The main objective of this paper is to reduce the

number of components in cascaded H-bridge

multilevel inverters. The proposed multilevel

inverter can generate dc voltage levels that are the

same as the cascade topology with less number of

semiconductor switches.

Table 2: Status of the switches for different output voltage

levels in the proposed asymmetric multilevel inverter

Output

Van

Switch State

S1 S2 S3 S4 … S2N-3 S2N-2 S2N-1 S2N

SA

SB

SC

SD

N

K

KV1

0 1 0 1 … 0 1 0 1 1 0

…

…

…

…

…

…

…

…

…

…

…

…

VN 1 0 1 0 … 1 0 0 1 1 0

…

…

…

…

…

…

…

…

…

…

…

…

V1 +V2 0 1 0 1 … 1 0 1 0 1 0

V2 1 0 0 1 … 1 0 1 0 1 0

V1 0 1 1 0 … 1 0 1 0 1 0

0 0 0 0 0 … 0 0 0 0 1 1

- V1 0 1 1 0 … 1 0 1 0 0 1

- V2 1 0 0 1 … 1 0 1 0 0 1

-(V1 +V2) 0 1 0 0 … 1 0 1 0 0 1

…

…

…

…

… …

…

…

…

…

…

…

-VN 1 0 1 0 … 1 0 0 1 0 1

…

…

…

…

… …

…

…

…

…

…

…

N

K

KV1

0 1 0 1 … 0 1 0 1 0 1

In the proposed multilevel inverters, switches

that are put on in the level creator arms are

switched in two half periods and those put on in

Output Van

Switch State

S1 S2 S3 … SN-1 SN SASB SCSD

NVdc 0 0 0 … 0 1 1 0

(N-1)Vdc 0 0 0 … 1 0 1 0

…

…

…

… …

…

…

…

…

3Vdc 0 0 1 … 0 0 1 0

2Vdc 0 1 0 … 0 0 1 0

Vdc 1 0 0 … 0 0 1 0

0 0 0 0 … 0 0 1 1

-Vdc 1 0 0 … 0 0 0 1

-2Vdc 0 1 0 … 0 0 0 1

-3Vdc 0 0 1 … 0 0 0 1

…

…

…

…

…

…

…

…

…

-(N-1)Vdc 0 0 0 … 1 0 0 1

-NVdc 0 0 0 … 0 1 0 1

Fig. 3 Proposed asymmetric multilevel inverter

1922


(a)

(b)

Fig. 4 Comparison study: Number of Levels vs. Number

of Switches (a) Symmetric state (b) Asymmetric state

the H- bridge cell are almost switched with

fundamental frequency. Reduction in number of

switches and low frequency switching of the

proposed inverters improves the efficiency in

comparison with other topologies.

For example, for a 15 level inverter, the

proposed symmetric topology uses 11 IGBTs and

7 dc voltage sources whereas the cascaded

symmetric H-bridge use 28 IGBTs and 7 dc

voltage sources. The proposed asymmetric

multilevel inverter uses considerable lower

number of IGBTs and dc sources in comparison

with other topologies. For instance, for a 31 level

inverter, the proposed asymmetric topology uses

12 IGBTs and 4 dc voltage sources whereas the

cascaded H-bridge use 16 IGBTs and 4 dc voltage

sources.

Table 3 and 4 summarize the comparison study

between the conventional cascaded topology in

symmetric and asymmetric with proposed

topology in symmetric and asymmetric states.

Table 3: Cascaded symmetric Vs. Proposed symmetric MLI

Inverter

Configuration Cascaded

Symmetric

H-Bridge

Proposed

Symmetric

inverter Parameters

DC sources N N

Voltage Level 2N+1 2N+1

Vo Max NVdc NVdc

Main switching

Devices 4N N+4

Table 4: Cascaded asymmetric Vs. Proposed asymmetric MLI

Inverter

Configuration

Cascaded

Asymmetric

H-Bridge

Proposed

Asymmetric

inverter Parameters

DC sources N N

Voltage Level 2(N+1)

-1 2(N+1)

-1

Vo Max (2N-1) Vdc (2

N-1) Vdc

Main switching

Devices 4N 2N+4

Fig.4 shows the comparison of the number of

switches between the topology suggested in this

paper and the conventional cascaded H-bridge

topology in symmetric and asymmetric states.

In the proposed topologies, the switches of the

H-bridge part have to withstand a voltage equal to

sum of all the dc voltage sources. So, the H-

bridge switches should have the high standing

voltage which restricts the application of the

proposed topologies for high voltage

requirements. In order to mitigate this problem,

the proposed topologies can be used in hybrid

forms. Fig.5 shows the hybrid topology using the

series connected proposed symmetric or

asymmetric topology and an H-bridge.

Fig. 5 Hybrid Topology

1923


In proposed symmetric hybrid multilevel inverter, the input voltage of added H-bridge inverter can be determined by the following equation.

VT = (N+1) Vdc (11) Where N is the number of separate dc sources used in the proposed topology only.

The maximum output voltage of the proposed

symmetric multilevel inverter used in the hybrid topology is:

Va1max = NVdc (12)

The maximum output voltage of the H-bridge

used in the symmetric hybrid topology is:

Va2max= (N+1)Vdc (13)

From the equation (12) and (13), the maximum

output voltage can be derived as follows for the

symmetric hybrid topology.

VLmax = (2N+1)Vdc (14)

Table 5 summarize the comparison study

between the conventional cascade symmetric

hybrid topology with proposed symmetric hybrid

topology.

Table 5: Cascaded symmetric hybrid vs. Proposed symmetric

hybrid MLI

Inverter

Configuration

Cascaded

Symmetric

Hybrid

Proposed

Symmetric

Hybrid Parameters

DC sources N+1 N+1

Voltage Level 4N+3 4N+3

Vo Max (2N+1)Vdc (2N+1)Vdc

Main switching

Devices 4(N+1) N+8

In proposed asymmetric hybrid multilevel

inverter, the input voltage of added H-bridge

inverter can be determined by the following

equation.

VT = 2N Vdc (15)

Where N is the number of separate dc sources

used in the proposed topology only.

The maximum output voltage of the proposed

asymmetric multilevel inverter used in the hybrid

topology is:

Va1max = (2N - 1) Vdc (16)

The maximum output voltage of the H-bridge

used in the asymmetric hybrid topology is:

Va2max= 2N Vdc (17)

From the equation (16) and (17), the maximum

output voltage can be derived as follows for the

asymmetric hybrid topology.

VLmax = (2N+1)Vdc (18)

Table 6 summarize the comparison study

between the conventional cascade asymmetric

hybrid topology with proposed asymmetric hybrid

topology.

Table 6: Cascaded asymmetric hybrid vs. Proposed

asymmetric hybrid MLI

Inverter

Configuration

Cascaded

Asymmetric

Hybrid

Proposed

Asymmetric

Hybrid Parameters

DC sources N+1 N+1

Voltage Level 2(N+2) - 1 2(N+2) - 1

Vo Max (2N+1 - 1) Vdc (2N+1 - 1) Vdc

Main switching

Devices 4(N+1) 2N+8

Fig.6 shows the typical output of the proposed

symmetric hybrid topology. Fig.6 (a) and (b)

shows the output voltage of the proposed

symmetric topology and added H-bridge. This

figure indicates a possible modulation scheme to

get the desired output voltage. Fig.6(c) shows the

output voltage of the hybrid topology.

Fig.6 (a) Output voltage of the proposed symmetric

topology (for three Vdc sources) (b) Output voltage of the

added H-bridge(c) Output voltage of the hybrid topology

1924


In this hybrid MLI, the proposed symmetric

topology is responsible for creating the voltage

levels. The added H-bridge decreases the voltage

rating requirements of the switches for a specific

output voltage rating. The same form can be done

for the asymmetric topology.

Result and Discussion

The performance of the proposed symmetric

and asymmetric inverter is verified via computer

simulation. The MATLAB-SIMULINK power

blockset software has been used for simulation.

The dc voltage sources used in the simulation

studies are separate dc sources. In practice, these

dc voltage sources may be available via

renewable energy sources such as photovoltaic,

wind and fuel cells.

For verifying the validity of the proposed

multilevel inverter in the generation of a desired

output voltage waveform, a prototype is simulated

based on the proposed symmetric topology which

is shown in Fig.2.

The input is given from generator through

rectifier as shown in Fig.1 or renewable energy

sources. The symmetrical multilevel inverter

shown in Fig.7 is adjusted to produce an output

voltage of 252 volts, 50Hz and 15 level staircase

waveform. This symmetric 15-level inverter

requires 7 separate dc voltage sources with the

rating of 36 volts which is now available in the

market. A resistive load of 100Ω is selected as a

parameter for testing the proposed symmetric

topology.

Switching status are given in Table 7 and the

output voltage waveform for the proposed

symmetric 15 level multilevel inverter is shown in

Fig.8.

The asymmetrical multilevel inverter is shown in

Fig.9 is adjusted to produce an output voltage of

252 volts, 50Hz and 15 level staircase waveform.

A resistive load of 100Ω is selected as a

parameter for testing the proposed asymmetric

topology.

This asymmetric 15-level inverter requires 3

separate dc voltage sources with different voltage

rating of V1=36V, V2=72V and V3=144V. The

output voltage waveform for the proposed

asymmetric 15 level multilevel inverter is shown

in Fig.10 and the status of the switches for the

corresponding output is given in Table 8. The

simulation results shows that the proposed

asymmetric multilevel inverter produce the output

voltage and level as that of proposed symmetric

inverter with less number of separate dc voltage

sources and switches. Reduction of switches leads

to improved efficiency of the proposed topology.

Table 7: Status of the switches – 15 level proposed

symmetric MLI

Output

Van

Switch State

S1 S2 S3 S4 S5 S6 S7 SA

SB

SC

SD

7Vdc 0 0 0 0 0 0 1 1 0

6Vdc 0 0 0 0 0 1 0 1 0

5Vdc 0 0 0 0 1 0 0 1 0

4Vdc 0 0 0 1 0 0 0 1 0

3Vdc 0 0 1 0 0 0 0 1 0

2Vdc 0 1 0 0 0 0 0 1 0

Vdc 1 0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 0 1 1

-Vdc 1 0 0 0 0 0 0 0 1

-2Vdc 0 1 0 0 0 0 0 0 1

-3Vdc 0 0 1 0 0 0 0 0 1

-4Vdc 0 0 0 1 0 0 0 0 1

-5Vdc 0 0 0 0 1 0 0 0 1

-6Vdc 0 0 0 0 0 1 0 0 1

-7Vdc 0 0 0 0 0 0 1 0 1

Fig. 7 The proposed symmetric topology -15 level MLI circuit

1925


Table 8: Status of the switches – 15 level proposed

asymmetric MLI

Output Van

Switch State

S1 S2 S3 S4 S5 S6 SA

SB

SC

SD

V1 + V2+ V3 0 1 0 1 0 1 1 0

V2 + V3 1 0 0 1 0 1 1 0

V1 + V3 0 1 1 0 0 1 1 0

V3 1 0 1 0 0 1 1 0

V1 + V2 0 1 0 1 1 0 1 0

V2 1 0 0 1 1 0 1 0

V1 0 1 1 0 1 0 1 0

0 0 0 0 0 0 0 1 1

- V1 0 1 1 0 1 0 0 1

- V2 1 0 0 1 1 0 0 1

- (V1 + V2) 0 1 0 1 1 0 0 1

- V3 1 0 1 0 0 1 0 1

- (V1 + V3) 0 1 1 0 0 1 0 1

- (V2 + V3) 1 0 0 1 0 1 0 1

-(V1 +V2 + V3) 0 1 0 1 0 1 0 1

Fig.11 and Fig.12 shows the hybrid topology

based on the proposed symmetric and asymmetric

topology, respectively. These proposed inverters

are used for simulation studies of the hybrid

topologies. As shown in Fig.11, the proposed

symmetric topology uses 3 dc voltage sources,

each of which 36V and a 144 V dc voltage source

for the added H-bridge. Therefore the maximum

output voltage will be 252V for the proposed

symmetric hybrid topology. The simulation

results for the proposed symmetric hybrid

topology is shown in Fig.13. As the figure shows

the rated voltage (252V) is divided almost equally

between the two parts of the multilevel inverter.

As shown in Fig.12, the proposed asymmetric

topology uses 3 dc voltage sources of 18V, 36V

and 72V and an added H-bridge uses a dc voltage

source of 144V. Therefore the maximum output

voltage will be 270V for the proposed asymmetric

hybrid topology. The simulation results for the

proposed asymmetric hybrid topology is shown in

Fig.14. As the figure shows the rated voltage

(270V) is divided almost equally between the two

parts of the multilevel inverter leading to

reduction in the voltage rating of the switches

used in the H-bridge parts. Therefore, the

proposed hybrid topologies will be more suitable

for higher voltage application. Proposed hybrid

topologies are used to reduce and mitigate the

voltage stress problem persist in the switches of

the H-bridge part (Fig.7 and Fig.9). Proposed

hybrid topologies require less number of switches

when compared to conventional cascaded H-

bridge hybrid topologies.

Fig. 10 Proposed Asymmetric Topology - 15Level Output

Voltage

Fig. 9 The proposed asymmetric topology-15 level MLI

circuit

Fig. 8 Proposed Symmetric Topology - 15 Level Output

Voltage

1926


Experimental Results

In order to validate the proposed concept, the

asymmetric multilevel inverter in Fig.3 was

constructed and tested in the 15 level mode. It can

generate staircase waveform with maximum of 42

volts on the output.

Fig.15 shows the generation of control signal for

proposed multilevel inverter circuit. The control

signal generation circuit consist of Field

Programmable Gate array (FPGA) controller,

opto-coupler and driver circuit. Each switch in the

converter requires an isolated driver circuit. This

isolation can be provided by using opto-coupler.

FPGA controller has been used to generate the

Pulse Width Modulation (PWM) control signals

according to the proposed switching strategy. The

PWM signal is used to trigger the power switches

present in the proposed multilevel inverter circuit.

Fig.16 shows the experimental setup of the

proposed asymmetric multilevel inverter.The

converter consists of dc voltage sources of 6V,

12V, 24V and one H-bridge. The experimental

setup was realized by supplying a R load with

1.5A current. This prototype inverter was built

using MOSFET IRF840 as switching devices, IC

TLP250 as MOSFET driver. The gating pulses

are produced by FPGA controller (Xilinx ISE).

Fig.17 shows the experimental waveforms of the

15 level output voltage and current of the

prototype system.The output voltage is a 50Hz

staircase waveform with amplitude of 42 volts. As

can be seen, the results verify the ability of the

proposed system for the generation of desired

output voltage.Also, we can note that in 15 level

output, due to the reduction of switches two

percent reduction in Total Harmonic

Distortion(THD) is obtained in proposed

symmetric and asymmetric topologies compared

to cascaded symmetric and asymmetric

topologies.As the number of level increases,there

will be a appreciable reduction in THD. Harmonic

profile can be improved further by applying

various modulation and control techniques like

carrier based Sinusoidal Pulse Width Modulation

(SPWM), Selective Harmonic Elimination (SHE-

PWM) and Space Vector Modulation(SVM).

Fig. 12 The proposed asymmetric hybrid topology -

31 level MLI

Fig. 11 The proposed symmetric hybrid topology -

15 level MLI

1927


Fig. 14 Simulation results- The proposed asymmetric hybrid

topology (a) output voltage of the proposed asymmetric

topology(Va1), (b) output voltage of the added H-

bridge(Va2), (c) voltage across the load VL(31 level).

Fig.13 Simulation results- The proposed symmetric hybrid

topology (a) output voltage of the proposed symmetric

topology(Va1), (b) output voltage of the added H-

bridge(Va2), (c) voltage across the load VL(15 level).

1928


Conclusion

In this paper, a novel topology has been

proposed for both symmetric and asymmetric

multilevel inverter. The suggested topology needs

fewer switches to obtain the same levels of output

voltage when compared with conventional one. It

provides more flexibility for the designers with

low switching loss. Also, two hybrid topologies

have been proposed based on new symmetric and

asymmetric multilevel inverter which are more

suitable for high voltage applications.

The advantages of proposed inverter over

conventional inverter scheme can be summarized

as follows:

(1) Reduced switching loss. (2) Improved efficiency and reliability. (3) Reduced cost, size and weight compared

to conventional systems.

Therefore, the suggested multilevel inverter

circuit is a good choice for electric ship

propulsion system because it allows to choose

optimal sizing of diesel motor and synchronous

generator thereby reducing the fuel consumption.

Simulation and experimental results are given to

verify the proposed topologies.

Acknowledgement

We are grateful to the management of

Agni college of Technology, Chennai and Mepco

Schlenk Engineering College, Sivakasi for

providing facilities to carry out the above research

work.

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1929


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