nov. 7, 2002the svx4 chip -- m. garcia-sciveres1 the svx4 readout chip vertex 2002 m....

Nov. 7, 2002 The SVX4 Chip -- M. Garcia-Sciveres 1

The SVX4 Readout ChipVertex 2002

M. Garcia-Sciveres, Lawrence Berkeley National Lab.

SVX21996 SVX3

1998

SVX42002

SVX’1990

The SVX Family of chips


Credits & History

• Design Team:– LBNL: Brad Krieger (lead designer), Jean-Pierre Walder (ADC), Henrik von

der Lippe (I/O pads), Emanuelle Mandelli (full chip simulation)– FNAL: Tom Zimmerman (preamp & pipeline), Jim Hoff (pipeline logic)– U. of Padova: Stefania Alfonsi (FIFO)

• Timeline– July 2000: First SVX4 proposal meeting following studies at LBNL – May 2001: Common CDF/D0 specifications supplied to designers.

Preliminary design review.– October 2001: Final Design Review– April 2002: Design submitted for fabrication– June 10, 2002: Wafers delivered to FNAL– June 12, 2002: First chip tested at LBNL, basic functionality verified.


Why SVX4?

• Present CDF and D0 detectors not expected to survive beyond 4-6 fb-1

• Noise increase in SVX3 and SVX2 chips is important limitation on lifetime

• Not possible to re-order existing chips to build new detectors

• Take advantage of new Quarter Micron technology and work done for LHC experiments.

• Functionally, SVX4 SVX3 + additional interface logic to make it optionally heave like SVX2 chip.

~=


Review of SVX3(presented at Vertex 1998)

• Low resistivity substrate exploited for ground distribution and digital/analog isolation

• Real time pedestal subtraction built into ADC

ADC

8

Charge sensitive amplifier with adjustable risetime

Dual-ported analog pipeline for dead-timeless operation

Wilkinson type ADC 128 channels in parallel

Zero-suppressed readout on 8-bit parallel bus


SXV4 features

• Use same floor plan as SVX3• Most analog circuits redesigned at schematic level- full

custom layout• Digital circuits made using library parts from rad-hard

library developed for ATLAS pixel chip, based on RAL quarter micron library.

• Use low resistivity substrate as in SVX3• Add on-chip decoupling capacitance• Design relies heavily on fantastic accuracy of high volume

commercial process simulation tools – this is THE biggest change relative to traditional rad-hard electronics.


Results• Full SVX4 chip was simulated before submission. The

problem is no longer “can you simulate it” but rather “what to simulate”.

• First full size chip fabricated is essentially a usable chip:The number of changes needed for the next SVX4 submission is less than the number of changed made for the SVX3 production run.

• The things that need to be fixed were not caught by the simulation because the right things were not simulated.

• Every item could be simulated after the fact, including a very subtle ADC effect (shown later).

• Radiation tolerance to spare. SEU x-section lower than SVX3- same register cells as ATLAS but 100 times fewer of them.


Analog performance

0500

1000150020002500

30003500

0 10 20 30 40 50

Input Capacitance (pF)

EN

C (

ele

ctr

on

s)

svx3D 4MRad SVX4 10MRad

100ns integration time, 70ns 0-90% rise time, 290uA/channel preamp current


Zero-Suppressed Data Out “FIFO”• SVX3 “FIFO” is full custom, dynamic

logic circuit with asynchronous collapse to achieve zero suppression.

• This was the only way to do it fast enough in 0.8m.

• 0.25m is SO MUCH faster that we could instead use a fully synchronous, automatic place and routed VHDL circuit with no collapse phase- zero suppression happens in real time during readout.

• At design readout speed if 53MHz it works exactly except for some special low occupancy hit patterns in which case a single extra readout clock is used. This OK for us.


Full chip Simulation

• >300K transistors

• TIME-MILL program with some tricks

• Save DC points of programmable registers

• About 1hr per s


ADC Comparator channel-to-channel scatter

Channel number

AD

C c

ount

s (p

edes

tal)

Measurement: Each line is a different comparator bias current

Less bias

More bias

• Pedestal shifts but gain is the same for all traces


ADC scatter cause

• All comparators identical at schematic and layout levels.

• Quarter micron circuits it turns out are particularly sensitive to tiny threshold mismatch in “matched” (at layout level) transistors. – This is NOT the same thing as lot-to-lot global variations or “corners”

• TSMC in fact provides data on this type of mismatch for every transistor parameter (for IBM data comes from a thesis)

• With these data one can run a Monte Carlo circuit simulation were the parameters are wiggled for selected transistors.

• We wiggled other parameters, not just Vth, but found that Vth is the only one that matters.

• Interestingly the ATLAS FE chip was also bitten by this bug, which led to a higher than desired threshold dispersion in current prototype. We copied the MC simulation idea from them.


MC Simulation of Channel-to-Channel Variations

Measured SPREADSimulated, 4 transistor MC

Simulated, all transistor MC

Measured DELAYSimulated, 4 transistor MC

Simulated, all transistor MC

Bias current

AD

C c

oun

ts


Conclusion

• SVX3 circuit was converted to .25mm with some enhancements in a little over 1 year.

• SVX4 significantly outperforms SVX3.

• Full chip prototype in hand 2 years after first we though of doing it is already closer to a production chip than the final SVX3 prototype was.

• Really a new (to us) way to design ICs. Use state of the art industry tools for high volume process. Full chip simulation leading to very high confidence submission.

nov. 7, 2002the svx4 chip -- m. garcia-sciveres1 the svx4 readout chip vertex 2002 m....

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