non ideal effects of pll

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NON IDEAL EFFECTS OF PLL Presented by:- Amrendra prakash(EC- 11) Anil kumar pandit(EC- 12) Anjali manjhi (EC-13) Dayanand kumar(EC-30) Madhukar anand (EC-48) Presented to:- Ravitesh Mishra A.P. BCE Mandideep 1 Time taken-30mins March 5, 2013

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Page 1: Non ideal effects of pll

NON IDEAL EFFECTS OF PLL

Presented by:- Amrendra prakash(EC-

11) Anil kumar pandit(EC-12) Anjali manjhi (EC-13) Dayanand kumar(EC-30) Madhukar anand (EC-48)

Presented to:- Ravitesh Mishra

A.P.

BCE Mandideep

1Time taken-30mins March 5, 2013

Page 2: Non ideal effects of pll

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CONTENTS Introduction(PLL) Phase detector Phase frequency detector(PFD) Non ideal effects of PLL (a)PFD non idealities (b)Jitter in PLL Noise in PLL Application of PLL

March 5, 2013 AMRENDRA PRAKASH

Page 3: Non ideal effects of pll

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INTRODUCTION

PHASE LOCK LOOPS(PLL)

A PLL is a feedback system that compares the output phase with the input phase.

March 5, 2013 AMRENDRA PRAKASH

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The comparison is performed by a phase comparator or phase detector(PD)

Operates on excess phase of x(t) and y(t). “Locked” when phase difference between input

and output is constant with time. The operation of phase detectors is similar to that

of differential amplifier in which difference between the two inputs, generating a proportional output.

March 5, 2013 AMRENDRA PRAKASH

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PHASE DETECTOR

March 5, 2013 ANJALI MANJHI

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Example of phase detector-

Exclusive OR (XOR) gate

March 5, 2013 ANJALI MANJHI

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PHASE FREQUENCY DETECTOR(PFD)

For periodic signals, it is possible to merge the two loops by devising a circuit that can detect both phase and frequency differences called a PFD.

March 5, 2013 ANJALI MANJHI

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NON IDEAL EFFECTS OF PLL

In practical PFD the delay of the gates creates non-idealities in the phase input/output characteristic.

The PFD can no longer resolve very small phase errors, and a dead zone is created.

To solve this problem, extra delay is introduced in the feedback path of reset signal.

(1) PFD non idealities

March 5, 2013 ANIL KUMAR PANDIT

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•Dead Zone problem-1)Due to finite gate delay2) Introduce large jitter or poor phase noise

March 5, 2013 ANIL KUMAR PANDIT

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(2)Jitter in PLL

March 5, 2013 ANIL KUMAR PANDIT

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11March 5, 2013 ANIL KUMAR PANDIT

Page 12: Non ideal effects of pll

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NOISE IN PLL

March 5, 2013 MADHUKAR ANAND

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14March 5, 2013 MADHUKAR ANAND

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VOLTAGE CONTROLLED OSCILLATOR(VCO)

March 5, 2013 MADHUKAR ANAND

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APPLICATIONS OF PLL

Frequency multiplication

March 5, 2013 DAYANAND KUMAR

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Data recovery(Jitter reduction)

March 5, 2013 DAYANAND KUMAR

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Skew reduction

March 5, 2013 DAYANAND KUMAR

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THANK YOU

March 5, 2013 DAYANAND KUMAR

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