Non-conventional Operation of FETs and FET Circuits, and Non-

conventional FETsHow much can we gain and what are the

applications

M. Jamal Deen

ECE Department, McMaster UniversityHamilton, Ontario L8S 4K1 Canada

E-mail: jamal@mcmaster.ca

2

ITRS Predictionsf

f

Linewidth

RF Frequency

t

Linewidth

Max. RF Frequency from 10 to 100GHz

fT from 45 to 125GHz

fMAX from 90 to 250GHz

Time from 2001 to 2016

tOX from 1.45 to 0.45 nm

Linewidth from 150 to 25 nm

3

Alternate Niche Technology

Finished plastic foil, consisting of a 3 inch polyimide substrate and about 50 integrated circuits.

Each circuit contains a programmable code generator together with a variety of components and test circuits.

http://physicsweb.org/article/world/12/3/11http://researchweb.watson.ibm.com/journal/rd/451/dimitrakopoulos.html

4

Plastic Electronics

Plastic thin-film transistors have a variety of uses, including

wearable electronics,

RFID tags, and

electronic newspapers.

http://www.infineon.com/news/press/211_016e.htm

1000 transistors/IC (Philips 02)plastic chips,electronic barcode or tags, bank or telephone cards, and drivers for flat panel displays

http://www.imo.luc.ac.be/research_activities/oem/plastic_trans.html

5

OutlineWhat can we gain from the 4th MOS terminal

Substrate bias effects and dynamic VTH MOSFETSubthreshold operation of devicesGated-lateral BJTCircuits - oscillator, AGC, mixer

Non-conventional/emerging FET - the PFETApplicationsHow are they madeTypical characteristics

Research issues

Conclusions

6

Why MOSFETs?Dominant technology in information technology systems

Used in almost all digital circuits and systems

Excellent reliability

Large infrastructure of industry; probably most studied device

Performance keeps improving, displacing other technologies

Other flavours of technology are becoming available for higher frequency or future applications- SOI, SOS, SiGe

Highly sophisticated models are available for designers -technology, device, circuit and systems

Offers the best economic and system level integration capabilities of any existing technologies

Is the best solution for system-on-chip (SOC) architectures

7

RF Performance of MOSFETs

DUTs are fabricated in 0.18µm CMOS technology with the channel length 10×6 µm and measured at VDS = 1.0 V.Maximum fT is around 50 GHz and the best NFMIN is about 0.5 dB at 2GHz.

8

MOS Device DetailsImportant Device Details

Source/Drain, Gate and Substrate LDD regionsLOCOS isolation or STIGate oxide thicknessJunction depthSidewall dielectricGate materialChannel dopingContacts of junctions (S and D)Contacts to G (and also B)Types/doping of substrateTechnology: bulk, SOI or SOSTechnology: homo- or hetero-junctionsShort channel effects

gate oxide 4.3nm thickness

gate-sidewall 100nm thickness

in situphosphorus doped polysilicon

Leakage Current

Space Charge Region

Source DrainGateVDD (V)

0 V

0 V

9

Issues in Scaling MOSFETs (IEDM’00, 235)

Issues Reasons (esp. < 100 nm MOS)Short channel effect Reduced L; less reduction in depth & broadness

of junction.

Gate leakage current Direct tunneling through thin oxide

VTH fluctuations Gate length and dopant density fluctuations

Polygate depletion effects Solid solubility limit, increased Evertical and Bpenetration

Junction capacitance Higher doping and abrupt junction

Mobility degradation Increased Nchannel, increased Evertical and Bpenetration

Junction leakage Shallow junctions with silicide metallization

S/D resistance Shallow junctions

Gate sheet resistance Narrow gate width

10

Recent MOS Technologies (IEDM’00, 235)

Elevated S/D. Lower Rparasitic & junction leakage. Better SCEBandgap engineering. SiGe S/D. Improved SCENi silicide. Lower Rparasitic. Improved transistor performance

S/D engineering

Atomic layer doping. Si molecular epitaxyLow energy implantation, optimized annealsPlasma doping. Laser or spike annealing. SiGe extension

Shallow junction

Poly SiGe gate. Reduced polydepletion. Better PMOS.Poly/Metal (Cu,W) stack gate. Reduced gate sheet Res.Dual metal gate - Ti for NMOS and Mo for PMOS

Gate electrode

Oxynitride using NO. Reduced B penetration, VTH spreadOxide scaling evaluation and optimization.

Gate oxide

Channel epitaxy. SCE and Cj improve. Less VTH fluctuationsStrained-Si channel. Enhanced mobility and gM

Halo implant optimization. Reduced SCE, junct. leakage, Cj

Channel engineering

Technology (Below 100 nm CMOS)Process

11

Substrate BiasingImproves the MOSFET performance

Forward substrate biasing (VBS>0) reduces the threshold voltage VT → low voltage applications

Forward substrate biasing (VBS>0) speeds - up the MOSFET → RF applications

Reverse substrate biasing (VBS<0) reduces the drain current ID → low power applications

S

D

BGVDS

VGS VBS

NMOS, 10x0.2µm

VDS=25mV

0.0 0.3 0.6 0.9 1.2

Gate Voltage (V)

10 -12

10 -11

10 -10

10 -9

10 -8

10 -7

10 -6

10 -5

10 -4

10 -3

Dra

in C

urre

nt (A

) 0.5V

-0.5V

0V

12

DTMOS (IEDM’00, 451)

GateDrainSource

Conv. Body

tBox=360nm

Pocket

DT

tSi=200nm

0

0.1

0.2

0.3

0.4

0.2 0.4 0.6 0.80Body Bias (V)

V TH

(V)

Lpoly=80nm

In pocketB pocket

10µm

Sour

ce

Sour

ce

Drain

Gate/Body

f max

(GH

z)

0.0 0.5 1.0

Rgate (Ω /Sq)

50

100

150

Gate length = 80nm

Finger length = 10µm

1.50.0 0.5 1.00

50

100

150 f T

, fm

ax(G

Hz)

VGS (V)

fT

fmax

DTConv.

Lpoly=80nm, VDS=1VDT

Conv.

Lpoly=80nm

VDS=1V

-0.5 0.0 0.5 1.0 1.510-12

10-10

10-8

10-6

10-4

10-2

0

200

400

600

800

1000

1200

VGATE (V)

I drai

n(A

/µm

)

g M(m

S/m

m)

13

Circuit Description VDD

VBP

VBN

Output buffer

501 stage

Fully integrated Ring VCO Fabricated in 0.18 µm technologyVDD

VoutVin

VBP

VBN

µm1.6=W18.0=L µm

µm8.1=W18.0=L µm

Vin Vout

VDDVBP

VBN

14

Oscillation Frequency

time

VDD

tPHL+ tPHL

VDD

2

V1 V2 V3

CL

V1 V2

VDD

VBP

VBN

V3

CL, the effective loading seen by each inverter, is charged and discharged

Charge and discharge at 3 consecutive Inverters output

D,AVG

L DDo

IN C V

f =• • N = number of stages

fo = frequency of oscillationPHL PLH

o1

N (t t )f =

⋅ +

15

Power ConsumptionCurrent from power supply has two components:

load current ICL,

short circuit current ISC (negligible).

2L DD o NC V fP = • • •

CL

Vin

ICL

VDD

VBP

VBN

ISC

fo×N = constant ==>

Power consumption is independent of the number of stages

2L DD

PHL PLH

C V(t t )

P ⋅=

+

16

Sub-Threshold Operation of MOSFETThe sub-threshold I-V characteristics of a MOSFET

φ φ − = − −

GS DSo

T T

thD

V VI exp 1 exV pn

I

0.15

VDS (V)

Measured

0.15

10-9

10-10

10-11

10-12

10-13

10-14

Calculation

0.20

0.10

0.04V

VGS=-0.01V

0 0.05 0.1 0.15

I D(A

)

TkTq

φ =

Vth = threshold voltage

n = sub-threshold slope

17

Sub-Threshold Operation of InverterVoltage transfer characteristics of inverter operating in sub-threshold is similar to that of strong inversion.

0

0.2

0.4

0.6

0.0 0.2 0.4 0.6 Vin (V)

Vo

ut(V

)

VBS=0

ModelMeas

Analyzing the operation of inverter in sub-threshold

Measurement: functional down to ~ 80 mV supply.

0.0 0.05 0.1 0.15 0.2Vout (V)

1

10

100

1000 Vin=0.15 V

0.125

0.10.0940.075

0.05

NMOSFET

PMOSFET

0.1

Vin=0.05 V

0.0750.094

0.125

0.15

0.0 0.05 0.1 0.15 0.2Vout (V)

1

10

100

1000 Vin=0.15 V

0.125

0.10.0940.075

0.05

NMOSFET

PMOSFET

0.1

Vin=0.05 V

0.0750.094

0.125

0.15

0.0 0.05 0.1 0.15 0.2Vout (V)

1

10

100

1000 Vin=0.15 V

0.125

0.10.0940.075

0.05

NMOSFET

PMOSFET

0.1

V

I DD

(pA

)

18

Experimental ResultsOperation with VDD down to ~80 mV

5 St

age-

VCO

, f

(MH

z)5

Stag

e-VC

O ,

f (M

Hz)

5 St

age-

VCO

, f

(MH

z)5

Stag

e-VC

O ,

f (M

Hz)

0

10

20

30

40

0 0.5 1 1.5 2Supply Voltage, VDD (V)

501

stag

e -VC

O ,

f (M

Hz)

calculationMeasured

VBS=0

0

10

20

30

40

0 0.5 1 1.5 2Supply Voltage, VDD (V)

501

stag

e -VC

O ,

f (M

Hz)

calculationMeasured

VBS=0

0

10

20

30

40

0 0.5 1 1.5 2Supply Voltage, VDD (V)

501

stag

e -VC

O ,

f (M

Hz)

calculationMeasured

VBS=0

0

10

20

30

40

0 0.5 1 1.5 2Supply Voltage, VDD (V)

501

stag

e -VC

O ,

f (M

Hz)

calculationMeasured

VBS=0

0 0.5 1 1.5 2Supply Voltage, VDD (V)

501

stag

e-VC

O ,

f (M

Hz)

CalculationMeasured

10 0

10 +2

10 -2

10 -4

10 -6

10 +4

10 +2

10 0

10 -2

10 -4

VBS=0

0 0.5 1 1.5 2Supply Voltage, VDD (V)

501

stag

e-VC

O ,

f (M

Hz)

CalculationMeasured

10 0

10 +2

10 -2

10 -4

10 -6

10 +4

10 +2

10 0

10 -2

10 -4

VBS=0

0 0.5 1 1.5 2Supply Voltage, VDD (V)

501

stag

e-VC

O ,

f (M

Hz)

CalculationMeasured

10 0

10 +2

10 -2

10 -4

10 -6

10 +4

10 +2

10 0

10 -2

10 -4

VBS=0

0 0.5 1 1.5 2Supply Voltage, VDD (V)

501

stag

e-VC

O ,

f (M

Hz)

CalculationMeasured

10 0

10 +2

10 -2

10 -4

10 -6

10 +4

10 +2

10 0

10 -2

10 -4

VBS=0

For VDD below ~80 mV loop gain < 1, the Barkhausen condition does not hold and circuit stops oscillating

19

Frequency Control MechanismPropagation delays tPHL, tPLH determine oscillation freq.

N.(tPHL+ tPLH

1f o =)

tPHL, tPLH are determined by the rate of charge and discharge of CL through N and PMOSFET:

CL

ICL

VDD

Vin

VBP

charging

Vout

Vin VouttPLH

CL

ICL

Vin

VBN

dischargingVout

Vin VouttPHL

20

Body Bias To Control Frequency Changing the threshold voltage of N and PMOSFET changes the charge and discharge current.

By changing the body voltage of N and PMOSFET, their threshold voltages Vthare changed:

0

0.1

0.2

0.3

0.4

0.2 0.4 0.6 0.80

Body Bias (V)

V TH

(V)

Lpoly=80nm

In pocketB pocket

Vth = Vtho + γ( VFB + VSB − VFB )

21

Body Bias for Frequency ControlVBS and VDD control f from a few tenths of a Hz to 40 MHz (for a 501 stage oscillator).

Measurement results

10-10

10-8

10-6

10-4

10-2

10+2

-2 -1 0 1

Freq

uenc

y, f

(MH

z)

0.6 V

VDD=0.2 V

Model

Meas.

1.8 V

1 V

1.4100

VBS (V)

10-10

10-8

10-6

10-4

10-2

10+2

-2 -1 0 1

Freq

uenc

y, f

(MH

z)

0.6 V

VDD=0.2 V

Model

Meas.

1.8 V

1 V

1.4100

VBS (V)

10-10

10-8

10-6

10-4

10-2

10+2

-2 -1 0 1

Freq

uenc

y, f

(MH

z)

0.6 V

VDD=0.2 V

Model

Meas.

1.8 V

1 V

1.4100

VBS (V)

10-10

10-8

10-6

10-4

10-2

10+2

-2 -1 0 1

Freq

uenc

y, f

(MH

z)

0.6 V

VDD=0.2 V

Model

Meas.

1.8 V

1 V

1.4100

VBS (V)

10-10

10-8

10-6

10-4

10-2

10+2

-2 -1 0 1

Freq

uenc

y, f

(MH

z)

0.6 V

VDD=0.2 V

Model

Meas.

1.8 V

1 V

1.4100

VBS (V)

10-10

10-8

10-6

10-4

10-2

10+2

-2 -1 0 1

Freq

uenc

y, f

(MH

z)

0.6 V

VDD=0.2 V

Model

Meas.

1.8 V

1 V

1.4100

VBS (V)

10-10

10-8

10-6

10-4

10-2

10+2

-2 -1 0 1

Freq

uenc

y, f

(MH

z)

0.6 V

VDD=0.2 V

Model

Meas.

1.8 V

1 V

1.4100

VBS (V)

Body bias controls fthrough Vth which changes IDSAT

22

Tuning RangeThe frequency of the VCO is tuned by body bias voltage in both reverse and forward directions

0

10

20

30

40

0 0.2 0.4 0.6 0.8Forward Body Bias, (V)

Freq

uenc

y, f

(MH

z)

VDD=1.8 V

1.4 V

1 V

0.6 V

0

10

20

30

40

-1 -0.5 0Reverse Body Bias, (V)

Freq

uenc

y, f

(MH

z) VDD=1.8 V

1.4 V

1 V

0

10

20

30

40

0 0.2 0.4 0.6 0.8Forward Body Bias, (V)

Freq

uenc

y, f

(MH

z)

VDD=1.8 V

1.4 V

1 V

0.6 V

0

10

20

30

40

0 0.2 0.4 0.6 0.8Forward Body Bias, (V)

Freq

uenc

y, f

(MH

z)

VDD=1.8 V

1.4 V

1 V

0.6 V

0

10

20

30

40

-1 -0.5 0Reverse Body Bias, (V)

Freq

uenc

y, f

(MH

z) VDD=1.8 V

1.4 V

1 V

0

10

20

30

40

-1 -0.5 0Reverse Body Bias, (V)

Freq

uenc

y, f

(MH

z) VDD=1.8 V

1.4 V

1 V

0

10

20

30

40

0 0.2 0.4 0.6 0.8Forward Body Bias, (V)

Freq

uenc

y, f

(MH

z)

VDD=1.8 V

1.4 V

1 V

0.6 V

0

10

20

30

40

0 0.2 0.4 0.6 0.8Forward Body Bias, (V)

Freq

uenc

y, f

(MH

z)

VDD=1.8 V

1.4 V

1 V

0.6 V

0

10

20

30

40

-1 -0.5 0Reverse Body Bias, (V)

Freq

uenc

y, f

(MH

z) VDD=1.8 V

1.4 V

1 V

0

10

20

30

40

-1 -0.5 0Reverse Body Bias, (V)

Freq

uenc

y, f

(MH

z) VDD=1.8 V

1.4 V

1 V

0

10

20

30

40

0 0.2 0.4 0.6 0.8Forward Body Bias, (V)

Freq

uenc

y, f

(MH

z)

VDD=1.8 V

1.4 V

1 V

0.6 V

0

10

20

30

40

0 0.2 0.4 0.6 0.8Forward Body Bias, (V)

Freq

uenc

y, f

(MH

z)

VDD=1.8 V

1.4 V

1 V

0.6 V

0

10

20

30

40

-1 -0.5 0Reverse Body Bias, (V)

Freq

uenc

y, f

(MH

z) VDD=1.8 V

1.4 V

1 V

0

10

20

30

40

-1 -0.5 0Reverse Body Bias, (V)

Freq

uenc

y, f

(MH

z) VDD=1.8 V

1.4 V

1 V

e.g., for VDD=1.8 V: fo= 6.538 ×VBS + 30.228 MHz

23

Power Consumption - Ring OscillatorPower consumption is from less than a nW to a few mW and is independent of the number of stages

10-12

10-8

10-4

10+2

-2 -1 0 1

ModelVDD=0.2 V

0.6 V

1 V

1.8 V

Meas.

1001.4 V

10-12

10-8

10-4

10+2

-2 -1 0 1Body Bias, VBS (V)

Pow

er, P

(mW

)

ModelVDD=0.2 V

0.6 V

1 V

1.8 V

Meas.

1001.4 V

2L DD o NC V fP = • • •

2L DD

PHL PLH

C V(t t )

P ⋅=

+

24

LTV Phase Noise Model - Ring Osc.An Impulse Sensitivity Function, Γ(ωt) , describes the time

dependence of φ(t) on noise in Ring Oscillators:

time

VddVdd

2

Ring Oscillator Output

Γ(ωοt)

time

tftr

f

r

tAt

=

∫

Ideal integration

φ(t)

Γ(ωοt)

in(t)

Vout

(A is an indication of waveform asymmetry)

According to LTV model, the conversion of noise in(t) to φ(t) is described by the following system:

25

LTV Phase Noise Model - Ring Osc.In LTV model, DC and rms values of Γ(ωt) determine the

conversion of 1/f and white noise into φ(t), respectively

In ring oscillator, Γdc and Γrms can be shown to be

)1()1(12

22 AA

N +−=Γdc

ηπ

333

2

)1(11

382

AA3

Nrms ++=Γ

ηπ

N = number of stages,

η ≈ 0.75 is a fitting constant.

Therefore, by adjusting the waveform symmetry, A~1, (e.g., using MOSFET’s body bias) it is possible to decrease the effect of 1/f and white noise.

26

LTV Phase Noise Model - Ring Osc.Output spectrum of ring VCO has 2 slopes of 1/f3 and 1/f2 with respect to offset frequency fm.

Up-converted 1/f LF noise

Up-converted white noise noisephase

f1

2m

noisephasef1

3m

f1

3m

S Φ(f m

), dB

c/H

z

log fmfc(VCO)

f1

2m

Corner frequency fc is used as a criteria for 1/f noise up-conversion:

πΦ m 2

2rms

2m

2 2L DD

2nΓ

f= •

8 C V

i ∆fS (f )

C(VCO) C(MO

2dc

2r

S)

ms

Γ

Γ= f f

LTV model gives the phase noise due to white noise in/∆f as:2

27

VBS Effect - 1/f Noise Up-ConversionBody bias also changes the Γdcthrough changing the waveform symmetry, which affects the phase noise.

The 1/f noise in a MOSFET:

KF is reduced with forward bias VBS for a fixed VDD (i. e., 1/f noise is reduced).

fIKi

2DF2

f1

×=

-70

reverse ← VBS (V)→ forward

f=1Hz, VDS=0.6V

Weak inversionStrong inversion

, dB

/Hz

S I/ID2

S I/ID2

S I/ID2

S I/ID2

S I/ID2

S I/ID2

S I/ID2

S I/ID2

-75

-80

-85

-900.80.40-0.4-0.8

Slope ~ -8dB/V

A)(1A)(1

N1

η2πΓ

22dc +−=

10

V DD =1.3 V

10

-1.5 -1 -0.5 0 0.5 1VBS (V)

VDD=1.3 V

10

V DD =1.3 V

10

-1.5 -1 -0.5 0 0.5 1VBS (V)

VDD=1.3 V

10

V DD =1.3 V

10

-1.5 -1 -0.5 0 0.5 1VBS (V)

VDD=1.3 V

10

V DD =1.3 V

10

-1.5 -1 -0.5 0 0.5 1VBS (V)

VDD=1.3 V

10

V DD =1.3 V

10

-1.5 -1 -0.5 0 0.5 1VBS (V)

0

20

40

-1.5 -1 -0.5 0 0.5 1VBS (V)

Freq

uenc

y (M

Hz)

0

4.10-12

DC

Val

ue o

f ISF

,Γ

VDD=1.3V

2.10-12

DC

28

Effect of VDD on Phase NoiseLowering VDD decreases IDand therefore 1/f noise is decreased.

Circuit is designed to provide symmetry at VDD=1.8 V; reducing VDD increases Γdc

Effect of ID dominates that of Γdc; lowering VDD decreases the phase noise.f

IKi DF2

f1

×=2

0

20

40

0 0.5 1 1.5 2VDD (V)

0

VBS=0

5×10-12

1×10-11

Γ

0

20

40

0 0.5 1 1.5 2VDD (V)

0

VBS=0

5×10-12

1×10-11

Γ

0

20

40

0 0.5 1 1.5 2VDD (V)

0

VBS=0

5×10-12

1×10-11

Γ

0

20

40

0 0.5 1 1.5 2VDD (V)

0

VBS=0

5×10-12

1×10-11

Γ

S I, d

BA

/Hz

Reverse VBS

~ID2

VDS=0.6V

Reverse VBS

~ID2

VDS=0.6V

Reverse VBS

~ID2

VDS=0.6V

Reverse VBS

~ID2

VDS=0.6V

Reverse VBS

~ID2

~ID2

VDS=0.6V-170

-190

-210

-230

-250

-270

Reverse VBS

~ID2

~ID2

VDS=0.6V

Reverse VBS

~ID2

~ID2

VDS=0.6V

Reverse VBS

~ID2

~ID2

VDS=0.6V

Reverse VBS

~ID2

~ID2

VDS=0.6V

ID (A)

Reverse VBS

~ID2

~ID2

VDS=0.6V

10-10

-170

-190

-210

-230

-250

-27010-8 10-6 10-4

DC

Val

ue o

f ISF

, D

CD

C V

alue

of I

SF,

DC

DC

Val

ue o

f ISF

, D

CD

C V

alue

of I

SF,

DC

29

VBS Dependence of Phase Noise

Generally the phase noise decreases with forward body bias, because 1/f noise in MOSFET is lower.

Also, the waveform symmetry improves.

Modeling agrees well with the measured results.

-100

-90

-80

-70

-60

-50

-2 -1 0 1Body Bias, VBS (V)

Phas

e N

oise

, dB

c/H

z

ModelMeasured

1kHzVDD =1.3 V

10kHz

30

VDD Dependence of Phase NoiseDecrease in VDD decreases the current ID,

Decrease in ID reduces the 1/f noise, which reduces the phase noise,

Decrease in VDD disturbs the waveform symmetry but the overall phase noise decreases due to decrease in ID.

Modeling agrees well with measurement down to VDD=0.5 V.

-140

-120

-100

-80

-60

-40

0 0.5 1 1.5 2Supply Voltage, VDD (V)

Phas

eN

oise

, dB

c/H

z

Model

Measured

VBS=0 V 1kHz

10kHz

Measurement for VDD<0.5 is possible if N < 501.

31

Measured Phase Noise vs. VDD and VBS

-100

-90

-80

-70

-60

-50

1000 10000

Offset Frequency, fm (Hz)

Phas

e N

oise

, dB

c/H

z

to 0.5

Decrease of VDD from 1.8 V

~1/f3

VBS=0

-110

-100

-90

-80

-70

-60

-50

103 104 105

Offset Frequency, fm Hz

+0.6 Forward- 0.6 ReverseZero Bias

1/f3

VDD=1.3 V

-110

-100

-90

-80

-70

-60

-50

103 104 105

Offset Frequency, fm HzPh

ase

Noi

se, d

Bc/

Hz +0.6 Forward

- 0.6 ReverseZero Bias

1/f3

VDD=1.3 V

-110

-100

-90

-80

-70

-60

-50

103 104 105

Offset Frequency, fm Hz

+0.6 Forward- 0.6 ReverseZero Bias

1/f3

VDD=1.3 V

-110

-100

-90

-80

-70

-60

-50

103 104 105

Offset Frequency, fm HzPh

ase

Noi

se, d

Bc/

Hz +0.6 Forward

- 0.6 ReverseZero Bias

1/f3

VDD=1.3 V

Experimental results show the improvement of phase noise with forward body bias and lowering of VDD.

32

Phase Noise - Weak InversionFor VDD ≤ 0.6 V, this circuit can be used:

VoutVin

VDD

-100

-80

-60

-40

-20

0

0 101 102 103 104 105

0.6 V7.8 MHz

0.3 V58 kHz

White noise

1/f2

-100

-80

-60

-40

-20

0

0 101 102 103 104 105

Offset Frequency, fH (Hz)

Phas

e N

oise

, dB

c /H

z

0.6 V7.8 MHz

0.2 V2.6 kHz

White noise

Weak Inversion

1/f2

VDD=VBS

By reducing the number of stages to 3, the frequency increases to above 1 GHz with no increase in phase noise.

For VDD ≤ 0.6V, phase noise is dominated by white noise.

33

Gated Lateral Bipolar Transistor

n-well n+

G

E C

B

p+

p+p+

n- well

p- substrate

n+

plugLPNP

PMOS

G C BE

VPNP

RERC

E C

G

B

34

GLBT-Based Circuits

~VG

VE

vin

VC

RLVout

CLB

C

G

E

E

B

C

G~

VLO

VRF

VIF

10k50

50

50µF

50mH

10µF

10µF

50mH

50µF~

~

VGA

Mixer

0 1500 300 450 600-55

-45

-35

-35

-15

IF, 0.5MHz

IF, 2MHz

PRF = 0dBmPLO = 0 - 14dBmVG = 0VVE = 0.76 - 0.82V

Signal (RF) Frequency

IF O

utpu

t Pow

er (d

Bm)

35

Polymer Field-Effect Transistor - PFET

SiO2

Gate

Source Draindox

Polymer

L L

Insulator

Gate

Source Drain

dox

Polymer

Active Matrix DisplaysElectronic TagsHigh Voltage DriversSensorsImagers - UV, X-Ray

Large Area DeviceLow Power DeviceSelective SensitivitySimple TechnologyLow Cost Fabrication

36

Alternate Niche Technology

Finished plastic foil, consisting of a 3 inch polyimide substrate and about 50 ICs.

Each circuit contains a programmable code generator together with a variety of components and test circuits.

http://physicsweb.org/article/world/12/3/11http://researchweb.watson.ibm.com/journal/rd/451/dimitrakopoulos.html

37

Charge Transport in PolymersCharge transport in molecule is easy

Between molecules is difficult because of disorder

Transport due to charge hopping between localized states in energy and space

Ordering ⇔ ease of hopping

Structure of polymer ⇔ deposition method

Solution processed ⇔ poor ordering

Vacuum deposited ⇔ good ordering

38

PFET’s Electrical Characteristics

0.02 0.04 0.06 0.080Mobility (cm2/Vs)

0

2

4

6

8

10

12

14

Cou

nts

-2.4

-1.6

-0.8

0

I D (µ

A)

-30-20-100V (V)

VGS,V

-30-26

-100

-20

DS

Pentacene PFETs from one waferD. de Leeuw, et. al., IEEE-IEDM, 293-296, 2002.

Pentacene (top contact)

P. Necliudov, et al., Journal of Applied Physics, Vol. 88(9), pp. 5395-5399, 2000.

P3AT (bottom contact)

O. Marinov et al, Proc. FAN, Vol. 5113 pp. 301-312, 2003.

39

Variations of PFET Characteristics

-2.4µA

-1.6 µA

-0.8 µA

0 µA

ID

-30-20-100

VDS, V

VGS,V-30-26-100

-20

Good PolyFET

The shape of the characteristics varies from sample to sample

• ID depends strongly on VGS

• ID is almost independent on VDS• Significant part of IDis independent of VGS

• The bulk conductance prevails over the field effect

-0.6µA

-0.4 µA

-0.2 µA

0 µA

ID

-30-20-100

VGS,V

-30-20-100

VDS, V

Diode-like TFT

-0.12 µA

-0.08 µA

-0.04 µA

0 µA-30-20-100

VDS, V

ID

-30-20-100

VGS,V

Leaking PolyFET

-0.9µA

-0.6 µA

-0.3 µA

0 µA-30-20-100

VDS, V

ID

-30-20-100

VGS,V

Resistive TFT

40

Charge Buildup Increases the Leakage

010

20300

0.2

0.4

0.6

0.8

1

-VDS, V

Measurement

Time

-ID, µ

A

10sec3min

10min30min

100min

Field-effect current decreases with time

10-9

10-8

10-7

10-6

0.1 1 10 100Measurement Time, min

-ID, A

Increasing the

Leakage current increases with time

The charge buildup:

• Increases VT → ID decreases; and

• Modulates the polymer conductivity

SiO2Gate

S DCharge buildup

41

P3AT-Thin Film TransistorsResearch Project: Microelectronic Laboratory at McMaster University in collaboration with SFU

Active material: A continuous film of a semiconducting polymer made by spin coating

polymer

Gate

DrainSource

Insulator: SiO2

Substrate: n+Si

Gate

polymer

Gate

DrainSource

Insulator: SiO 2

Gate

polymer

Gate

DrainSource

Insulator: SiO2

Substrate: n+Si

Gate

polymer

Gate

DrainSource

Insulator: SiO2

Gate

0

1

2

3

-40-30-20-100

VGS=-40 V

-25 V

-30 V

-35 V

P3HDT

I D(µ

A)

VDS (V)

0.0

0.5

1.0

1.5

-40-30-20-100VDS (V)

I D(µ

A)

VGS=-28 V

-12 V-16 V

-20 V

-24 V

0V

P3HT

P3HT=Poly(3-hexylthiophene) P3HDT=Poly(3-hexadekylthiophene)

42

DC vs. Polymer, Annealing & DopingI D

, A

10-10

10-8

10-6

0.00

01%

Ag

(P3H

DT)

0.00

10%

Ag

(P3H

DT)

0.01

00%

Ag

(P3H

DT)

0.10

00%

Ag

(P3H

DT)

1.00

00%

Ag

(P3H

DT)

10.0

000

% A

g (P

3HD

T)

110100100010000100000

Rat

io, a

.u.

IOFF ION

ON/OFF ratio

Polymer

P3H

TP3

OT

P3D

DT

P3H

DT

118o C

(P3H

DT)

140o C

(P3H

DT)

Ann

eale

d @

Doping

No

Ag

(P3H

DT)

Longer polymer chain ⇒ better PFET

Improper high annealing temperature ⇒ worse PFET

Changing the doping ⇒ indifferent

Polymer and its deposition conditions are the most important factors for PFET fabrication and performance characteristics

43

Recommendations for FabricationRecommendations for fabrication of polymer thin film transistorsPolymers with longer chains (e.g. P3DDT or P3HDT) give better electrical performance – High ON-current, Low OFF-current, High ON/OFF ratio;

Polymer deposition is very important. Solutions with lower concentration of polymer should be preferred;

Higher spin coating speed gives higher on/off ratio.

P3HDT

P3OT10-8

10-7

10-6

10-5

-40-30-20-100

VDS (Volt)-I D

(Am

ps)

-32V

VGS

-32V

-22V

-22V

Polymer type is the most important factor

44

Drain Current ID vs. Temperature

before

after heating

VGS = -32V

-24V

-32V

-26V0

1

2

3

-40-30-20-100

-I D(µ

A)

VDS (V)

P3HDT-C16

0

1

2

23 35 45 55 65Temperature (OC)

I D(µ

A)

saturationlinear

Bias: VGS=22.6V

VDS=15V for saturation region

VDS=5V for linear region

The DC performance of the polymer FET (e.g. ID) decreases at temperatures above 40OC.The degradation is not recoverable.

45

Injection Limit in IDLM - Variations

Si O2

Gate

Source Drain

VDS

VGS

dox

d,VBIPolymer

-2.4µA

-1.6 µA

-0.8 µA

0 µA

ID

-30-20-100

VDS, V

VGS,V-30-26-100

-20

Low disorderHigh VBI

-0.6µA

-0.4 µA

-0.2 µA

0 µA

ID

-30-20-100

VGS,V

-30-20-100

VDS, V

-0.12 µA

-0.08 µA

-0.04 µA

0 µA-30-20-100

VDS, V

ID

-30-20-100

VGS,V

High disorderLow VBI

-0.9µA

-0.6 µA

-0.3 µA

0 µA-30-20-100

VDS, V

ID

-30-20-100

VGS,V

Very high disorderVBI=0

Polymer deposition is an important factorHole injection from

source due to VGS

46

Printing TechnologiesCourtesy of John Rogers, Lucent Technologies, now at Univ. Illinois, UC

Adv. Mat. 11(9), p. 741 (1999) (left)

Science 291, p. 1502 (2003) (bottom)

47

UL Area Printed Plastic CircuitsCollaboration between Lucent and DuPont

4096 transistors6ft2 area3 printed levels

Courtesy of John Rogers, Lucent Technologies, now at Univ. Illinois, UC

APL 82, p. 463 (2003)

48

E-Ink DisplaysPaul Drzaic, director of technology for E Ink demonstrates E Ink’s flexible display prototype

Prototypes - 25-square-inch display area made up of several hundred pixels.

Displays were constructed using two ground-breaking developments

Transistors (from Bell labs) in these circuits are made of plastic materials and are fabricated with a low-cost printing process that uses high-resolution rubber stamps. New materials for electronic ink

49

Electronic Paper

Video screen with the properties of paperThe device is fired by plastic transistors that are flexible, inexpensive to make

Transistors work well enough to constantly refresh the screen to create moving pictures.

http://news.nationalgeographic.com/news/2001/12/1206_TVtransistorpaper1.html

50

Operational StabilityPentacene ring oscillator

tested in air without encapsulation

IEDM 2003, Klauk, Infineon

Stage delay is constant and after ~1,000s decreases

Amplitude increases slightly up to ~3,000s and then drops to 0 at ~10,000s

Supply current ~constant at ~1,000, then increases up to ~10,000s, after which circuit fails

10 sec

3,000 sec

6,000 sec

9,000 sec

11,000 sec

51

The Promise of Plastic TransistorsIntegrated circuits made from polymers could usher in a whole new era in computing.Article by Erick Schonfeld, Business Week, Apr 13, 2001

“Back in 1958, when Jack Kilby and Robert Noyce invented the integrated circuit, its transistors were made from metal and silicon.”

“Today's integrated circuits are still forged from the same materials, even though they contain many more millions of transistors.”

“There's a growing scientific movement afoot to build circuits made from entirely new materials. Forget about the rigid metals of old. Now it's all about plastic.”

http://www.business2.com/articles/web/0,1653,11392,00.html

52

Properties of P3HDT

0.0

0.5

1.0

-20-15-10-50VDS, (V)

|I D|,

(µA

)

-32 V

VGS = -36 V

-24 V

-28 V

P3HDT

1000 rpm

Measured

in dark

Good PFET characteristics

Response to visible light

Good photogain at VDS=2V, VGS=0V of 104

Light has same effect as VGS in ID-VDScurves

1.0

0.5

0.0

-20-15-10-50VDS, (V)

|I D|,

(µA

)

Measured under

visible light

0

-12

VGS = -16 V

VGS = +8 V

-8

P3HDT

1000 rpm

10-11

10-9

10-7

10-5

0.1 1 10 100

|I D|,

(µA

) VGS =-35 V

at dark

VGS=0light on

2

1

P3HT3000 rpm

VGS=0in dark

-5

0

5

10

-40 -20 0 20 40VDS, (V)

|I D|,

(µA

)

VGS=-35 Vin dark

VGS= 0 Vlight on

VGS=0in dark

Trap-limit SCLC

Trap-free SCLC

P3HT3000 rpm

VDS, (V)

53

Research Issues - PFETsStability and reliability

Improved electrical performance with inexpensive processing

improved mobilityreduced off current for higher Ion/Ioff ratioreduced bulk leakage currents

Temperature characteristics ↔ degradation

Theoretical description of charge transport

Explore photodetection capabilities of PFETs

Extension of FET-based models now used

54

Research Issues - VB-FETModels for FET with B as fourth active terminal

include all parasitic effects - other transistors, substrate, forward biasing SB, capacitances and resistancesDC and RF - small- and large-signalLF, RF and phase noise behavior

Four terminal FET is newer technologies

SOI, SiGe, BiCMOS flavoursModified CMOS for improved performance

Effects of thin gate oxide and resulting gate currents

tox=1.7nm

n+ n+n-n-

VG

S D

G

p-substrateLDD MOSFET

0.18 µm Tech.

Spacer

oxide

Overlaptunneling current

------------gate tunneling

current

A

A

A

55

Concluding RemarksInteresting opportunities for non-conventional use of existing devices - body biasing in MOSTs

Significant improvement in gM, fT, fmax, noiseCan also create gated lateral BJT - is almost a circuitNew use for existing technologies with superior performance or finer precision

Non-traditional FET technology discussed -polymer FET

Inexpensive, flexible, suitable for niche applicationsCan be combined with OLEDs or E-Ink for displaysMany interesting research issues remain - materials, interface, reliability, stability, theory, modeling

56

AcknowledgementsJ. De La Hidalga (INAOEP, Puebla), Z.X. Yan (Conexant, Newport Beach), D.S. Malhi (Synposis, Toronto), M. Marin (Montpelier) and S. Naseh, O. Marinov, M. Kazemeini (McMaster University) - collaborators and students for body bias, GLBT, Circuits and PFET work

J. Yu, G. Vamvounis, W. Woods and S. Holdcroft (Simon Fraser University, Vancouver) - collaborators and students for PFET work

NSERC of Canada, Micronet and Canada Research Chair -for financial support

57

Muchas Gracias