noc general concepts andreas ehliar - per karlström
Post on 21-Dec-2015
219 views
TRANSCRIPT
![Page 1: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/1.jpg)
![Page 2: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/2.jpg)
NoC
General conceptsAndreas Ehliar - Per Karlström
![Page 3: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/3.jpg)
Outline
• Background• Some Implementations• Design Issues / Tools• Example Application• Conclusions
![Page 4: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/4.jpg)
Current Situation
Transistors
Time
![Page 5: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/5.jpg)
Current Situation
IP
IP
IP
IP
IP
IP
IP IP
IP IP IP
![Page 6: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/6.jpg)
NOC implementations
• SoCBUS• xPipes• Pleiades• Eclipse• (FPGA)
![Page 7: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/7.jpg)
SoCBUS
![Page 8: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/8.jpg)
Pipes
![Page 9: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/9.jpg)
Pleiades
MEM ALU
FPGA MAC
ALU
DSP
MEM MAC etc.
![Page 10: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/10.jpg)
Eclipse
![Page 11: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/11.jpg)
FPGA
![Page 12: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/12.jpg)
Homogenous NoC
FU
FU
FU
FU
FU
![Page 13: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/13.jpg)
Heterogeneous NoC
FU
FU
FU
FU
FU
MUL
ALU
DSP
![Page 14: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/14.jpg)
Heterogeneous NoC
FU
FU
FU
FUMUL
ALU
DSP
![Page 15: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/15.jpg)
Quality of Service
• Guaranteed latency• Guaranteed bandwidth• Correctness
![Page 16: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/16.jpg)
Design Issues - Signaling
V
t
![Page 17: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/17.jpg)
Design Issues - Clocking
MEM
FPGA
ALU
DSP
![Page 18: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/18.jpg)
Design Issues - Architecture
FU FU
FU FU
FU
FU
FU FU FU
![Page 19: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/19.jpg)
Design Issues - Architecture
FU FU
FU FU
FU
FU
FU FU FU
![Page 20: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/20.jpg)
Design Issues- Errors
Ne/Np
Cost
Error correction
Error detection
![Page 21: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/21.jpg)
Design Issues - Flow Control
![Page 22: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/22.jpg)
Design Issues - Effect of Design
AlgorithmArchitecture
RTLGate
TransistorSilicon
![Page 23: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/23.jpg)
Design Issues - Power Control
![Page 24: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/24.jpg)
![Page 25: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/25.jpg)
Design Issues - Long Wires
• Solving the global interconnect mess– Delay– Bit errors– Repeaters– Clock domains
• Create one optimized solution that can be reused
![Page 26: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/26.jpg)
Design Issues - Long Wires
• Add flip flops to increase clock frequency
• What about ACKs?
NoCRoute
r
NoCRoute
r
![Page 27: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/27.jpg)
Design Issues - Long Wires
• Add flip flops to increase clock frequency
• What about ACKs?
NoCRoute
r
NoCRoute
r
What about bit errors?
![Page 28: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/28.jpg)
Design Issues - Long Wires
• Bit errors on long wires will not be avoidable in the future
• Use error correcting codes– Disadvantage: More wires
• Use parity bits to discover errors– Resend damaged packets– No longer possible to guarantee real-time
performance
![Page 29: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/29.jpg)
Design Issues - Long Wires
• Possibility to create heavily optimized solution– Low voltage signaling– Advanced symbol encoding/decoding– Wave pipelining
![Page 30: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/30.jpg)
Design Issues - Long Wires
• High performance interconnect through wave pipelining– Need very careful analysis
NoCRoute
r
NoCRoute
r
NoCRoute
r
NoCRoute
r
![Page 31: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/31.jpg)
Design Issues - Long Wires
• Wave pipelining performance– 3.45 Ghz signaling on one bit line in 0.25
um– More energy efficient than regular
pipeline– Faster than regular pipeline
• Disadvantage– Much harder to test/verify
![Page 32: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/32.jpg)
System design
• Typical tools– Simulator– Network generator
![Page 33: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/33.jpg)
System design
• What I would want– Graphical frontend to design NoC– C and RTL models of the finished NoC– C API to create C level models of the NoC– Mix C and RTL models in RTL simulator– And of course...
![Page 34: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/34.jpg)
System design
IP cores
![Page 35: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/35.jpg)
Example: Core Router
• SoCBUS Simulation• Study of 16 port core router on a
chip• 16 x 10 Gigabit Ethernet Ports• Prove feasibility of using SoCBUS
![Page 36: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/36.jpg)
Example: Core Router
IPP
FT
PB
OPP
CPU
MU
![Page 37: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/37.jpg)
Example: Core Router
• IPP (Input Packet Processor)– Receive packet from network– Validate Packet/Filter packet– Send lookup request to forwarding table– Send packet to Packet Buffer
• FT (Forwarding Table)– Get IP address from IPP– Perform Lookup and send the output port
to the packet buffer
• OPP (Output Packet Processor)– Send packet to Network
![Page 38: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/38.jpg)
Example: Core Router
• PB (Packet Buffer)– Responsible for packet buffering– Buffers packets until output port
information is received from the forwarding table
• MU (Multicast Unit)– Handle multicast packets
• CPU
![Page 39: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/39.jpg)
Example: Core Router
• Data flow for a single packet
Output Packet
Processor
Forwarding Table
Packet Buffer
Input Packet
Processor
![Page 40: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/40.jpg)
Example: Core Router
• Assumptions:– Each link can transfer 64 bits each clock
cycle– SoCBUS can be clocked at 1.2 Ghz– Packet buffers are “large enough”
![Page 41: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/41.jpg)
• Results for “Internet Mix” packet sizes
Example: Core Router
![Page 42: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/42.jpg)
• Results for minimum size packets
Example: Core Router
![Page 43: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/43.jpg)
Example: Core Router
• Network utilization
![Page 44: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/44.jpg)
Example: Core Router
• Bottleneck in forwarding table access– Current version of SoCBUS creates a
virtual circuit for each request
• Proposal: Extend SoCBUS– Reliable delivery of small (64 bit or less)
packets without setting up a virtual circuit
![Page 45: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/45.jpg)
Example: Core Router
• Conclusion on this application example– Initial concept seems to work in
simulation
• Current work:– Master thesis to test concept in an FPGA
![Page 46: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/46.jpg)
Our Reflections
• Many papers use routers for each connection core– Not every IP core has to have a NoC
Uplink– Probably better to use local shared
buses with a common NoC Uplink– On the Internet, terminals are not
connected directly to routers
• Hard to design a network if the traffic is unknown
![Page 47: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/47.jpg)
Our Reflections
• Research on how to improve NoCs can often be used to improve non-NoC based designs– Communication over long distances– Improved crossbars
• It will be hard to guarantee real-time performance on NoCs
![Page 48: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/48.jpg)
Conclusions
• NoC seems to be a reasonable tradeoff– Similar to how standard cells make it
easier to design chips
• No industry usage (yet?)• As yet, no killer application has
been demonstrated• Next level of abstraction
– IP centric design
![Page 49: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/49.jpg)
Questions/Discussion
• Will future chips have communication patterns favoring NoCs?
![Page 50: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/50.jpg)
References
• Networks on chips: a new SoC paradigm Benini, L.; De Micheli, G.; Computer , Volume: 35 , Issue: 1 , Jan. 2002 Pages:70 - 78
• Powering networks on chips Benini, L.; De Micheli, G.; System Synthesis, 2001. Proceedings. The 14th International Symposium on, 30 Sept.-3 Oct. 2001 Pages:33 – 38
• Addressing the system-on-a-chip interconnect woes through communication-based design Sgroi, M.; Sheets, M.; Mihal, A.; Keutzer, K.; Malik, S.; Rabaey, J.; Sangiovanni-Vincentelli, A.; Design Automation Conference, 2001. Proceedings , 18-22 June 2001 Pages:667 - 672
• On-chip networks: a scalable, communication-centric embedded system design paradigm Henkel, J.; Wolf, W.; Chakradhar, S.; VLSI Design, 2004. Proceedings. 17th International Conference on , 2004 Pages:845 - 851
• Design of a Core Router using the SoCBUS On-chip Network; Jimmy Svensson; LiTH-ISY-EX-04/3562-SE; LiTH
![Page 51: NoC General concepts Andreas Ehliar - Per Karlström](https://reader030.vdocuments.us/reader030/viewer/2022032801/56649d535503460f94a2fe32/html5/thumbnails/51.jpg)
References
• A scalable high-performance computing solution for networks on chips Forsell, M.; Micro, IEEE , Volume: 22 , Issue: 5 , Sept.-Oct. 2002 Pages:46 - 55
• Xpipes: a network-on-chip architecture for gigascale systems-on-chip Bertozzi, D.; Benini, L.; Circuits and Systems Magazine, IEEE , Volume: 4 , Issue: 2 , 2004 Pages:18 - 31
• xpipesCompiler: a tool for instantiating application specific networks on chip Jalabert, A.; Murali, S.; Benini, L.; De Micheli, G.; Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings , Volume: 2 , 16-20 Feb. 2004 Pages:884 - 889 Vol.2
• A wave-pipelined on-chip interconnect structure for networks-on-chips Jiang Xu; Wayne, W. High Performance Interconnects, 2003. Proceedings. 11th Symposium on, Vol., Iss., 20-22 Aug. 2003 Pages: 10- 14
• An on-chip network architecture for hard real time system; Daniel Wiklund; LiU-TEK-LIC-2002:69 LIU