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New Features in the LabVIEW FPGA ModulePublish Date: Mar 09, 2015

Overview

The NI LabVIEW FPGA Module extends the LabVIEW graphical development platform to target FPGAs on NI reconfigurable I/O(RIO) hardware. With every release, the module offers powerful new features for shortening your development time and improvingyour application’s performance. See highlights of features from past and most recent versions of the module.

Table of Contents

New LabVIEW 2013 Features New LabVIEW 2012 Features New LabVIEW 2011 FeaturesNew LabVIEW 2010 FeaturesNew LabVIEW 2009 FeaturesNew LabVIEW 8.6 FeaturesNew LabVIEW 8.5 FeaturesNew LabVIEW 8.2 FeaturesNew LabVIEW 8.0 FeaturesNew LabVIEW 7.1 FeaturesNext Steps

1. New LabVIEW 2013 Features

FPGA High-Performance Linear Algebra Library

Advanced applications such as radio frequency communications, image and audio processing, heat distribution, and cryptographyrequire high-performance algorithms on reconfigurable hardware. The LabVIEW 2013 FPGA Module includes new IP libraries thatgive you the ability to implement FPGA-based high-performance algorithms.Building basic linear algebra operations with specific timing, resource utilization, and throughput requirements in FPGAs can be achallenge. To alleviate this challenge, the LabVIEW 2013 FPGA Module introduces a new IP library that includes the mostcommon linear algebra functions: matrix transpose, dot product, vector norm square, and matrix multiply.

Figure 1. The LabVIEW 2013 FPGA Module includes a new IP library that features the most common linear algebra operations.

These operations serve as basic building blocks for many numerical linear algebra applications, including the solution of linearsystems of equations, linear least square problems, eigenvalue problems, and singular value problems.

Figure 2. The linear algebra library helps you meet your requirements on timing, resources, and throughput.

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Figure 2. The linear algebra library helps you meet your requirements on timing, resources, and throughput.

Instrument Driver FPGA Extensions

Test engineers now have even more options for programming their software-designed instruments such as NI vector signal with the release of This feature combines the compatibility of thetransceivers (VSTs) instrument driver FPGA extensions.

full-featured NI-RFSA and NI-RFSG instrument drivers with the flexibility of the completely open-source LabVIEW sample projectsand instrument design libraries. You can add application-specific IP to your VST FPGA while preserving all of the features of theNI-RFSA and NI-RFSG instrument drivers, and without modifying those APIs. Potential FPGA enhancements include customand/or novel instrument capabilities such as frequency mask triggering, better system integration through hardware-timed deviceunder test (DUT) control and the deterministic triggering of other instruments, accelerated test throughput with FPGA-basedmeasurement acceleration and coprocessing, and even closed-loop or “protocol-aware” tests in which the instrumentationhardware responds to the DUT in real time.

Figure 3. Instrument driver FPGA extensions give you the ability to define custom capabilities for software-designed instruments,while preserving instrument driver functionality and APIs.

Improved Signal Visualization in Debugging Tools

You can use traditional debugging tools such as probes, execution highlighting, breakpoints, and single-stepping when simulatingyour FPGA VIs on the development computer. However, in FPGA designs that involve communication protocols, you need to viewsignals in relation to each other with history data in order to debug the application. The LabVIEW 2013 FPGA Module introduces anew probe based on sampling events that makes it easy to visualize signals on a waveform graph, including relevant timinginformation.

Figure 4. The Sampling Waveform Probe gives you the ability to visualize multiple signals on a waveform graph based onsampling events.

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The Sampling Waveform Probe can use While Loops, For Loops, and FPGA clock domains as sampling event sources. Multiplewires on the block diagram can be associated to those sampling sources so they can be visualized together on the SamplingProbe Watch Window. This new way of visualization makes it easier to analyze multiple signals, especially when they aregenerated within a single-cycle Timed Loop. Extended I/O Simulation and Timing Control Capabilities

LabVIEW FPGA gives you the ability to generate I/O signals to simulate the functionality of real-world I/O. This is traditionally doneby simulating random data or configuring a custom simulation VI. The LabVIEW 2013 FPGA Module offers a more direct path forproviding simulated data to your LabVIEW FPGA VI.

Figure 5. The FPGA Desktop Execution Node facilitates the simulation of FPGA VIs in the development environment.

The FPGA Desktop Execution Node in the LabVIEW 2013 FPGA Module facilitates the simulation of individual FPGA VIs on thedevelopment computer. Based on a configuration dialog, it allows the selection of the appropriate I/O terminals as well as theFPGA clock to be used during the simulation within While Loops, and interaction with models inside of simulation loops using the

. These simulations have increased timing fidelity with respect to primitives,LabVIEW Control Design and Simulation Moduledynamics of DMA FIFOs, and single-cycle Timed Loops.

Figure 6. The FPGA Desktop Execution Node is a configuration-based simulation harness that provides direct access to I/Oterminals and timing resources of the FPGA.

Dynamically Loading Multiple FPGA Interfaces

Dynamically specifying a bitfile at run time gives you the ability to create field upgradeable FPGA-based applications. Traditionally,LabVIEW FPGA users had to use multiple static references using the Open FPGA VI Reference Node to share an FPGA interfacewith multiple bitfiles.

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Figure 7. Before the LabVIEW 2013 FPGA Module, users had to specify static references to manipulate multiple bitfiles. In the LabVIEW 2013 FPGA Module, you can use the new Open Dynamic Bitfile Reference function to select multiple bitfiles atrun time through a given path input. With this function, multiple bitfiles can use a common FPGA interface as long as they sharethe same named set of controls, indicators, and DMA FIFOs. You can use this function to create more flexible host interfaces foradvanced applications.

Figure 8. The LabVIEW 2013 FPGA Module allows the sharing of a single FPGA interface with multiple bitfiles specified at runtime by a path input.

Web-Based Bitfile Deployment

New in 2013, you can update the FPGA bitfile on next-generation NI CompactRIO devices through the Web-Based Configurationand Monitoring interface. This process requires only a Silverlight-enabled web browser and an FPGA bitfile, and makes it easier tomanage the embedded target’s configuration.

Figure 9. Bitfiles for FPGA chips in CompactRIO targets can now be updated through the Web-Based Configuration andMonitoring interface.

2. New LabVIEW 2012 Features

Proven, NI Recommended Architectures for Control and Monitoring ApplicationsThe new LabVIEW project templates and sample projects for NI Single-Board RIO and CompactRIO hardware provideapplications and source code that are designed to scale to a wide variety of control and monitoring applications.

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Figure 1. Sample projects provide proven, reliable architecture starting points for embedded control and monitoring applications.If you’re beginning a new application, the sample projects provide a starting point that can shorten your development time andensure your design is reliable. If you have an existing LabVIEW RIO application that you would like to optimize or improve, youcan use the sample projects to learn LabVIEW FPGA design techniques and architectural best practices that are specific toembedded applications. To learn more about LabVIEW sample projects for control and monitoring applications, watch the

and read the white paper.LabVIEW Real-Time 2012 Sample Projects Webcast LabVIEW Templates and Sample Projects Better Verification of FPGA VI With Execution on Development ComputerCompiling an FPGA VI can take minutes to hours. However, you can test the logic of an FPGA VI before compiling it by runningthe FPGA VI on a development computer with simulated I/O. When you run the FPGA VI on the development computer, you canuse all traditional LabVIEW debugging techniques, such as probes, execution highlighting, breakpoints, and single-stepping. In theLabVIEW 2012 FPGA Module, when you run your FPGA VI on your development PC, you will notice improved fidelity with respectto time when executing multiple single-cycle Timed Loops at the same or different clock rates, and when sharing resourcesbetween two or more single-cycle Timed Loops.

Figure 2. Notice improved fidelity when executing your FPGA VI on a development computer. Floating-Point Support Within LabVIEW FPGAPrevious versions of LabVIEW FPGA required developers to use the fixed-point data type when fractional data was needed. Whilethe fixed-point data type is efficient for hardware-based designs when it comes to speed and resource utilization, it does notprovide the flexibility that the floating-point data type offers. In the LabVIEW 2012 FPGA Module, the single-precision floating-pointdata type is natively supported. Not only does this give users the ability to directly retrieve floating-point data from DMA FIFOs,avoiding an expensive conversion from fixed-point to floating-point on the real-time or Windows host, but it gives DSP designersthe ability to solve linear-algebra problems in LabVIEW FPGA that require a wider dynamic range than what fixed-point or integerdata type provide. Note that although the floating-point data type offers many benefits, it has limited support when used insingle-cycle Timed Loops, and uses significantly more FPGA resources than the fixed-point data type for certain operations.

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Figure 3. Floating-point data type is supported in the LabVIEW 2012 FPGA Module.

For more information on the functions and structures that support the floating-point data type, see Functions That Support the For benchmarks that compare floating-point data type resource.Single Precision Floating-Point Data Type in FPGA VIs

utilization to fixed-point, see .LabVIEW FPGA Floating-Point Data Type Support Array and Cluster Support Within Single-Cycle Timed LoopsIn the LabVIEW 2012 FPGA Module, Boolean, numeric, and comparison operations within single-cycle Timed Loops now supportcluster and array data types. Each primitive operation is parallelized on the FPGA for maximum performance, so you no longerneed to break out each operation individually. This idea originated in the .LabVIEW FPGA Idea Exchange

Figure 4. Cluster and array data type support has been added to single-cycle Timed Loops.

Faster Compilations With Support for LinuxWhen it’s time to compile your LabVIEW FPGA VI, you can iterate faster with new Linux-based FPGA compilation options.Linux-based compilation workers offer substantial performance benefits over Windows-based workers. For large, complex FPGAVIs, NI has seen a significant decrease in compilation times. The performance gains vary based on the specifications of themachine performing the compilation and the size of the FPGA target. Linux-based compilation is available with the LabVIEWFPGA Compile Cloud Service, in addition to remote PC compile works and the LabVIEW FPGA Compile Farm Toolkit. For moreinformation on using Linux machines as a compile worker with the LabVIEW 2012 FPGA Module, see NI LabVIEW FPGA

and . Compilation Options FPGA Compile Worker Performance Benchmarks

Figure 5. Linux-Based FPGA Compilation Options

Higher Clock Rates With Single-Cycle Timed Loops

To compile single-cycle Timed Loops at higher clock rates for large streaming applications, the compiler, under certain conditions,

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To compile single-cycle Timed Loops at higher clock rates for large streaming applications, the compiler, under certain conditions,can remove enable chain for the single-cycle Timed Loops that have no dataflow dependences. Removing this enable chaindecreases routing congestion and improves timing performance. For more information on how to use this new feature, see

. Improving Timing Performance in Large FPGA VIs Array Support With High-Throughput Math NodesWhen designing sophisticated DSP algorithms for high-throughput applications, there is often a need to perform high-throughputmath on arrays. In the LabVIEW 2012 FPGA Module, the High-Throughput Math Nodes support fixed-size array inputs, eliminatingthe need to perform math operations element by element with multiple nodes.

Figure 6. Array Support for High-Throughput Math Functions

Tools for Simplifying IP ReuseWhen designing LabVIEW FPGA algorithms, it’s important to be able to reuse the IP that was created for one application withinanother. Oftentimes, developers find themselves modifying the algorithm they created, so that the FPGA VI compiles in a way thatit meets system requirements, such as execution speed, throughput, or latency. When they want to reuse this algorithm foranother application with different system requirements, they have to make major modifications to the LabVIEW FPGA sourcecode. LabVIEW FPGA IP Builder is a LabVIEW FPGA add-on that gives you the ability to write one algorithm that you can easilycompile for multiple systems for various system requirements, without modifying the source code. For more information, see Get

.Better Performance and Resource Utilization With LabVIEW FPGA IP Builder

Figure7. LabVIEW FPGA IP Builder gives you the ability to design an algorithm in LabVIEW, and compile it for multipleapplications with different performance requirements.

FIFO Improvements for Faster StreamingThe LabVIEW 2012 FPGA Module includes several new features that improve streaming performance with FIFOs for NI FlexRIOtargets for PXI Express. One example is a deeper and wider DMA FIFO. The depth of a DMA FIFO has been increased from 32ksamples to 256k samples, which makes it easier to achieve sustainable rates when streaming data at high rates.Additional improvements to both the DMA FIFO and peer-to-peer FIFO give you the ability to pack small data size elements into a64-bit array before sending to a host. With this new feature, you can obtain higher transfer rates when transferring smaller datasize elements between an FPGA target and host. The number of elements that can be sent with a FIFO depends on the data typeof the elements.

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Figure 8. Write four 16-bit integers in parallel with DMA and peer-to-peer FIFOs for NI FlexRIO targets for PXI Express.

Improved Ability to Create Reusable SubVIsYou now have the option to use a new LabVIEW FPGA construct, the register, to write lightweight, reusable code forcommunication between loops executing in parallel. You can think of the register as a single-element memory implemented withflip-flops. Like globals, you can write and read registers in the same or different clock domains. Similar to FPGA I/O, memories,FIFOs, and clocks, registers can be specified via name controls, which is how you write reusable subVIs with registers.

Figure 9. Register functions are consistent with those for memories and FIFOs.For more information on creating reusable subVIs with LabVIEW FPGA, see For moreUsing Register Items in SubVIs.information on the register, see .Register Items 3. New LabVIEW 2011 Features

More Efficient DevelopmentWith the LabVIEW 2011 FPGA Module, you can now develop your custom logic and Host VI Interface code quicker and moreefficiently. After analyzing the common edit-time operations performed during development, NI improved time-intensive operations,from manipulating host interface functions to opening and closing FPGA VIs.

Figure 1. Module improvements for 2011 reduce the time required for common edit-time operations, which helps you develop yourcustom logic faster.

Learn how these LabVIEW FPGA improvements help reduce development time. Simplified Xilinx CORE Generator IP AccessYou can now drag and drop configurable Xilinx CORE Generator IP blocks directly from the LabVIEW FPGA palette onto the blockdiagram. This streamlines integrating existing communications, math, and even image or video processing IP using the same IPIntegration Node introduced in the LabVIEW 2010 FPGA Module.

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Figure 2. The new Xilinx CORE Generator IP palette makes it easier to access existing FPGA IP that you can use to speed upyour development process.

See details on using the new palette to import Xilinx CORE Generator IP into LabVIEW FPGA. Expanded Options for Cycle-Accurate SimulationIn addition to executing cycle-accurate LabVIEW FPGA application simulations with the Mentor Graphics ModelSim tool, you cannow use the Xilinx iSim environment included with the module. Furthermore, when working with ModelSim simulations, you cannow use LabVIEW to quickly create test benches that use cosimulation to validate logic signal propagation, rather than workingdirectly with HDL.Learn about incorporating cycle-accurate simulation into your LabVIEW FPGA development process. 4. New LabVIEW 2010 Features

IP Integration NodeThe IP Integration Node replaces the HDL Interface Node as a way to integrate third-party IP. Point the node to existing VHDL oruse the built-in compatibility with the Xilinx CORE Generator. This node also automatically creates a simulation model for the IP.Because of this, you can simulate the FPGA diagram on the development computer even if it has CoreGen or straight VHDL. Afteryou have configured the node, you can use the IP just like any other LabVIEW node with inputs and outputs.

Figure 1.

New Compilation Features With Compile Farm/Cloud Software and Build SpecificationsLabVIEW FPGA now uses build specifications to hold properties of compilations for a particular VI. This helps you organize yourcompiles and easily experiment with different Xilinx tool configurations. NI also released a toolkit that you can use to create amultimachine compile farm to offload FPGA compiles from their development machines. NI is experimenting with incorporating thistechnology in the cloud as well. The LabVIEW FPGA Cloud Compile Service, a beta feature for LabVIEW 2010, helps you easilyuse high-end dedicated machines for lengthy FPGA compilations.

Figure 2.

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Cycle-Accurate Simulation With ModelSimLabVIEW 2010 can export the LabVIEW diagram to a set of files that you can analyze in off-the-shelf simulation software. Usingthese methods, you can run cycle-accurate simulations of your LabVIEW FPGA system. Keep in mind that this feature is for thosewho have experience with ModelSim and other FPGA design tools. New and Improved IPLabVIEW 2010 also features new FPGA IP for statistics, such as mean, variance, and standard deviation; a new complex multiply;a matrix-vector multiply; and a complete implementation for the DSP48E MAC block. New memory IP includes a dual-port readand external DRAM support. Finally, there are CLIP improvements including a Configuration Wizard to replace XML creation andVHDL generic support. Dynamic Host Interface WirePreviously, the FPGA interface was difficult to reuse because the FPGA reference wire was strictly typed to the bitfile or VI. As ofLabVIEW 2010, NI has created a dynamic reference wire that you can apply to more easily reuse subVIs you build with FPGAinterface VIs. Keep in mind that the FPGA VI still features a name-based connection to the registers (front panel controls andindicators). You need to make sure these names are also reusable when using this feature. In addition, you can use the legacystrictly typed wire if needed moving forward. 5. New LabVIEW 2009 Features

Early Size and Speed Resource EstimationA large portion of user feedback asked for more estimation of the FPGA resource usage before waiting through an entire compile.With LabVIEW 2009, the compiler shows early size and speed estimates of your design after the “synthesis” step and alerts youwhen this report is ready for viewing. Timing Violation Debugging With Critical-Path HighlightingWhen a timing violation happens, it can be difficult to diagnose the critical path and reduce the timing constraints by programmingmore efficiently and adding pipeline stages. Now, timing violations give you a window that shows every VI in the critical path andhighlights the location of the VI on the FPGA block diagram. The feature even examines subVIs to find the source of a timingviolation. New and Improved High-Throughput Math and Signal-Processing IPNew high-throughput math VIs offer functions, such as sin, cos, and exponential, with the high-speed handshaking protocol thatallows the functions to be used in a single-cycle Timed Loop. You not only have new math functions, but you can use them withother functions in a high-throughput signal chain such as Window, FFT, and resample. Host Integration FeaturesOn the host side, there are two important features in LabVIEW 2009. First, NI has exported a C Interface so that you can talk toyour LabVIEW FPGA program running in hardware with C. The functionality includes read and write registers, DMA, andinterrupts. Second, LabVIEW 2009 features new scaling companion VIs for certain FPGA IP functions. For example, there is a VIthat converts the raw FFT data to a spectrum; a VI that prepares coefficients for FPGA filtering VIs; and a VI that takes frequency,amplitude, and phase and returns values to use with signal generation VIs. 6. New LabVIEW 8.6 Features

Enhanced Behavioral SimulationFor more efficient development, you can use enhanced behavioral simulation to run the code on the development computer andverify functionality before compilation. Additionally, in LabVIEW 8.6, you can use LabVIEW programs that assert test vectors orinteractive values to the I/O nodes in the FPGA. Capture the outputs for verification and visualization of FPGA behavior, run thehost at the same time as the FPGA on the development computer, and get simulated register and DMA transfers between thesimulated FPGA and host code. With these new features, you can create a test bench for the FPGA code and simulate the entiresystem without always compiling to check logic.

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FFT and Other New IPIn LabVIEW 8.6, you can implement fast Fourier transform (FFT) with windowing on the FPGA. This is one of the most requestedfeatures, and NI has delivered a customizable IP core that can execute FFT, inverse FFT, multiple bin sizes, and multiplethroughput settings. NI also released rational resampling, divide, square root, adaptive filters, and fixed-point overflow handlingfunctions. Fixed-Point SupportThe fixed-point data type is now supported on nearly every FPGA function input. This includes support for DMA, memory, filters,PID, FFT, and all arithmetic. Additionally, the fixed-point data type offers an option to add an overflow bit carried on the wire. NIwill continue to enhance fixed-point support in the future to work with resource-constrained targets. Component-Level IP (CLIP)CLIP is a new way to import and use external IP written in a hardware description language (HDL). Implementations instantiatedwith CLIP run in parallel with the LabVIEW diagram, and you communicate to them through user-created I/O nodes. With somehardware targets, you can use CLIP to talk directly to I/O pins. CLIP functions open the FPGA platform further to include all typesof IP, which may be better suited to run in parallel rather than in data flow like the current HDL Interface Node runs. 7. New LabVIEW 8.5 Features

FPGA Project WizardThe new FPGA Project Wizard helps you create a complete LabVIEW project with the FPGA target and I/O configured and readyto program. Because it can directly link to the existing FPGA Wizard, you can quickly generate functional code for analog anddigital I/O, counter, and quadrature encoder measurements. The FPGA Project Wizard is enhanced with new DMA options forFPGA and host code generation.

Figure 1.

Control, Filtering, and Signal-Generation IPThe LabVIEW FPGA Module 8.5 includes new IP in the FPGA palette as well as enhanced existing IP for improved resource useon the FPGA.

Control: Included in the LabVIEW PID and Fuzzy Logic Toolkit, the PID block in FPGA now works with multiple channels, soyou can input an array of channels into the same PID logic on the FPGA. This enhancement is especially important forhigh-channel-count applications. The number of possible channels rose from eight to 256 for a 1M gate target. Additionally, thesingle-channel benchmark is three times faster and uses almost 20 percent fewer FPGA resources.Filtering: All filters are also compatible with multiple channels. Additionally, LabVIEW FPGA includes a new notch filter,rounding out the existing Butterworth highpass and lowpass filters.Signal generation: In addition to the existing sine generator, LabVIEW FPGA now features a square wave generator andnoise generators (Gaussian and white).

Modularity and Code Reuse Features

I/O name controls: Put I/O nodes, methods, and properties inside subVIs to specify the I/O item through a wire.Clock controls: Use a wire to specify which clock, such as an onboard or derived clock, to use in a particular single-cycleTimed Loop.

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Figure 2.Enhanced Feedback Node: Place a Feedback Node anywhere in a block diagram to escape the context of a loop. AFeedback Node can be useful for state storage or pipelining and now works anywhere, including subVIs.

LabVIEW Statechart ModuleNI now offers additional ways to program FPGAs graphically. Many designers prefer using statecharts to represent the systemthey want to build. With this new module supporting LabVIEW FPGA, you can not only represent FPGA-based systems withstatecharts but also program them with the same visual paradigm. Pioneer-Level Support for Fixed-Point Data TypeThere is a new fixed-point data type in LabVIEW that is especially useful for FPGA programming. Previously, LabVIEW FPGAsupported only integers. However, with support for new fixed-point data types, you can bring fractional numbers and arbitrarybit-width data types to FPGA programming. LabVIEW 8.5 features fixed-point support for a small number of primitive math andcomparison functions. Future releases may expand support for this important data type. 8. New LabVIEW 8.2 Features

FPGA Math and Analysis IPThe LabVIEW FPGA Module 8.2 provides new native analysis functions so you can reuse code for basic signal processing andcontrol functionalities common to FPGAs. This new IP includes the following:

Direct current (DC) and root-mean-square (RMS) measurements that calculate the DC, RMS, sum, mean square, and/or square sum values of a signalA Butterworth filter, for input signals, that is configurable using the Express VI A period measurement that calculates the period of an evenly sampled periodic signal using threshold crossing detection

FPGA WizardYou can design FPGA I/O and timing for your intelligent data acquisition applications with the FPGA Wizard. Using thisconfiguration-based wizard, you can select the timing and synchronization between your FPGA device and host VI. After selectingyour timing, you can configure your analog, digital, counter, or quadrature encoder I/O. When you have configured your I/O, youcan save your configuration and generate basic FPGA code and host code. You can then incorporate additional code to completeyour application functions such as control algorithms, data logging, or data networking.

Figure 1.New Memory VIs

With the new memory read and write interface, you can access all 80 KB of memory on 1M gate devices and all 190 KB of

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With the new memory read and write interface, you can access all 80 KB of memory on 1M gate devices and all 190 KB ofmemory on 3M gate devices. You can use memory to store data for waveform generation or data logging without using arrays thatinefficiently use FPGA gates. 9. New LabVIEW 8.0 Features

LabVIEW ProjectWith a LabVIEW project, you can not only target and open VIs in LabVIEW for Windows and LabVIEW FPGA, LabVIEWReal-Time, and other LabVIEW modules simultaneously but also develop LabVIEW FPGA applications. A LabVIEW project canhelp you create and manage all FPGA resources, including:

VIsFPGA I/OCustom clocksCompactRIO configurationsFPGA FIFOs

Figure 1.

DMA Data TransfersThe LabVIEW FPGA Module 8.0 DMA capabilities eliminate throughput limitations between the FPGA device and host. AlthoughFPGAs on RIO devices can run at rates up to 20 MHz, the fastest data-streaming rate without DMA is approximately 1 MB/s. Themodule implements DMA on all NI R Series and CompactRIO devices for at least a 20 times increase in data-streaming ratesbetween the FPGA and a host application compared to other implementations such as using interrupt requests.DMA provides a direct data-to-RAM link on the host machine. Relying on the host processor to stream data from the device to thehost often leads to latencies and causes a data transfer bottleneck. Using interrupt requests also consumes processor clockcycles and increases the overall load on a host CPU. With LabVIEW 8.0, you gain more efficient device-to-host and host-to-devicedata transfers that bypass the CPU, creating a higher performance data acquisition system for all applications.To use DMA, simply create two memory buffers: one in memory on the FPGA device and another in memory on the hostprocessor. LabVIEW efficiently and transparently transfers data over the PCI bus. The module uses FPGA FIFOs configured forDMA to write and read to DMA memory and uses FPGA invoke methods on the host side to create, write, and read from hostmemory. DMA significantly enhances RIO hardware for applications such as buffered intelligent data acquisition, communicationdevice digital streaming, in-vehicle data acquisition, and online machine condition monitoring.

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Figure 2.

Drag-and-Drop FPGA I/OWith LabVIEW FPGA, you can quickly access RIO device I/O through specific device I/O functions. (However, the LabVIEWFPGA function palettes mentioned in this document are specific to FPGA execution targets and contain functions available onlywhen targeted to an FPGA device or FPGA device emulator.) The module gives you direct single-point access to analog anddigital I/O on NI RIO hardware. With the LabVIEW FPGA Module 8.0, you can directly drag and drop I/O from the LabVIEW projectwindow onto the block diagram of your FPGA VI.The module offers many device I/O functions, including:

Analog inputAnalog outputDigital inputDigital outputDigital port inputDigital port outputI/O Method NodeI/O Property Node

Figure 3.

10. New LabVIEW 7.1 Features

Single-Cycle Timed LoopThe LabVIEW Timed-Loop structure executes a loop at the period you specify. Use the Timed Loop to develop VIs with multiratetiming capabilities, precise timing, and feedback generation on loop execution or to dynamically change timing characteristics orseveral execution priority levels. The LabVIEW FPGA single-cycle Timed Loop is a specialized Timed Loop with which you candevelop LabVIEW FPGA applications as efficiently (in terms of speed and space) as hand-coded HDL programming. Thesingle-cycle Timed Loop is similar to a clocked process in VHDL. All of the LabVIEW code in the loop is combinatorial logic on theFPGA, where inputs are from components such as digital input functions, controls, or left-shift registers and outputs are digitaloutput functions, indicators, and right-shift registers. It is easy to take advantage of a single-cycle Timed Loop—use it as you do astandard While Loop.The single-cycle Timed Loop ensures that all code within the loop executes in a single clock cycle (25 ns). Although there aresome limitations to the single-cycle Timed Loop, such as ensuring that all the code inside it can execute within a clock cycle, usingit can result in extremely efficient code for executing digital I/O and simple logic and signal processing. HDL Interface NodeYou can integrate existing HDL IP directly into a LabVIEW FPGA VI using the HDL Interface Node and represent this code as asingle function block within LabVIEW. You then can reuse this code within the same application or in other applications using thesame function block. If you have a block of HDL code to use in an FPGA VI, you can either enter your VHDL code directly into theHDL Interface Node or refer to external .vhd files rather than rewriting the code in LabVIEW.

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Figure 1.11. Next Steps

Evaluate LabVIEW Real-Time and LabVIEW FPGA programming with the NI Embedded Software Evaluation KitLearn how to upgrade your NI software in the most cost-effective way with the Upgrade AdvisorPurchase the LabVIEW FPGA Module now The registered trademark Linux® is used pursuant to a sublicense from LMI, the exclusive licensee of Linus Torvalds, owner of themark on a worldwide basis.